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-rw-r--r--arch/arm/boards/friendlyarm-mini2440/Kconfig34
-rw-r--r--arch/arm/boards/friendlyarm-mini2440/Makefile3
-rw-r--r--arch/arm/boards/friendlyarm-mini2440/config.h118
-rw-r--r--arch/arm/boards/friendlyarm-mini2440/env/boot/nand4
-rw-r--r--arch/arm/boards/friendlyarm-mini2440/env/config-board16
-rw-r--r--arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand6
-rw-r--r--arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S42
-rw-r--r--arch/arm/boards/friendlyarm-mini2440/mini2440.c342
8 files changed, 0 insertions, 565 deletions
diff --git a/arch/arm/boards/friendlyarm-mini2440/Kconfig b/arch/arm/boards/friendlyarm-mini2440/Kconfig
deleted file mode 100644
index feb905e96e..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-
-if MACH_MINI2440
-
-config MINI2440_VIDEO
- bool
- select VIDEO
- select DRIVER_VIDEO_S3C24XX
-
-config MINI2440_VIDEO_N35
- bool "Support N35 display (240x320)"
- select MINI2440_VIDEO
- help
- This adds support for NEC 3.5 inch TFT display,
- the most common one used with MINI2440 board.
-
-config MINI2440_VIDEO_A70
- bool "Support A70 display (800x480)"
- select MINI2440_VIDEO
- help
- This adds support for Innolux 7.0 inch TFT display.
-
-config MINI2440_VIDEO_SVGA
- bool "Support SVGA video adapter"
- select MINI2440_VIDEO
- help
- This adds support for MINI2440 SVGA (1024x768) video output adapter.
-
-config MINI2440_VIDEO_W35
- bool "Support W35 display (320x240)"
- select MINI2440_VIDEO
- help
- This adds support for Sharp 3.5 inch TFT display.
-
-endif
diff --git a/arch/arm/boards/friendlyarm-mini2440/Makefile b/arch/arm/boards/friendlyarm-mini2440/Makefile
deleted file mode 100644
index da3520cc81..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-
-obj-y += mini2440.o
-lwl-y += lowlevel_init.o
diff --git a/arch/arm/boards/friendlyarm-mini2440/config.h b/arch/arm/boards/friendlyarm-mini2440/config.h
deleted file mode 100644
index 86c78e54f6..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/config.h
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/**
- * @file
- * @brief Global defintions for the ARM S3C2440 based mini2440 CPU card
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/**
- * The external clock reference is a 12.00 MHz crystal
- */
-#define S3C24XX_CLOCK_REFERENCE 12000000
-
-/**
- * Define the main clock configuration to be used in register CLKDIVN
- *
- * We must limit the frequency of the connected SDRAMs with the clock ratio
- * setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 405Mhz:102MHz:51MHz
- */
-#define BOARD_SPECIFIC_CLKDIVN 0x05
-
-/**
- * Define the MPLL configuration to be used in register MPLLCON
- *
- * We want the MPLL to run at 405.0 MHz
- */
-#define BOARD_SPECIFIC_MPLL ((0x7f << 12) + (2 << 4) + 1)
-
-/**
- * Define the UPLL configuration to be used in register UPLLCON
- *
- * We want the UPLL to run at 48.0 MHz
- */
-#define BOARD_SPECIFIC_UPLL ((0x38 << 12) + (2 << 4) + 2)
-
-/*
- * Flash access timings
- * Tacls = 0ns (but 20ns data setup time)
- * Twrph0 = 25ns (write) 35ns (read)
- * Twrph1 = 10ns (10ns data hold time)
- * Read cycle time = 50ns
- *
- * Assumed HCLK is 100MHz
- * Tacls = 1 (-> 20ns)
- * Twrph0 = 3 (-> 40ns)
- * Twrph1 = 1 (-> 20ns)
- * Cycle time = 80ns
- */
-#define MINI2440_TACLS 1
-#define MINI2440_TWRPH0 3
-#define MINI2440_TWRPH1 1
-
-/* needed in the generic NAND boot code only */
-#ifdef CONFIG_S3C_NAND_BOOT
-# define BOARD_DEFAULT_NAND_TIMING \
- CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0, MINI2440_TWRPH1)
-#endif
-
-/*
- * Needed in the generic SDRAM boot code only
- *
- * SDRAM configuration
- * Two types of SDRAM devices are common on mini2440:
- * - Two devices of HY57V561620 to form 64 MiB in bank 6 only
- * - http://friendlyarm.net/dl.php?file=HY57V561620.pdf
- * - Two devices of MT48LC16M16 to form 64 MiB in bank 6 only
- * - http://friendlyarm.net/dl.php?file=MT48LC16M16.pdf
-
- * Most of the time the CPU is specified for 400 MHz only. As the CPU frequency
- * and the SDRAM frequency are fix coupled by 4:1, the SDRAM runs at HCLCK.
- * So, we need a 100 MHz timing setup with CL=2 for the SDRAMs.
- */
-
-/*
- * - ST7/WS7/DW7: reserved, this SDRAM bank is not used
- * - ST6/WS6/DW6: 32 bit data bus (for SDRAM usage)
- * - ST5/WS5/DW5: reserved, to be set by the board init code
- * - ST4/WS4/DW4: reserved, to be set by the board init code
- * - ST3/WS3/DW3: reserved, to be set by the board init code
- * - ST2/WS2/DW2: reserved, to be set by the board init code
- * - ST1/WS1/DW1: reserved, to be set by the board init code
- * - DW0: not to be changed
- */
-#define BOARD_SPECIFIC_BWSCON ((0x3 << 28) | (0x2 << 24) | 0x333330)
-/*
- * - MT = 11 (= sync dram type)
- * - Trcd = 00 (= CL2)
- * - SCAN = 01 (= 9 bit columns)
- */
-#define BOARD_SPECIFIC_BANKCON6 ((0x3 << 15) + (0x0 << 2) + (0x1))
-#define BOARD_SPECIFIC_BANKCON7 0 /* disabled */
-/*
- * SDRAM refresh settings
- * - REFEN = 1 (= refresh enabled)
- * - TREFMD = 0 (= auto refresh)
- * - Trp = 00 (= 2 RAS precharge clocks)
- * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
- * - Refresh = 2^11 + 1 - 100 * 7.8 = 2049 - 780 = 1269
- */
-#define BOARD_SPECIFIC_REFRESH ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 1269)
-/*
- * SDRAM banksize
- * - BURST_EN = 1 (= burst mode enabled)
- * - SCKE_EN = 1 (= SDRAM SCKE enabled)
- * - SCLK_EN = 1 (= clock active only during accesses)
- * - BK67MAP = 001 (= 64 MiB)
- */
-# define BOARD_SPECIFIC_BANKSIZE ((1 << 7) + (1 << 5) + (1 << 4) + 1)
-/*
- * SDRAM mode register
- * CL = 010 (= 2 clocks)
- */
-# define BOARD_SPECIFIC_MRSRB6 (0x2 << 4)
-# define BOARD_SPECIFIC_MRSRB7 0 /* not used */
-
-#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/friendlyarm-mini2440/env/boot/nand b/arch/arm/boards/friendlyarm-mini2440/env/boot/nand
deleted file mode 100644
index e0ef904432..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/env/boot/nand
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/sh
-
-global.bootm.image="/dev/nand0.kernel.bb"
-global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs"
diff --git a/arch/arm/boards/friendlyarm-mini2440/env/config-board b/arch/arm/boards/friendlyarm-mini2440/env/config-board
deleted file mode 100644
index 3e07a015b0..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/env/config-board
+++ /dev/null
@@ -1,16 +0,0 @@
-#!/bin/sh
-
-# board defaults, do not change in running system. Change /env/config
-# instead
-
-global.linux.bootargs.console="console=ttySAC0,115200"
-
-#
-# "mini2440" kernel parameter
-# 0 .. 9 = screen type
-# b = backlight enabled
-# t = touch enabled
-# c = camera enabled
-# Note: can be "minit2440= " if nothing of these components are connected
-#
-global.linux.bootargs.base="mini2440=6tb"
diff --git a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand b/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand
deleted file mode 100644
index b51104ad76..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-
-mtdparts="256k(nand0.barebox),128k(nand0.bareboxenv),1536k(nand0.kernel),-(nand0.root)"
-kernelname="nand"
-
-mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S b/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S
deleted file mode 100644
index 43bf49c12c..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Low level initialization for the FriendlyARM mini2440 board
- */
-
-#include <config.h>
-#include <linux/sizes.h>
-#include <mach/s3c-iomap.h>
-#include <asm/barebox-arm-head.h>
-
- .section ".text_bare_init.barebox_arm_reset_vector","ax"
-
-/* ------------------------------------------------------------------------ */
-
-.globl barebox_arm_reset_vector
-barebox_arm_reset_vector:
- bl arm_cpu_lowlevel_init
-
- bl s3c24x0_disable_wd
-
- /* skip everything here if we are already running from SDRAM */
- cmp pc, #S3C_SDRAM_BASE
- blo 1f
- cmp pc, #S3C_SDRAM_END
- bhs 1f
-
- b out
-
-/* we are running from NOR or NAND/SRAM memory. Do further initialisation */
-1:
- bl s3c24x0_pll_init
-
- bl s3c24x0_sdram_init
-
-#ifdef CONFIG_S3C_NAND_BOOT
-/* up to here we are running from the internal SRAM area */
- bl s3c24x0_nand_boot
-#endif
-out:
- mov r0, #S3C_SDRAM_BASE
- mov r1, #SZ_32M
- mov r2, #0
- b barebox_arm_entry
diff --git a/arch/arm/boards/friendlyarm-mini2440/mini2440.c b/arch/arm/boards/friendlyarm-mini2440/mini2440.c
deleted file mode 100644
index 413537d247..0000000000
--- a/arch/arm/boards/friendlyarm-mini2440/mini2440.c
+++ /dev/null
@@ -1,342 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/*
- * Copyright (C) 2010 Marek Belisko <marek.belisko@open-nandra.com>
- *
- * Based on a9m2440.c board init by Juergen Beisert, Pengutronix
- */
-
-#include <common.h>
-#include <driver.h>
-#include <init.h>
-#include <generated/mach-types.h>
-#include <partition.h>
-#include <platform_data/eth-dm9000.h>
-#include <nand.h>
-#include <mci.h>
-#include <fb.h>
-#include <asm/armlinux.h>
-#include <asm/sections.h>
-#include <io.h>
-#include <gpio.h>
-#include <mach/bbu.h>
-#include <mach/iomux.h>
-#include <mach/s3c-iomap.h>
-#include <mach/devices-s3c24xx.h>
-#include <mach/s3c24xx-nand.h>
-#include <mach/s3c-generic.h>
-#include <mach/s3c-mci.h>
-#include <mach/s3c24xx-fb.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-static struct s3c24x0_nand_platform_data nand_info = {
- .nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
- MINI2440_TWRPH1),
- .flash_bbt = 1, /* same as the kernel */
-};
-
-/*
- * dm9000 network controller onboard
- * Connected to CS line 4 and interrupt line EINT7,
- * data width is 16 bit
- * Area 1: Offset 0x300...0x303
- * Area 2: Offset 0x304...0x307
- */
-static struct dm9000_platform_data dm9000_data = {
- .srom = 1,
-};
-
-static struct s3c_mci_platform_data mci_data = {
- .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .gpio_detect = 232, /* GPG8_GPIO */
- .detect_invert = 0,
-};
-
-static struct fb_videomode s3c24x0_fb_modes[] = {
-#ifdef CONFIG_MINI2440_VIDEO_N35
- {
- .name = "N35",
- .refresh = 60,
- .xres = 240,
- .left_margin = 21,
- .right_margin = 38,
- .hsync_len = 6,
- .yres = 320,
- .upper_margin = 4,
- .lower_margin = 4,
- .vsync_len = 2,
- .pixclock = 115913,
- .sync = FB_SYNC_USE_PWREN,
- .vmode = FB_VMODE_NONINTERLACED,
- },
-#endif
-#ifdef CONFIG_MINI2440_VIDEO_A70
- {
- .name = "A70",
- .refresh = 50,
- .xres = 800,
- .left_margin = 40,
- .right_margin = 40,
- .hsync_len = 48,
- .yres = 480,
- .upper_margin = 29,
- .lower_margin = 3,
- .vsync_len = 3,
- .pixclock = 41848,
- .sync = FB_SYNC_USE_PWREN | FB_SYNC_DE_HIGH_ACT,
- .vmode = FB_VMODE_NONINTERLACED,
- },
-#endif
-#ifdef CONFIG_MINI2440_VIDEO_SVGA
- {
- .name = "SVGA",
- .refresh = 24,
- .xres = 1024,
- .left_margin = 1,
- .right_margin = 2,
- .hsync_len = 2,
- .yres = 768,
- .upper_margin = 200,
- .lower_margin = 16,
- .vsync_len = 16,
- .pixclock = 40492,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_DE_HIGH_ACT
- /* | FB_SYNC_SWAP_HW */ /* FIXME maybe */ ,
- .vmode = FB_VMODE_NONINTERLACED,
- },
-#endif
-#ifdef CONFIG_MINI2440_VIDEO_W35
- {
- .name = "W35",
- .refresh = 60,
- .xres = 320,
- .left_margin = 68,
- .right_margin = 66,
- .hsync_len = 4,
- .yres = 240,
- .upper_margin = 4,
- .lower_margin = 4,
- .vsync_len = 9,
- .pixclock = 115913,
- .sync = FB_SYNC_USE_PWREN | FB_SYNC_CLK_INVERT,
- .vmode = FB_VMODE_NONINTERLACED,
- },
-#endif
-};
-
-static struct s3c_fb_platform_data s3c24x0_fb_data = {
- .mode_list = s3c24x0_fb_modes,
- .mode_cnt = sizeof(s3c24x0_fb_modes) / sizeof(struct fb_videomode),
- .bits_per_pixel = 16,
- .passive_display = 0,
-};
-
-static const unsigned pin_usage[] = {
- /* address bus, used by NOR, SDRAM */
- GPA1_ADDR16,
- GPA2_ADDR17,
- GPA3_ADDR18,
- GPA4_ADDR19,
- GPA5_ADDR20,
- GPA6_ADDR21,
- GPA7_ADDR22,
-
- GPA8_ADDR23_GPIO | GPIO_IN,
- GPA9_ADDR24, /* BA0 */
- GPA10_ADDR25, /* BA1 */
- GPA11_ADDR26_GPIO | GPIO_IN, /* not connected */
-
- /* DM9000 requirements */
- GPA15_NGCS4,
- GPF7_EINT7,
-
- /* de-activate the speaker */
- GPB0_GPIO | GPIO_OUT | GPIO_VAL(0),
-
- /* SD socket */
- GPE5_SDCLK,
- GPE6_SDCMD,
- GPE7_SDDAT0,
- GPE8_SDDAT1,
- GPE9_SDDAT2,
- GPE10_SDDAT3,
- GPG8_GPIO | GPIO_IN, /* change detection */
- GPH8_GPIO | GPIO_IN, /* write protection sense */
-
- /* NAND requirements */
- GPA17_CLE,
- GPA18_ALE,
- GPA19_NFWE,
- GPA20_NFRE,
- GPA21_NRSTOUT,
- GPA22_NFCE,
-
- /* Video out */
- GPC0_LEND,
- GPC1_VCLK,
- GPC2_VLINE,
- GPC3_VFRAME,
- GPC4_VM,
- GPC5_LPCOE,
- GPC6_LPCREV,
- GPC7_LPCREVB,
- GPG4_LCD_PWREN,
-
- GPC8_VD0,
- GPC9_VD1,
- GPC10_VD2,
- GPC11_VD3,
- GPC12_VD4,
- GPC13_VD5,
- GPC14_VD6,
- GPC15_VD7,
- GPD0_VD8,
- GPD1_VD9,
- GPD2_VD10,
- GPD3_VD11,
- GPD4_VD12,
- GPD5_VD13,
- GPD6_VD14,
- GPD7_VD15,
- GPD8_VD16,
- GPD9_VD17,
- GPD10_VD18,
- GPD11_VD19,
- GPD12_VD20,
- GPD13_VD21,
- GPD14_VD22,
- GPD15_VD23,
-
- /* K6 or CON12, pin 6, external pull up */
- GPG11_EINT19 | GPIO_IN,
- /* K5 or CON12, pin 5*/
- GPG7_EINT15 | GPIO_IN,
- /* K4 or CON12, pin 4 */
- GPG6_EINT14 | GPIO_IN,
- /* K3 or CON12, pin 3 */
- GPG5_EINT13 | GPIO_IN,
- /* K2 or CON12, pin 2 */
- GPG3_EINT11 | GPIO_IN,
- /* K1 or CON12, pin 1, external pull up */
- GPG0_EINT8 | GPIO_IN,
-
- /* LED 1 1=off */
- GPB5_GPIO | GPIO_OUT | GPIO_VAL(1),
- /* LED 2 1=off */
- GPB6_GPIO | GPIO_OUT | GPIO_VAL(1),
- /* LED 3 1=off */
- GPB7_GPIO | GPIO_OUT | GPIO_VAL(1),
- /* LED 4 1=off */
- GPB8_GPIO | GPIO_OUT | GPIO_VAL(1),
-
- /* camera interface (ignore it) */
- GPJ0_GPIO | GPIO_IN,
- GPJ1_GPIO | GPIO_IN,
- GPJ2_GPIO | GPIO_IN,
- GPJ3_GPIO | GPIO_IN,
- GPJ4_GPIO | GPIO_IN,
- GPJ5_GPIO | GPIO_IN,
- GPJ6_GPIO | GPIO_IN,
- GPJ7_GPIO | GPIO_IN,
- GPJ8_GPIO | GPIO_IN,
- GPJ9_GPIO | GPIO_IN,
- GPJ10_GPIO | GPIO_IN,
- GPJ11_GPIO | GPIO_IN,
- GPJ12_GPIO | GPIO_IN,
-
- /* I2C bus */
- GPE14_IICSCL, /* external pull up */
- GPE15_IICSDA, /* external pull up */
-
- GPA12_NGCS1, /* CON5, pin 7 */
- GPA13_NGCS2, /* CON5, pin 8 */
- GPA14_NGCS3, /* CON5, pin 9 */
- GPA16_NGCS5, /* CON5, pin 10 */
-
- /* UART2 (spare) */
- GPH4_TXD1,
- GPH5_RXD1,
-
- /* UART3 (spare) */
- GPH6_TXD2,
- GPH7_RXD2,
-};
-
-static int mini2440_mem_init(void)
-{
- arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size());
-
- return 0;
-}
-mem_initcall(mini2440_mem_init);
-
-static int mini2440_devices_init(void)
-{
- uint32_t reg;
- int i;
-
- /* ----------- configure the access to the outer space ---------- */
- for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
- s3c_gpio_mode(pin_usage[i]);
-
- reg = readl(S3C_BWSCON);
-
- /* CS#4 to access the network controller */
- reg &= ~0x000f0000;
- reg |= 0x000d0000; /* 16 bit */
- writel(0x1f4c, S3C_BANKCON4);
-
- writel(reg, S3C_BWSCON);
-
- /* release the reset signal to external devices */
- reg = readl(S3C_MISCCR);
- reg |= 0x10000;
- writel(reg, S3C_MISCCR);
-
- s3c24xx_add_nand(&nand_info);
-
- add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304,
- IORESOURCE_MEM_16BIT, &dm9000_data);
-#ifdef CONFIG_NAND
- /* ----------- add some vital partitions -------- */
- devfs_del_partition("self_raw");
- devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
- dev_add_bb_dev("self_raw", "self0");
-
- devfs_del_partition("env_raw");
- devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
- dev_add_bb_dev("env_raw", "env0");
-
- s3c24x0_bbu_nand_register_handler();
-#endif
- s3c24xx_add_mci(&mci_data);
- s3c24xx_add_fb(&s3c24x0_fb_data);
- s3c24xx_add_ohci();
- armlinux_set_architecture(MACH_TYPE_MINI2440);
-
- return 0;
-}
-
-device_initcall(mini2440_devices_init);
-
-static int mini2440_console_init(void)
-{
- /*
- * configure the UART1 right now, as barebox will
- * start to send data immediately
- */
- s3c_gpio_mode(GPH0_NCTS0);
- s3c_gpio_mode(GPH1_NRTS0);
- s3c_gpio_mode(GPH2_TXD0);
- s3c_gpio_mode(GPH3_RXD0);
-
- barebox_set_model("Friendlyarm mini2440");
- barebox_set_hostname("mini2440");
-
- s3c24xx_add_uart1();
- return 0;
-}
-
-console_initcall(mini2440_console_init);