1 files changed, 1132 insertions, 0 deletions
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c b/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c
new file mode 100644
index 0000000000..54c8442673
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c
@@ -0,0 +1,1132 @@
+/*
+ * Copyright 2018 InnoComm Mobile Technology Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+
+#define DDR_ONE_RANK
+#include <soc/imx8m/lpddr4_define.h>
+
+#include "lowlevel.h"
+
+static struct dram_cfg_param ddr_ddrc_cfg_1g_2ch1cs15r10cx32[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304,0x1},
+	{0x3d400030,0x1},
+	{0x3d400000,0xa1080020},
+	{0x3d400020,0x223},
+	{0x3d400024,0x2ee00},
+	{0x3d400064,0x49006c},
+	{0x3d4000d0,0xc0030495},
+	{0x3d4000d4,0x770000},
+	{0x3d4000dc,0xc40024},
+	{0x3d4000e0,0x310000},
+	{0x3d4000e8,0x66004d},
+	{0x3d4000ec,0x16004d},
+	{0x3d400100,0x1618141a},
+	{0x3d400104,0x504a6},
+	{0x3d40010c,0x909000},
+	{0x3d400110,0xb04060b},
+	{0x3d400114,0x2030909},
+	{0x3d400118,0x1010006},
+	{0x3d40011c,0x301},
+	{0x3d400130,0x20500},
+	{0x3d400134,0xb100002},
+	{0x3d400138,0x71},
+	{0x3d400144,0x78003c},
+	{0x3d400180,0x2580012},
+	{0x3d400184,0x1e0493e},
+	{0x3d400188,0x0},
+	{0x3d400190,0x4938208},
+	{0x3d400194,0x80303},
+	{0x3d4001b4,0x1308},
+	{0x3d4001a0,0xe0400018},
+	{0x3d4001a4,0xdf00e4},
+	{0x3d4001a8,0x80000000},
+	{0x3d4001b0,0x11},
+	{0x3d4001c0,0x1},
+	{0x3d4001c4,0x1},
+	{0x3d4000f4,0xc99},
+	{0x3d400108,0x60c1514},
+	{0x3d400200,0x1f},
+	{0x3d40020c,0x0},
+	{0x3d400210,0x1f1f},
+	{0x3d400204,0x80808},
+	{0x3d400214,0x7070707},
+	{0x3d400218,0xf070707},
+	{0x3d40021c,0xf0f},
+	{0x3d400250,0x29001701},
+	{0x3d400254,0x2c},
+	{0x3d40025c,0x4000030},
+	{0x3d400264,0x900093e7},
+	{0x3d40026c,0x2005574},
+	{0x3d400400,0x111},
+	{0x3d400408,0x72ff},
+	{0x3d400494,0x2100e07},
+	{0x3d400498,0x620096},
+	{0x3d40049c,0x1100e07},
+	{0x3d4004a0,0xc8012c},
+	{0x3d402020,0x21},
+	{0x3d402024,0x7d00},
+	{0x3d402050,0x20d040},
+	{0x3d402064,0xc0012},
+	{0x3d4020dc,0x840000},
+	{0x3d4020e0,0x310000},
+	{0x3d4020e8,0x66004d},
+	{0x3d4020ec,0x16004d},
+	{0x3d402100,0xa040305},
+	{0x3d402104,0x30407},
+	{0x3d402108,0x203060b},
+	{0x3d40210c,0x505000},
+	{0x3d402110,0x2040202},
+	{0x3d402114,0x2030202},
+	{0x3d402118,0x1010004},
+	{0x3d40211c,0x301},
+	{0x3d402130,0x20300},
+	{0x3d402134,0xa100002},
+	{0x3d402138,0x13},
+	{0x3d402144,0x14000a},
+	{0x3d402180,0x640004},
+	{0x3d402190,0x3818200},
+	{0x3d402194,0x80303},
+	{0x3d4021b4,0x100},
+	{0x3d4020f4,0xc99},
+	{0x3d403020,0x21},
+	{0x3d403024,0x1f40},
+	{0x3d403050,0x20d040},
+	{0x3d403064,0x30005},
+	{0x3d4030dc,0x840000},
+	{0x3d4030e0,0x310000},
+	{0x3d4030e8,0x66004d},
+	{0x3d4030ec,0x16004d},
+	{0x3d403100,0xa010102},
+	{0x3d403104,0x30404},
+	{0x3d403108,0x203060b},
+	{0x3d40310c,0x505000},
+	{0x3d403110,0x2040202},
+	{0x3d403114,0x2030202},
+	{0x3d403118,0x1010004},
+	{0x3d40311c,0x301},
+	{0x3d403130,0x20300},
+	{0x3d403134,0xa100002},
+	{0x3d403138,0x5},
+	{0x3d403144,0x50003},
+	{0x3d403180,0x190004},
+	{0x3d403190,0x3818200},
+	{0x3d403194,0x80303},
+	{0x3d4031b4,0x100},
+	{0x3d4030f4,0xc99},
+	{0x3d400028,0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0,0x0},
+	{0x100a1,0x1},
+	{0x100a2,0x2},
+	{0x100a3,0x3},
+	{0x100a4,0x4},
+	{0x100a5,0x5},
+	{0x100a6,0x6},
+	{0x100a7,0x7},
+	{0x110a0,0x0},
+	{0x110a1,0x1},
+	{0x110a2,0x3},
+	{0x110a3,0x4},
+	{0x110a4,0x5},
+	{0x110a5,0x2},
+	{0x110a6,0x7},
+	{0x110a7,0x6},
+	{0x120a0,0x0},
+	{0x120a1,0x1},
+	{0x120a2,0x3},
+	{0x120a3,0x2},
+	{0x120a4,0x5},
+	{0x120a5,0x4},
+	{0x120a6,0x7},
+	{0x120a7,0x6},
+	{0x130a0,0x0},
+	{0x130a1,0x1},
+	{0x130a2,0x2},
+	{0x130a3,0x3},
+	{0x130a4,0x4},
+	{0x130a5,0x5},
+	{0x130a6,0x6},
+	{0x130a7,0x7},
+	{0x1005f,0x1ff},
+	{0x1015f,0x1ff},
+	{0x1105f,0x1ff},
+	{0x1115f,0x1ff},
+	{0x1205f,0x1ff},
+	{0x1215f,0x1ff},
+	{0x1305f,0x1ff},
+	{0x1315f,0x1ff},
+	{0x11005f,0x1ff},
+	{0x11015f,0x1ff},
+	{0x11105f,0x1ff},
+	{0x11115f,0x1ff},
+	{0x11205f,0x1ff},
+	{0x11215f,0x1ff},
+	{0x11305f,0x1ff},
+	{0x11315f,0x1ff},
+	{0x21005f,0x1ff},
+	{0x21015f,0x1ff},
+	{0x21105f,0x1ff},
+	{0x21115f,0x1ff},
+	{0x21205f,0x1ff},
+	{0x21215f,0x1ff},
+	{0x21305f,0x1ff},
+	{0x21315f,0x1ff},
+	{0x55,0x1ff},
+	{0x1055,0x1ff},
+	{0x2055,0x1ff},
+	{0x3055,0x1ff},
+	{0x4055,0x1ff},
+	{0x5055,0x1ff},
+	{0x6055,0x1ff},
+	{0x7055,0x1ff},
+	{0x8055,0x1ff},
+	{0x9055,0x1ff},
+	{0x200c5,0xa},
+	{0x1200c5,0x7},
+	{0x2200c5,0x7},
+	{0x2002e,0x2},
+	{0x12002e,0x2},
+	{0x22002e,0x2},
+	{0x90204,0x0},
+	{0x190204,0x0},
+	{0x290204,0x0},
+	{0x20024,0x1ab},
+	{0x2003a,0x0},
+	{0x120024,0x1ab},
+	{0x2003a,0x0},
+	{0x220024,0x1ab},
+	{0x2003a,0x0},
+	{0x20056,0x2},
+	{0x120056,0xa},
+	{0x220056,0xa},
+	{0x1004d,0xe00},
+	{0x1014d,0xe00},
+	{0x1104d,0xe00},
+	{0x1114d,0xe00},
+	{0x1204d,0xe00},
+	{0x1214d,0xe00},
+	{0x1304d,0xe00},
+	{0x1314d,0xe00},
+	{0x11004d,0xe00},
+	{0x11014d,0xe00},
+	{0x11104d,0xe00},
+	{0x11114d,0xe00},
+	{0x11204d,0xe00},
+	{0x11214d,0xe00},
+	{0x11304d,0xe00},
+	{0x11314d,0xe00},
+	{0x21004d,0xe00},
+	{0x21014d,0xe00},
+	{0x21104d,0xe00},
+	{0x21114d,0xe00},
+	{0x21204d,0xe00},
+	{0x21214d,0xe00},
+	{0x21304d,0xe00},
+	{0x21314d,0xe00},
+	{0x10049,0xeba},
+	{0x10149,0xeba},
+	{0x11049,0xeba},
+	{0x11149,0xeba},
+	{0x12049,0xeba},
+	{0x12149,0xeba},
+	{0x13049,0xeba},
+	{0x13149,0xeba},
+	{0x110049,0xeba},
+	{0x110149,0xeba},
+	{0x111049,0xeba},
+	{0x111149,0xeba},
+	{0x112049,0xeba},
+	{0x112149,0xeba},
+	{0x113049,0xeba},
+	{0x113149,0xeba},
+	{0x210049,0xeba},
+	{0x210149,0xeba},
+	{0x211049,0xeba},
+	{0x211149,0xeba},
+	{0x212049,0xeba},
+	{0x212149,0xeba},
+	{0x213049,0xeba},
+	{0x213149,0xeba},
+	{0x43,0x63},
+	{0x1043,0x63},
+	{0x2043,0x63},
+	{0x3043,0x63},
+	{0x4043,0x63},
+	{0x5043,0x63},
+	{0x6043,0x63},
+	{0x7043,0x63},
+	{0x8043,0x63},
+	{0x9043,0x63},
+	{0x20018,0x3},
+	{0x20075,0x4},
+	{0x20050,0x0},
+	{0x20008,0x258},
+	{0x120008,0x64},
+	{0x220008,0x19},
+	{0x20088,0x9},
+	{0x200b2,0xdc},
+	{0x10043,0x5a1},
+	{0x10143,0x5a1},
+	{0x11043,0x5a1},
+	{0x11143,0x5a1},
+	{0x12043,0x5a1},
+	{0x12143,0x5a1},
+	{0x13043,0x5a1},
+	{0x13143,0x5a1},
+	{0x1200b2,0xdc},
+	{0x110043,0x5a1},
+	{0x110143,0x5a1},
+	{0x111043,0x5a1},
+	{0x111143,0x5a1},
+	{0x112043,0x5a1},
+	{0x112143,0x5a1},
+	{0x113043,0x5a1},
+	{0x113143,0x5a1},
+	{0x2200b2,0xdc},
+	{0x210043,0x5a1},
+	{0x210143,0x5a1},
+	{0x211043,0x5a1},
+	{0x211143,0x5a1},
+	{0x212043,0x5a1},
+	{0x212143,0x5a1},
+	{0x213043,0x5a1},
+	{0x213143,0x5a1},
+	{0x200fa,0x1},
+	{0x1200fa,0x1},
+	{0x2200fa,0x1},
+	{0x20019,0x1},
+	{0x120019,0x1},
+	{0x220019,0x1},
+	{0x200f0,0x660},
+	{0x200f1,0x0},
+	{0x200f2,0x4444},
+	{0x200f3,0x8888},
+	{0x200f4,0x5665},
+	{0x200f5,0x0},
+	{0x200f6,0x0},
+	{0x200f7,0xf000},
+	{0x20025,0x0},
+	{0x2002d,0x0},
+	{0x12002d,0x0},
+	{0x22002d,0x0},
+	{0x200c7,0x21},
+	{0x1200c7,0x21},
+	{0x2200c7,0x21},
+	{0x200ca,0x24},
+	{0x1200ca,0x24},
+	{0x2200ca,0x24},
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg_1g_2ch1cs15r10cx32[] = {
+	{0xd0000, 0x0},
+	{0x54003,0x960},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x131f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x24c4},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x24c4},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0xc400},
+	{0x54033,0x3124},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0xc400},
+	{0x54039,0x3124},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg_1g_2ch1cs15r10cx32[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x101},
+	{0x54003,0x190},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x84},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x84},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0x8400},
+	{0x54033,0x3100},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0x8400},
+	{0x54039,0x3100},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg_1g_2ch1cs15r10cx32[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x102},
+	{0x54003,0x64},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400d,0x100},
+	{0x54012,0x110},
+	{0x54019,0x84},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x84},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0x8400},
+	{0x54033,0x3100},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0x8400},
+	{0x54039,0x3100},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32[] = {
+	{0xd0000, 0x0},
+	{0x54003,0x960},
+	{0x54004,0x2},
+	{0x54005,0x2228},
+	{0x54006,0x11},
+	{0x54008,0x61},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400f,0x100},
+	{0x54010,0x1f7f},
+	{0x54012,0x110},
+	{0x54019,0x24c4},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x24c4},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x1},
+	{0x54032,0xc400},
+	{0x54033,0x3124},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0xc400},
+	{0x54039,0x3124},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000,0x10},
+	{0x90001,0x400},
+	{0x90002,0x10e},
+	{0x90003,0x0},
+	{0x90004,0x0},
+	{0x90005,0x8},
+	{0x90029,0xb},
+	{0x9002a,0x480},
+	{0x9002b,0x109},
+	{0x9002c,0x8},
+	{0x9002d,0x448},
+	{0x9002e,0x139},
+	{0x9002f,0x8},
+	{0x90030,0x478},
+	{0x90031,0x109},
+	{0x90032,0x0},
+	{0x90033,0xe8},
+	{0x90034,0x109},
+	{0x90035,0x2},
+	{0x90036,0x10},
+	{0x90037,0x139},
+	{0x90038,0xf},
+	{0x90039,0x7c0},
+	{0x9003a,0x139},
+	{0x9003b,0x44},
+	{0x9003c,0x630},
+	{0x9003d,0x159},
+	{0x9003e,0x14f},
+	{0x9003f,0x630},
+	{0x90040,0x159},
+	{0x90041,0x47},
+	{0x90042,0x630},
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+	{0x137b4,0x1},
+	{0x138b4,0x1},
+	{0x2003a,0x2},
+	{0xc0080,0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg_1g_2ch1cs15r10cx32[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg_1g_2ch1cs15r10cx32,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1g_2ch1cs15r10cx32),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg_1g_2ch1cs15r10cx32,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_1g_2ch1cs15r10cx32),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg_1g_2ch1cs15r10cx32,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1g_2ch1cs15r10cx32),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info innocomm_wb15_dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg_1g_2ch1cs15r10cx32,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1g_2ch1cs15r10cx32),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg_1g_2ch1cs15r10cx32,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_1g_2ch1cs15r10cx32),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 400, 100, },
+};