diff options
Diffstat (limited to 'arch/arm/boards/nxp-imx8mq-evk')
| -rw-r--r-- | arch/arm/boards/nxp-imx8mq-evk/.gitignore | 2 | ||||
| -rw-r--r-- | arch/arm/boards/nxp-imx8mq-evk/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/boards/nxp-imx8mq-evk/board.c | 4 | ||||
| -rw-r--r-- | arch/arm/boards/nxp-imx8mq-evk/ddr_init.c | 3 | ||||
| -rw-r--r-- | arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c | 12 | ||||
| -rw-r--r-- | arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg | 5 | ||||
| -rw-r--r-- | arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 46 |
7 files changed, 29 insertions, 45 deletions
diff --git a/arch/arm/boards/nxp-imx8mq-evk/.gitignore b/arch/arm/boards/nxp-imx8mq-evk/.gitignore index ef13747c92..cafa52b207 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/.gitignore +++ b/arch/arm/boards/nxp-imx8mq-evk/.gitignore @@ -1 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + *.ddr-phy-fw* diff --git a/arch/arm/boards/nxp-imx8mq-evk/Makefile b/arch/arm/boards/nxp-imx8mq-evk/Makefile index 2995f06f0f..17d769f330 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/Makefile +++ b/arch/arm/boards/nxp-imx8mq-evk/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o ddr_init.o ddrphy_train.o diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c index c28107cb17..d86666958a 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/board.c +++ b/arch/arm/boards/nxp-imx8mq-evk/board.c @@ -7,7 +7,7 @@ #include <init.h> #include <linux/phy.h> #include <linux/sizes.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <envfs.h> @@ -40,7 +40,7 @@ static int nxp_imx8mq_evk_init(void) barebox_set_hostname("imx8mq-evk"); flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0; - imx8m_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0.barebox", flags); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", flags); flags = bootsource_get_instance() == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0; imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", flags); diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c index 39addea973..b1f752c4cb 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c +++ b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c @@ -81,6 +81,7 @@ void ddr_init(void) reg32_write(0x3d400200,0x15); reg32_write(0x3d40020c,0x0); reg32_write(0x3d400210,0x1f1f); + reg32_write(0x3d40021c,0xf0f); reg32_write(0x3d400204,0x80808); reg32_write(0x3d400214,0x7070707); reg32_write(0x3d400218,0x48080707); @@ -222,4 +223,4 @@ void ddr_init(void) /* enable DDR auto-refresh mode */ tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; reg32_write(DDRC_RFSHCTL3(0), tmp); -}
\ No newline at end of file +} diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c index d2c73fc7ce..bac7d0a517 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c +++ b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c @@ -11,6 +11,8 @@ void ddr_cfg_phy(void) { unsigned int tmp, tmp_t; + ddr_get_firmware(DRAM_TYPE_LPDDR4); + //Init DDRPHY register... reg32_write(0x3c080440,0x2); reg32_write(0x3c080444,0x3); @@ -142,7 +144,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 1D training image - ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE); + imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE); //configure DDRPHY-FW DMEM structure @clock0... reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); @@ -187,7 +189,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //configure DDRPHY-FW DMEM structure @clock1... reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); @@ -256,7 +258,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //set the PHY input clock to the desired frequency for pstate 0 reg32_write(0x3038a088,0x7070000); @@ -289,7 +291,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 2D training image - ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE); + imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); @@ -330,7 +332,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //Halt MPU reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); diff --git a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg index 80ce03e22c..f82759f849 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg +++ b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg @@ -1,6 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx8mq loadaddr 0x007E1000 max_load_size 0x3F000 ivtofs 0x400 -#include <mach/habv4-imx8-gencsf.h> + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index 92cc22e022..d1a517dddb 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -2,26 +2,26 @@ #include <common.h> #include <firmware.h> -#include <image-metadata.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx8m-ccm-regs.h> -#include <mach/iomux-mx8mq.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/iomux-mx8mq.h> #include <soc/imx8m/ddr.h> -#include <mach/xload.h> +#include <mach/imx/xload.h> #include <io.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <asm/cache.h> #include <asm/sections.h> #include <asm/mmu.h> -#include <mach/atf.h> -#include <mach/esdctl.h> +#include <mach/imx/atf.h> +#include <mach/imx/esdctl.h> #include "ddr.h" -extern char __dtb_imx8mq_evk_start[]; +extern char __dtb_z_imx8mq_evk_start[]; #define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM) @@ -65,39 +65,15 @@ static __noreturn noinline void nxp_imx8mq_evk_start(void) * to DRAM in EL2. */ if (current_el() == 3) { - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; - int ret = -ENOTSUPP; - size_t bl31_size; - const u8 *bl31; - ddr_init(); - /* - * On completion the TF-A will jump to MX8MQ_ATF_BL33_BASE_ADDR - * in EL2. Copy the image there, but replace the PBL part of - * that image with ourselves. On a high assurance boot only the - * currently running code is validated and contains the checksum - * for the piggy data, so we need to ensure that we are running - * the same code in DRAM. - */ - imx8mq_get_boot_source(&src, &instance); - if (src == BOOTSOURCE_MMC) - ret = imx8m_esdhc_load_image(instance, false); - BUG_ON(ret); - - memcpy((void *)MX8MQ_ATF_BL33_BASE_ADDR, - __image_start, barebox_pbl_size); - - get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size); - imx8mq_atf_load_bl31(bl31, bl31_size); - /* not reached */ + imx8mq_load_and_start_image_via_tfa(); } /* * Standard entry we hit once we initialized both DDR and ATF */ - imx8mq_barebox_entry(__dtb_imx8mq_evk_start); + imx8mq_barebox_entry(__dtb_z_imx8mq_evk_start); } ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2) @@ -107,7 +83,5 @@ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2) relocate_to_current_adr(); setup_c(); - IMD_USED_OF(imx8mq_evk); - nxp_imx8mq_evk_start(); } |