diff options
Diffstat (limited to 'arch/arm/boards/reflex-achilles/lowlevel.c')
| -rw-r--r-- | arch/arm/boards/reflex-achilles/lowlevel.c | 32 |
1 files changed, 13 insertions, 19 deletions
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c index e8d1a9cee4..ec8c126c2a 100644 --- a/arch/arm/boards/reflex-achilles/lowlevel.c +++ b/arch/arm/boards/reflex-achilles/lowlevel.c @@ -23,21 +23,24 @@ #define BAREBOX_PART 0 #define BITSTREAM_PART 1 #define BAREBOX1_OFFSET SZ_1M -#define BAREBOX2_OFFSET BAREBOX1_OFFSET + SZ_512K -#define BAREBOX3_OFFSET BAREBOX2_OFFSET + SZ_512K -#define BAREBOX4_OFFSET BAREBOX3_OFFSET + SZ_512K +#define BAREBOX2_OFFSET (BAREBOX1_OFFSET + SZ_512K) +#define BAREBOX3_OFFSET (BAREBOX2_OFFSET + SZ_512K) +#define BAREBOX4_OFFSET (BAREBOX3_OFFSET + SZ_512K) +// Offset from the start of the second partition on the eMMC. #define BITSTREAM1_OFFSET 0x0 -#define BITSTREAM2_OFFSET BITSTREAM1_OFFSET + SZ_32M +#define BITSTREAM2_OFFSET (BITSTREAM1_OFFSET + SZ_32M) -extern char __dtb_socfpga_arria10_achilles_start[]; +extern char __dtb_z_socfpga_arria10_achilles_start[]; -static noinline void achilles_start(void) +#define ARRIA10_STACKTOP (ARRIA10_OCRAM_ADDR + SZ_256K) + +ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_xload, ARRIA10_STACKTOP, r0, r1, r2) { int pbl_index = 0; int barebox = 0; int bitstream = 0; - arm_early_mmu_cache_invalidate(); + arm_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); @@ -76,23 +79,16 @@ static noinline void achilles_start(void) arria10_start_image(barebox); } -ENTRY_FUNCTION(start_socfpga_achilles_xload, r0, r1, r2) -{ - arm_cpu_lowlevel_init(); - arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K); - achilles_start(); -} - ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2) { void *fdt; - fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset(); + fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset(); barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt); } -ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2) +ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_bringup, ARRIA10_STACKTOP, r0, r1, r2) { void *fdt; @@ -100,8 +96,6 @@ ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2) arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K); - arm_early_mmu_cache_invalidate(); - relocate_to_current_adr(); setup_c(); @@ -114,7 +108,7 @@ ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2) arria10_ddr_calibration_sequence(); - fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset(); + fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset(); barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt); } |