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-rw-r--r--arch/arm/boards/terasic-de0-nano-soc/board.c9
-rw-r--r--arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c2
-rw-r--r--arch/arm/boards/terasic-de0-nano-soc/lowlevel.c2
3 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/boards/terasic-de0-nano-soc/board.c b/arch/arm/boards/terasic-de0-nano-soc/board.c
index 4019dae6a4..b4502f552a 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/board.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/board.c
@@ -5,12 +5,13 @@
#include <driver.h>
#include <init.h>
#include <asm/armlinux.h>
+#include <linux/mdio.h>
#include <linux/micrel_phy.h>
#include <linux/phy.h>
#include <linux/sizes.h>
#include <fcntl.h>
#include <fs.h>
-#include <mach/cyclone5-regs.h>
+#include <mach/socfpga/cyclone5-regs.h>
static int phy_fixup(struct phy_device *dev)
{
@@ -18,9 +19,9 @@ static int phy_fixup(struct phy_device *dev)
* min rx data delay, max rx/tx clock delay,
* min rx/tx control delay
*/
- phy_write_mmd_indirect(dev, 4, 2, 0);
- phy_write_mmd_indirect(dev, 5, 2, 0);
- phy_write_mmd_indirect(dev, 8, 2, 0x003ff);
+ phy_write_mmd(dev, MDIO_MMD_WIS, 4, 0);
+ phy_write_mmd(dev, MDIO_MMD_WIS, 5, 0);
+ phy_write_mmd(dev, MDIO_MMD_WIS, 8, 0x003ff);
return 0;
}
diff --git a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
index 1458e76ba8..27af250232 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <mach/cyclone5-scan-manager.h>
+#include <mach/socfpga/cyclone5-scan-manager.h>
static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x00000000,
diff --git a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
index 91bfd1a776..71121b6d4c 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
@@ -9,7 +9,7 @@
#include "sequencer_auto_ac_init.c"
#include "iocsr_config_cyclone5.c"
-#include <mach/lowlevel.h>
+#include <mach/socfpga/lowlevel.h>
SOCFPGA_C5_ENTRY(start_socfpga_de0_nano_soc, socfpga_cyclone5_de0_nano_soc, SZ_1G);
SOCFPGA_C5_XLOAD_ENTRY(start_socfpga_de0_nano_soc_xload, SZ_1G);