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-rw-r--r--arch/arm/boards/zii-imx8mq-dev/Makefile2
-rw-r--r--arch/arm/boards/zii-imx8mq-dev/board.c6
-rw-r--r--arch/arm/boards/zii-imx8mq-dev/ddr_init.c5
-rw-r--r--arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c12
-rw-r--r--arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg4
-rw-r--r--arch/arm/boards/zii-imx8mq-dev/lowlevel.c39
6 files changed, 29 insertions, 39 deletions
diff --git a/arch/arm/boards/zii-imx8mq-dev/Makefile b/arch/arm/boards/zii-imx8mq-dev/Makefile
index d0148b5067..8894e40b5a 100644
--- a/arch/arm/boards/zii-imx8mq-dev/Makefile
+++ b/arch/arm/boards/zii-imx8mq-dev/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
obj-y += board.o
lwl-y += lowlevel.o ddr_init.o ddrphy_train.o
bbenv-y += defaultenv-imx8mq-zii-dev
diff --git a/arch/arm/boards/zii-imx8mq-dev/board.c b/arch/arm/boards/zii-imx8mq-dev/board.c
index 4ad09663ac..3581c7251d 100644
--- a/arch/arm/boards/zii-imx8mq-dev/board.c
+++ b/arch/arm/boards/zii-imx8mq-dev/board.c
@@ -10,7 +10,7 @@
#include <init.h>
#include <asm/memory.h>
#include <linux/sizes.h>
-#include <mach/bbu.h>
+#include <mach/imx/bbu.h>
#include "../zii-common/pn-fixup.h"
#define LRU_FLAG_EGALAX BIT(0)
@@ -81,7 +81,7 @@ static int zii_imx8mq_dev_fixup_egalax_ts(struct device_node *root, void *ctx)
static int zii_imx8mq_dev_fixup_deb_internal(void)
{
struct device_node *np, *aliases;
- struct device_d *dev;
+ struct device *dev;
/*
* In the internal DT remove the complete FEC hierarchy and move the
@@ -106,7 +106,7 @@ static int zii_imx8mq_dev_fixup_deb_internal(void)
unregister_device(dev);
- np = of_find_node_by_name(NULL, "i210@0");
+ np = of_find_node_by_name_address(NULL, "i210@0");
if (!np)
return -ENODEV;
diff --git a/arch/arm/boards/zii-imx8mq-dev/ddr_init.c b/arch/arm/boards/zii-imx8mq-dev/ddr_init.c
index 7a955193fd..2d4133fb13 100644
--- a/arch/arm/boards/zii-imx8mq-dev/ddr_init.c
+++ b/arch/arm/boards/zii-imx8mq-dev/ddr_init.c
@@ -81,6 +81,7 @@ void ddr_init(void)
reg32_write(0x3d400200,0x17);
reg32_write(0x3d40020c,0x0);
reg32_write(0x3d400210,0x1f1f);
+ reg32_write(0x3d40021c,0xf0f);
reg32_write(0x3d400204,0x80808);
reg32_write(0x3d400214,0x7070707);
reg32_write(0x3d400218,0x7070707);
@@ -177,7 +178,7 @@ void ddr_init(void)
reg32_write(DDRC_SWCTL(0), 0x0000);
/*
* ------------------- 9 -------------------
- * Set DFIMISC.dfi_init_start to 1
+ * Set DFIMISC.dfi_init_start to 1
* -----------------------------------------
*/
reg32_write(DDRC_DFIMISC(0), 0x00000030);
@@ -222,4 +223,4 @@ void ddr_init(void)
/* enable DDR auto-refresh mode */
tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1;
reg32_write(DDRC_RFSHCTL3(0), tmp);
-} \ No newline at end of file
+}
diff --git a/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c b/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c
index d2c73fc7ce..bac7d0a517 100644
--- a/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c
+++ b/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c
@@ -11,6 +11,8 @@
void ddr_cfg_phy(void) {
unsigned int tmp, tmp_t;
+ ddr_get_firmware(DRAM_TYPE_LPDDR4);
+
//Init DDRPHY register...
reg32_write(0x3c080440,0x2);
reg32_write(0x3c080444,0x3);
@@ -142,7 +144,7 @@ void ddr_cfg_phy(void) {
//enable APB bus to access DDRPHY RAM
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
//load the 1D training image
- ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE);
+ imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE);
//configure DDRPHY-FW DMEM structure @clock0...
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
@@ -187,7 +189,7 @@ void ddr_cfg_phy(void) {
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
- wait_ddrphy_training_complete();
+ imx8m_wait_ddrphy_training_complete();
//configure DDRPHY-FW DMEM structure @clock1...
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
@@ -256,7 +258,7 @@ void ddr_cfg_phy(void) {
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
- wait_ddrphy_training_complete();
+ imx8m_wait_ddrphy_training_complete();
//set the PHY input clock to the desired frequency for pstate 0
reg32_write(0x3038a088,0x7070000);
@@ -289,7 +291,7 @@ void ddr_cfg_phy(void) {
//enable APB bus to access DDRPHY RAM
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
//load the 2D training image
- ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE);
+ imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE);
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80);
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11);
@@ -330,7 +332,7 @@ void ddr_cfg_phy(void) {
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
- wait_ddrphy_training_complete();
+ imx8m_wait_ddrphy_training_complete();
//Halt MPU
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
diff --git a/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg b/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg
index 8921f32110..f82759f849 100644
--- a/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg
+++ b/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg
@@ -1,5 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
soc imx8mq
loadaddr 0x007E1000
max_load_size 0x3F000
ivtofs 0x400
+
+#include <mach/imx/habv4-imx8-gencsf.h>
diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
index cf53fb2def..4184748cd8 100644
--- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
+++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
@@ -6,22 +6,22 @@
#include <common.h>
#include <firmware.h>
-#include <image-metadata.h>
#include <linux/sizes.h>
-#include <mach/generic.h>
+#include <mach/imx/generic.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/imx8m-ccm-regs.h>
-#include <mach/iomux-mx8mq.h>
+#include <mach/imx/imx8m-ccm-regs.h>
+#include <mach/imx/iomux-mx8mq.h>
#include <soc/imx8m/ddr.h>
-#include <mach/xload.h>
+#include <mach/imx/xload.h>
#include <io.h>
#include <debug_ll.h>
+#include <mach/imx/debug_ll.h>
#include <asm/cache.h>
#include <asm/sections.h>
#include <asm/mmu.h>
-#include <mach/atf.h>
-#include <mach/esdctl.h>
+#include <mach/imx/atf.h>
+#include <mach/imx/esdctl.h>
#include "ddr.h"
@@ -63,21 +63,10 @@ static __noreturn void ddr_helper_halt(void)
static void zii_imx8mq_dev_sram_setup(void)
{
- enum bootsource src = BOOTSOURCE_UNKNOWN;
- int instance = BOOTSOURCE_INSTANCE_UNKNOWN;
- int ret = -ENOTSUPP;
-
ddr_init();
if (running_as_ddr_helper())
ddr_helper_halt();
-
- imx8mq_get_boot_source(&src, &instance);
-
- if (src == BOOTSOURCE_MMC)
- ret = imx8m_esdhc_load_image(instance, true);
-
- BUG_ON(ret);
}
enum zii_platform_imx8mq_type {
@@ -141,13 +130,8 @@ static __noreturn noinline void zii_imx8mq_dev_start(void)
* initialization routine, it is EL2 which means we'll skip
* loadting ATF blob again
*/
- if (current_el() == 3) {
- const u8 *bl31;
- size_t bl31_size;
-
- get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size);
- imx8mq_atf_load_bl31(bl31, bl31_size);
- }
+ if (current_el() == 3)
+ imx8mq_load_and_start_image_via_tfa();
system_type = get_system_type();
@@ -190,7 +174,7 @@ static __noreturn noinline void zii_imx8mq_dev_start(void)
*
* 4. BL31 blob is uploaded to OCRAM and the control is transfer to it
*
- * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR,
+ * 5. BL31 exits EL3 into EL2 at address MX8M_ATF_BL33_BASE_ADDR,
* executing start_nxp_imx8mq_evk() the third time
*
* 6. Standard barebox boot flow continues
@@ -201,8 +185,5 @@ ENTRY_FUNCTION(start_zii_imx8mq_dev, r0, r1, r2)
relocate_to_current_adr();
setup_c();
- IMD_USED_OF(imx8mq_zii_ultra_rmb3);
- IMD_USED_OF(imx8mq_zii_ultra_zest);
-
zii_imx8mq_dev_start();
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-01 01:11:30 +0000