diff options
Diffstat (limited to 'arch/arm/cpu/cache-armv5.S')
| -rw-r--r-- | arch/arm/cpu/cache-armv5.S | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S index a1193a6a66..d6ffaf10e2 100644 --- a/arch/arm/cpu/cache-armv5.S +++ b/arch/arm/cpu/cache-armv5.S @@ -3,6 +3,7 @@ #define CACHE_DLINESIZE 32 +.section .text.__mmu_cache_on ENTRY(__mmu_cache_on) mov r12, lr #ifdef CONFIG_MMU @@ -30,6 +31,7 @@ __common_mmu_cache_on: mrc p15, 0, r0, c1, c0, 0 @ and read it back to sub pc, lr, r0, lsr #32 @ properly flush pipeline +.section .text.__mmu_cache_off ENTRY(__mmu_cache_off) #ifdef CONFIG_MMU mrc p15, 0, r0, c1, c0 @@ -42,6 +44,7 @@ ENTRY(__mmu_cache_off) mov pc, lr ENDPROC(__mmu_cache_off) +.section .text.__mmu_cache_flush ENTRY(__mmu_cache_flush) 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache bne 1b @@ -49,7 +52,6 @@ ENTRY(__mmu_cache_flush) mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr ENDPROC(__mmu_cache_flush) -.section ".text.text" /* * dma_inv_range(start, end) @@ -64,6 +66,7 @@ ENDPROC(__mmu_cache_flush) * * (same as v4wb) */ +.section .text.__dma_inv_range ENTRY(__dma_inv_range) tst r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1 @@ -87,6 +90,7 @@ ENTRY(__dma_inv_range) * * (same as v4wb) */ +.section .text.__dma_clean_range ENTRY(__dma_clean_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry @@ -104,6 +108,7 @@ ENTRY(__dma_clean_range) * - start - virtual start address * - end - virtual end address */ +.section .text.__dma_flush_range ENTRY(__dma_flush_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |