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-rw-r--r--arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts45
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts
new file mode 100644
index 0000000000..6ad978f453
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-phycore-stm32mp1-3.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
+ * Author: Dom VOVARD <dom.vovard@linrt.com>.
+ */
+
+/dts-v1/;
+
+#include <arm/st/stm32mp157c-phycore-stm32mp1-3.dts>
+#include "stm32mp151.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-STM32MP1-3 SoM";
+ compatible = "phytec,phycore-stm32mp1-3", "st,stm32mp157";
+
+ chosen {
+ environment-sd {
+ compatible = "barebox,environment";
+ device-path = &sdmmc1, "partname:barebox-environment";
+ status = "disabled";
+ };
+
+ environment-emmc {
+ compatible = "barebox,environment";
+ device-path = &sdmmc2, "partname:barebox-environment";
+ status = "disabled";
+ };
+ };
+};
+
+&ethernet0_rgmii_pins_d {
+ /*
+ * Kernel uses ETH_RGMII_CLK125 instead of ETH_RGMII_GTX_CLK. Drop this
+ * once it is fixed upstream.
+ */
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+ };
+};