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-rw-r--r--arch/arm/dts/Makefile4
-rw-r--r--arch/arm/dts/bootstate.dtsi45
-rw-r--r--arch/arm/dts/rk3568-mecsbc-linux.dts704
-rw-r--r--arch/arm/dts/rk3568-mecsbc.dts147
-rw-r--r--arch/arm/dts/rk3568-wolfvision-pf5-io-expander-upstream.dtso137
-rw-r--r--arch/arm/dts/rk3568-wolfvision-pf5-io-expander.dtso11
-rw-r--r--arch/arm/dts/rk3568-wolfvision-pf5-upstream.dts528
-rw-r--r--arch/arm/dts/rk3568-wolfvision-pf5.dts48
-rw-r--r--arch/arm/dts/rk356x.dtsi31
-rw-r--r--arch/arm/dts/rk3588-rock-5b.dts15
-rw-r--r--arch/arm/dts/rockchip-pinconf.dtsi344
-rw-r--r--arch/arm/dts/stm32mp157c-lxa-mc1.dts14
-rw-r--r--arch/arm/dts/wolfvision-state.dtsi71
13 files changed, 1740 insertions, 359 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 056d4d565b..e4af867027 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -109,6 +109,7 @@ lwl-$(CONFIG_MACH_PROTONIC_IMX6) += \
imx6ul-prti6g.dtb.o \
imx6ull-jozacp.dtb.o
lwl-$(CONFIG_MACH_PROTONIC_IMX8M) += imx8mm-prt8mm.dtb.o
+lwl-$(CONFIG_MACH_PROTONIC_MECSBC) += rk3568-mecsbc.dtb.o
lwl-$(CONFIG_MACH_PROTONIC_STM32MP1) += \
stm32mp151-prtt1a.dtb.o \
stm32mp151-prtt1c.dtb.o \
@@ -185,6 +186,7 @@ lwl-$(CONFIG_MACH_WARP7) += imx7s-warp.dtb.o
lwl-$(CONFIG_MACH_VF610_TWR) += vf610-twr.dtb.o
lwl-$(CONFIG_MACH_WEBASTO_CCBV2) += imx6ul-webasto-ccbv2.dtb.o
lwl-$(CONFIG_MACH_WEBASTO_CCBV2) += imx6ul-webasto-marvel.dtb.o
+lwl-$(CONFIG_MACH_WOLFVISION_PF5) += rk3568-wolfvision-pf5.dtb.o
lwl-$(CONFIG_MACH_ZII_RDU1) += \
imx51-zii-rdu1.dtb.o \
imx51-zii-scu2-mezz.dtb.o \
@@ -229,4 +231,6 @@ lwl-$(CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP) += imx8mp-var-dart-dt8mcusto
lwl-$(CONFIG_MACH_TQMA93XX) += imx93-tqma9352-mba93xxca.dtb.o \
imx93-tqma9352-mba93xxla.dtb.o
+obj-$(CONFIG_MACH_WOLFVISION_PF5) += rk3568-wolfvision-pf5-io-expander.dtbo.o
+
clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.z
diff --git a/arch/arm/dts/bootstate.dtsi b/arch/arm/dts/bootstate.dtsi
new file mode 100644
index 0000000000..aa767d4e3b
--- /dev/null
+++ b/arch/arm/dts/bootstate.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+
+bootstate {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ system0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ remaining_attempts@0 {
+ reg = <0x0 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+
+ priority@4 {
+ reg = <0x4 0x4>;
+ type = "uint32";
+ default = <20>;
+ };
+ };
+
+ system1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ remaining_attempts@8 {
+ reg = <0x8 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+
+ priority@c {
+ reg = <0xc 0x4>;
+ type = "uint32";
+ default = <10>;
+ };
+ };
+
+ last_chosen@10 {
+ reg = <0x10 0x4>;
+ type = "uint32";
+ };
+};
diff --git a/arch/arm/dts/rk3568-mecsbc-linux.dts b/arch/arm/dts/rk3568-mecsbc-linux.dts
new file mode 100644
index 0000000000..4a36578614
--- /dev/null
+++ b/arch/arm/dts/rk3568-mecsbc-linux.dts
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <arm64/rockchip/rk3568.dtsi>
+
+/ {
+ model = "Protonic MECSBC";
+ compatible = "prt,mecsbc", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &rtl8111;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ tas2562-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Speaker";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&tas2562>;
+ };
+ };
+
+ vdd_gpu: regulator-vdd-gpu {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
+ pinctrl-names = "default";
+ pinctrl = <&pwm1m0_pins>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <915000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-settling-time-up-us = <250>;
+ pwm-dutycycle-range = <0 100>; /* dutycycle inverted 0% => 0.915V */
+ };
+
+ vdd_npu: regulator-vdd-npu {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
+ pinctrl-names = "default";
+ pinctrl = <&pwm2m0_pins>;
+ regulator-name = "vdd_npu";
+ regulator-min-microvolt = <915000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-settling-time-up-us = <250>;
+ pwm-dutycycle-range = <0 100>; /* dutycycle inverted 0% => 0.915V */
+ };
+
+ vcc_sd: bd2204-switch {
+ compatible = "regulator-gpio";
+ enable-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ regulator-name = "sdcard-gpio-supply";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ states = <1800000 0x1>, <3300000 0x0>;
+ };
+
+ p3v3: p3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "p3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ p1v8: p1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "p1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ portc0: connector_c0 {
+ compatible = "usb-c-connector";
+ label = "USB-C0";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usb_con_hs0: endpoint {
+ remote-endpoint = <&usb2phy0_host_portc0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ usb_con_ss0: endpoint {
+ remote-endpoint = <&combphy0_portc0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ usb_con_sbu0: endpoint {
+ remote-endpoint = <&edp_out_portc0>;
+ };
+ };
+ };
+ };
+
+ portc1: connector_c1 {
+ compatible = "usb-c-connector";
+ label = "USB-C1";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usb_con_hs1: endpoint {
+ remote-endpoint = <&usb2phy1_host_portc1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ usb_con_ss1: endpoint {
+ remote-endpoint = <&combphy1_portc1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ usb_con_sbu1: endpoint {
+ remote-endpoint = <&bridge_out_edp>;
+ };
+ };
+ };
+ };
+
+ edp0: edp@fe0c0000 {
+ compatible = "rockchip,rk3568-edp", "rockchip,rk3399-edp";
+ reg = <0x0 0xfe0c0000 0x0 0x10000>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_EDP_200M>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_EDPPHY_GRF>;
+ clock-names = "dp", "pclk", "grf";
+ power-domains = <&power RK3568_PD_VO>;
+ resets = <&cru SRST_P_EDP_CTRL>;
+ reset-names = "dp";
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp_in: port@0 {
+ reg = <0>;
+ };
+
+ edp_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+};
+
+&combphy0 {
+ status = "okay";
+ port {
+ combphy0_portc0: endpoint {
+ remote-endpoint = <&usb_con_ss0>;
+ };
+ };
+};
+
+&combphy1 {
+ status = "okay";
+ port {
+ combphy1_portc1: endpoint {
+ remote-endpoint = <&usb_con_ss1>;
+ };
+ };
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii";
+ clock_in_out = "output";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_clkinout
+ &gmac0_rgmii_bus>;
+ status = "okay";
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii";
+ clock_in_out = "output";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_clkinout
+ &gmac1m1_rgmii_bus>;
+ status = "okay";
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@60 {
+ compatible = "fcs,fan53555";
+ reg = <0x60>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ usbc_ctrl0: tps65987d@20 {
+ compatible = "ti,tps65987", "ti,tps6598x";
+ reg = <0x20>;
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ status = "okay";
+
+ tas2562: tas2562@4c {
+ compatible = "ti,tas2562";
+ reg = <0x4c>;
+ #sound-dai-cells = <0>;
+ shutdown-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+ interrupt-parent = <&gpio1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tas2562>;
+ interrupts = <RK_PD1 IRQ_TYPE_LEVEL_LOW>;
+ ti,imon-slot-no = <0>;
+ };
+
+ tc358867: tc358867@68 {
+ compatible = "toshiba,tc358767";
+ reg = <0x68>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tc358867>;
+ reset-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ clocks = <&cru CLK_CIF_OUT>;
+ clock-names = "ref";
+ toshiba,hpd-pin = <0>;
+ assigned-clocks = <&cru USB480M>, <&cru CLK_CIF_OUT>;
+ assigned-clock-parents = <0>, <&cru USB480M>;
+ assigned-clock-rates = <480000000>, <19200000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ bridge_in: endpoint {
+ remote-endpoint = <&dsi1_out_bridge>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bridge_out_aux: endpoint@0 {
+ remote-endpoint = <&panel_in_edp>;
+ };
+
+ bridge_out_edp: endpoint@1 {
+ remote-endpoint = <&usb_con_sbu1>;
+ };
+ };
+ };
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+
+ port {
+ panel_in_edp: endpoint {
+ remote-endpoint = <&bridge_out_aux>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ usbc_ctrl1: tps65987d@20 {
+ compatible = "ti,tps65987", "ti,tps6598x";
+ reg = <0x20>;
+ };
+
+ tmp1075n@48 {
+ compatible = "ti,tmp1075";
+ reg = <0x48>;
+ };
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf85363";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "rtcic_32kout";
+ };
+};
+
+&i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@8 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth_phy0_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth_phy1_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ /* pinctrl-0 = <&pcie20m1_pins>; */
+ pinctrl-0 = <&pcie_reset_h>;
+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pci@0,0 {
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ reg = <0 0 0 0 0>;
+
+ rtl8111: net@0,0 {
+ reg = <0 0 0 0 0>;
+ };
+ };
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x2m1_pins>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&p3v3>;
+ status = "okay";
+};
+
+&pinctrl {
+ ethernet {
+ eth_phy0_rst: eth_phy0_rst {
+ rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ eth_phy1_rst: eth_phy1_rst {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ tc358867 {
+ pinctrl_tc358867: tc358867 {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <4 RK_PC0 1 &pcfg_pull_none>,
+ <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+
+ };
+ };
+
+ tas2562 {
+ pinctrl_tas2562: tas2562 {
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pcie {
+ pcie_reset_h: pcie-reset-h {
+ rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>,
+ /* pcie20_clkreqnm1 */
+ <2 RK_PD0 4 &pcfg_pull_none>,
+ /* pcie20_wakenm1 */
+ <2 RK_PD1 4 &pcfg_pull_none>;
+ };
+ };
+
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&p3v3>;
+ pmuio2-supply = <&p3v3>;
+ vccio1-supply = <&p1v8>;
+ vccio2-supply = <&p1v8>;
+ /* vccio3-supply = <&vcc_sd>; */
+ vccio3-supply = <&p3v3>;
+ vccio4-supply = <&p1v8>;
+ vccio5-supply = <&p3v3>;
+ vccio6-supply = <&p1v8>;
+ vccio7-supply = <&p3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&p1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ vmmc-supply = <&p3v3>;
+ vqmmc-supply = <&p1v8>;
+ supports-emmc;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&p3v3>;
+ vqmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ extcon = <&usb2phy0>;
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ status = "okay";
+ port {
+ usb2phy0_host_portc0: endpoint {
+ remote-endpoint = <&usb_con_hs0>;
+ };
+ };
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ status = "okay";
+ port {
+ usb2phy1_host_portc1: endpoint {
+ remote-endpoint = <&usb_con_hs1>;
+ };
+ };
+};
+
+&usb2phy1_otg {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_dsi1: endpoint@ROCKCHIP_VOP2_EP_MIPI1 {
+ reg = <ROCKCHIP_VOP2_EP_MIPI1>;
+ remote-endpoint = <&dsi1_in_vp0>;
+ };
+};
+
+&vp1 {
+ vp1_out_edp0: endpoint@ROCKCHIP_VOP2_EP_EDP0 {
+ reg = <ROCKCHIP_VOP2_EP_EDP0>;
+ remote-endpoint = <&edp_in_vp1>;
+ };
+};
+
+&dsi1 {
+ status = "okay";
+};
+
+&dsi_dphy1 {
+ status = "okay";
+};
+
+&dsi1_in {
+ dsi1_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_dsi1>;
+ };
+};
+
+&dsi1_out {
+ dsi1_out_bridge: endpoint {
+ remote-endpoint = <&bridge_in>;
+ };
+};
+
+&edp_in {
+ edp_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_edp0>;
+ };
+};
+
+&edp_out {
+ edp_out_portc0: endpoint {
+ remote-endpoint = <&usb_con_sbu0>;
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&gpu_opp_table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <915000>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <915000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <915000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <920000>;
+ };
+
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <950000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1000000>;
+ };
+};
diff --git a/arch/arm/dts/rk3568-mecsbc.dts b/arch/arm/dts/rk3568-mecsbc.dts
new file mode 100644
index 0000000000..05893b8f72
--- /dev/null
+++ b/arch/arm/dts/rk3568-mecsbc.dts
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3568-mecsbc-linux.dts"
+#include "rk356x.dtsi"
+
+/ {
+ aliases {
+ state = &state_emmc;
+ };
+
+ chosen: chosen {
+ environment-sd {
+ compatible = "barebox,environment";
+ device-path = &environment_sd;
+ status = "disabled";
+ };
+
+ environment-emmc {
+ compatible = "barebox,environment";
+ device-path = &environment_emmc;
+ status = "okay";
+ };
+ };
+
+ state_emmc: state {
+ magic = <0x292D3A3C>;
+ compatible = "barebox,state";
+ backend-type = "raw";
+ backend = <&state_backend_emmc>;
+ backend-stridesize = <0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstate {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ system0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ remaining_attempts {
+ reg = <0x0 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+
+ priority {
+ reg = <0x4 0x4>;
+ type = "uint32";
+ default = <21>;
+ };
+ };
+
+ system1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ remaining_attempts {
+ reg = <0x10 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+
+ priority {
+ reg = <0x14 0x4>;
+ type = "uint32";
+ default = <20>;
+ };
+ };
+
+ last_chosen {
+ reg = <0x20 0x4>;
+ type = "uint32";
+ };
+ };
+
+ blobs {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ data_partitions {
+ reg = <0x26 0x100>;
+ type = "string";
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* Address will be determined by the bootloader */
+ ramoops {
+ compatible = "ramoops";
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* Address will be determined by the bootloader */
+ ramoops {
+ compatible = "ramoops";
+ };
+ };
+};
+
+&sdhci {
+ no-sd;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* eMMC reserved 8MiB for barebox (2 copies?), env and state */
+ environment_emmc: partition@7b0000 {
+ label = "barebox-environment";
+ reg = <0x0 0x7b0000 0x0 0x10000>;
+ };
+
+ /* eMMC state after barebox and environment */
+ state_backend_emmc: partition@7c0000 {
+ label = "state";
+ reg = <0x0 0x7c0000 0x0 0x40000>;
+ };
+ };
+};
+
+&sdmmc0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ environment_sd: partition@7b0000 {
+ label = "barebox-environment";
+ reg = <0x0 0x7b0000 0x0 0x10000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3568-wolfvision-pf5-io-expander-upstream.dtso b/arch/arm/dts/rk3568-wolfvision-pf5-io-expander-upstream.dtso
new file mode 100644
index 0000000000..ebcaeafc38
--- /dev/null
+++ b/arch/arm/dts/rk3568-wolfvision-pf5-io-expander-upstream.dtso
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Device tree overlay for the WolfVision PF5 IO Expander board.
+ *
+ * Copyright (C) 2024 WolfVision GmbH.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/rk3568-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&{/} {
+ gmac0_clkin: external-gmac0-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "gmac0_clkin";
+ #clock-cells = <0>;
+ };
+
+ usb_host_vbus: usb-host-vbus-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_vbus_en>;
+ regulator-name = "usb_host_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v_in>;
+ };
+
+ vcc1v8_eth: vcc1v8-eth-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc1v8_eth_en>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "1v8_eth";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_eth: vcc3v3-eth-regulator {
+ compatible = "regulator-fixed";
+ enable-active-low;
+ gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v3_eth_enn>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "3v3_eth";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>,
+ <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RMII_SPEED>,
+ <&gmac0_clkin>;
+ clock_in_out = "input";
+ phy-handle = <&dp83826>;
+ phy-mode = "rmii";
+ phy-supply = <&vcc3v3_eth>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_clkinout
+ &gmac0_rx_er
+ &gmac0_rx_bus2
+ &gmac0_tx_bus2>;
+ status = "okay";
+};
+
+&mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp83826: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth_wake_intn &eth_phy_rstn>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <2000>;
+ reset-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+};
+
+&pinctrl {
+ ethernet {
+ eth_wake_intn: eth-wake-intn-pinctrl {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ eth_phy_rstn: eth-phy-rstn-pinctrl {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc1v8_eth_en: vcc1v8-eth-en-pinctrl {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc3v3_eth_enn: vcc3v3-eth-enn-pinctrl {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb_host_vbus_en: usb-host-vbus-en-pinctrl {
+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&usb_host1_xhci {
+ maximum-speed = "high-speed";
+ phys = <&usb2phy0_host>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&usb_host_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-wolfvision-pf5-io-expander.dtso b/arch/arm/dts/rk3568-wolfvision-pf5-io-expander.dtso
new file mode 100644
index 0000000000..37b48afd2d
--- /dev/null
+++ b/arch/arm/dts/rk3568-wolfvision-pf5-io-expander.dtso
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Device tree overlay for the WolfVision PF5 IO Expander board.
+ *
+ * Copyright (C) 2024 WolfVision GmbH.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "rk3568-wolfvision-pf5-io-expander-upstream.dtso"
diff --git a/arch/arm/dts/rk3568-wolfvision-pf5-upstream.dts b/arch/arm/dts/rk3568-wolfvision-pf5-upstream.dts
new file mode 100644
index 0000000000..1160d1370e
--- /dev/null
+++ b/arch/arm/dts/rk3568-wolfvision-pf5-upstream.dts
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Device tree for the WolfVision PF5 mainboard.
+ *
+ * Copyright (C) 2024 WolfVision GmbH.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/regulator/ti,tps62864.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <arm64/rockchip/rk3568.dtsi>
+
+/ {
+ model = "WolfVision PF5";
+ compatible = "wolfvision,rk3568-pf5", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ mmc0 = &sdhci;
+ rtc0 = &pcf85623;
+ rtc1 = &rk809;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ hdmi_tx: hdmi-tx-connector {
+ compatible = "hdmi-connector";
+ hdmi-pwr-supply = <&hdmi_tx_5v>;
+ type = "a";
+
+ port {
+ hdmi_tx_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
+ hdmi_tx_5v: hdmi-tx-5v-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_tx_5v_en>;
+ regulator-name = "hdmi_tx_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v_in>;
+ };
+
+ pdm_codec: pdm-codec {
+ compatible = "dmic-codec";
+ num-channels = <1>;
+ #sound-dai-cells = <0>;
+ };
+
+ pdm_sound: pdm-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "microphone";
+
+ simple-audio-card,cpu {
+ sound-dai = <&pdm>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&pdm_codec>;
+ };
+ };
+
+ vcc12v_cam: vcc12v-cam-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc12v_cam_en>;
+ regulator-name = "12v_cam";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&vcc12v_in>;
+ };
+
+ vcc12v_in: vcc12v-in-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "12v_in";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v8_cam: vcc3v8-cam-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v8_cam_en>;
+ regulator-name = "3v8_cam";
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ vin-supply = <&vcc5v_in>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v_in>;
+ };
+
+ vcc5v_in: vcc5v-in-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "5v_in";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_in>;
+ };
+};
+
+&combphy0 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vcc0v9_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vcc0v9_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vcc0v9_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vcc0v9_cpu>;
+};
+
+&gpu {
+ mali-supply = <&vcc0v9_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vcc0v9a_image>;
+ avdd-1v8-supply = <&vcc1v8a_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_tx_in>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc5v_in>;
+ vcc2-supply = <&vcc5v_in>;
+ vcc3-supply = <&vcc5v_in>;
+ vcc4-supply = <&vcc5v_in>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc5v_in>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vcc0v9_logic: DCDC_REG1 {
+ regulator-name = "0v9_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc0v9_gpu: DCDC_REG2 {
+ regulator-name = "0v9_gpu";
+ regulator-always-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v1_ddr4: DCDC_REG3 {
+ regulator-name = "1v1_ddr4";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc0v9_npu: DCDC_REG4 {
+ regulator-name = "0v9_npu";
+ regulator-always-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8: DCDC_REG5 {
+ regulator-name = "1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc0v9a_image: LDO_REG1 {
+ regulator-name = "0v9a_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc0v9a: LDO_REG2 {
+ regulator-name = "0v9a";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc0v9a_pmu: LDO_REG3 {
+ regulator-name = "0v9a_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vcc3v3_acodec: LDO_REG4 {
+ regulator-name = "3v3_acodec";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: LDO_REG5 {
+ regulator-name = "3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc1v8a: LDO_REG7 {
+ regulator-name = "1v8a";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8a_pmu: LDO_REG8 {
+ regulator-name = "1v8a_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8a_image: LDO_REG9 {
+ regulator-name = "1v8a_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sw: SWITCH_REG1 {
+ regulator-name = "3v3_sw";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ regulator@42 {
+ compatible = "ti,tps62869";
+ reg = <0x42>;
+
+ regulators {
+ vcc0v9_cpu: SW {
+ regulator-name = "0v9_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <TPS62864_MODE_FPWM>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1150000>;
+ vin-supply = <&vcc5v_in>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ pcf85623: rtc@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk32k_in>;
+ quartz-load-femtofarads = <12500>;
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m1_xfer>;
+};
+
+&pdm {
+ pinctrl-0 = <&pdmm0_clk
+ &pdmm0_sdi0>;
+ status = "okay";
+};
+
+&pinctrl {
+ cam {
+ vcc12v_cam_en: vcc12v-cam-en-pinctrl {
+ rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc3v8_cam_en: vcc3v8-cam-en-pinctrl {
+ rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hdmitx {
+ hdmi_tx_5v_en: hdmi-tx-5v-en-pinctrl {
+ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l-pinctrl {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vcc3v3_acodec>;
+ vccio2-supply = <&vcc1v8>;
+ vccio3-supply = <&vcc3v3_sd>;
+ vccio4-supply = <&vcc1v8>;
+ vccio5-supply = <&vcc1v8>;
+ vccio6-supply = <&vcc3v3_sw>;
+ vccio7-supply = <&vcc3v3_sw>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc1v8a>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ vmmc-supply = <&vcc3v3_sw>;
+ vqmmc-supply = <&vcc1v8>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "peripheral";
+ /* The following quirks are required since the bInterval is 1 and we
+ * handle steady ISOC streaming. See Usecase 3 in commit 729dcffd1ed3
+ * ("usb: dwc3: gadget: Add support for disabling U1 and U2 entries").
+ */
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ /*
+ * Without this quirk the available fifosize seems to be miscalculated
+ * in cases where many endpoints are used. In one particular situation
+ * 8 IN EPs and 3 OUT EPs where selected and lead to stalled transfers
+ * without the resize quirk.
+ */
+ tx-fifo-resize;
+
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP2>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
diff --git a/arch/arm/dts/rk3568-wolfvision-pf5.dts b/arch/arm/dts/rk3568-wolfvision-pf5.dts
new file mode 100644
index 0000000000..e214842ee4
--- /dev/null
+++ b/arch/arm/dts/rk3568-wolfvision-pf5.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Device tree for the WolfVision PF5 mainboard.
+ *
+ * Copyright (C) 2024 WolfVision GmbH.
+ */
+
+/dts-v1/;
+#include "rk3568-wolfvision-pf5-upstream.dts"
+#include "rk356x.dtsi"
+#include "wolfvision-state.dtsi"
+
+/ {
+ aliases {
+ saradc = &saradc;
+ };
+
+ chosen: chosen {
+ environment-emmc {
+ compatible = "barebox,environment";
+ device-path = &environment_emmc;
+ };
+ };
+ /*
+ memory@a00000 {
+ device_type = "memory";
+ reg = <0x0 0x00a00000 0x0 0x7f600000>;
+ };
+ */
+};
+
+&sdhci {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ environment_emmc: partition@408000 {
+ label = "barebox-environment";
+ reg = <0x0 0x408000 0x0 0x8000>;
+ };
+
+ barebox_state: partition@410000 {
+ reg = <0x0 0x410000 0x0 0x8000>;
+ label = "state";
+ };
+ };
+};
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
index 923e18e7cc..fbabf2a6a6 100644
--- a/arch/arm/dts/rk356x.dtsi
+++ b/arch/arm/dts/rk356x.dtsi
@@ -1,6 +1,28 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+
/ {
+ aliases {
+ pmugrf.reboot_mode = &reboot_mode_pmugrf;
+ pwm0 = &pwm0;
+ pwm1 = &pwm1;
+ pwm2 = &pwm2;
+ pwm3 = &pwm3;
+ pwm4 = &pwm4;
+ pwm5 = &pwm5;
+ pwm6 = &pwm6;
+ pwm7 = &pwm7;
+ pwm8 = &pwm8;
+ pwm9 = &pwm9;
+ pwm10 = &pwm10;
+ pwm11 = &pwm11;
+ pwm12 = &pwm12;
+ pwm13 = &pwm13;
+ pwm14 = &pwm14;
+ pwm15 = &pwm15;
+ };
+
chosen {
barebox,bootsource-mmc0 = &sdhci;
barebox,bootsource-mmc1 = &sdmmc0;
@@ -31,3 +53,12 @@
resets = <&cru SRST_TRNG_NS>;
};
};
+
+&pmugrf {
+ reboot_mode_pmugrf: reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x200>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-serial = <0xef08a53c>; /* rk-usb-loader */
+ };
+};
diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts
index ddff76028e..0af5442870 100644
--- a/arch/arm/dts/rk3588-rock-5b.dts
+++ b/arch/arm/dts/rk3588-rock-5b.dts
@@ -62,21 +62,6 @@
status = "disabled";
};
-&pcie2x1l2 {
- /*
- * Originally in upstream dts this is:
- * ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
- * <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
- * <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
- *
- * Overwriting this shouldn't be necessary, but without it PCI doesn't
- * work. We have some deficiency in the PCI driver that causes this.
- */
- ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
- <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
- <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
-};
-
&pcie2x1l0 {
/* Does not work in barebox */
status = "disabled";
diff --git a/arch/arm/dts/rockchip-pinconf.dtsi b/arch/arm/dts/rockchip-pinconf.dtsi
deleted file mode 100644
index 5c645437b5..0000000000
--- a/arch/arm/dts/rockchip-pinconf.dtsi
+++ /dev/null
@@ -1,344 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-&pinctrl {
- /omit-if-no-ref/
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down: pcfg-pull-down {
- bias-pull-down;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none: pcfg-pull-none {
- bias-disable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
- bias-disable;
- drive-strength = <0>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
- bias-disable;
- drive-strength = <1>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
- bias-disable;
- drive-strength = <2>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
- bias-disable;
- drive-strength = <3>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
- bias-disable;
- drive-strength = <4>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
- bias-disable;
- drive-strength = <5>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
- bias-disable;
- drive-strength = <6>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
- bias-disable;
- drive-strength = <7>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
- bias-disable;
- drive-strength = <8>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
- bias-disable;
- drive-strength = <9>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
- bias-disable;
- drive-strength = <10>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
- bias-disable;
- drive-strength = <11>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
- bias-disable;
- drive-strength = <12>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
- bias-disable;
- drive-strength = <13>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
- bias-disable;
- drive-strength = <14>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
- bias-disable;
- drive-strength = <15>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
- bias-pull-up;
- drive-strength = <0>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
- bias-pull-up;
- drive-strength = <1>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
- bias-pull-up;
- drive-strength = <2>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
- bias-pull-up;
- drive-strength = <3>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
- bias-pull-up;
- drive-strength = <4>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
- bias-pull-up;
- drive-strength = <5>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
- bias-pull-up;
- drive-strength = <6>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
- bias-pull-up;
- drive-strength = <7>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
- bias-pull-up;
- drive-strength = <8>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
- bias-pull-up;
- drive-strength = <9>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
- bias-pull-up;
- drive-strength = <10>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
- bias-pull-up;
- drive-strength = <11>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
- bias-pull-up;
- drive-strength = <12>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
- bias-pull-up;
- drive-strength = <13>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
- bias-pull-up;
- drive-strength = <14>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
- bias-pull-up;
- drive-strength = <15>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
- bias-pull-down;
- drive-strength = <0>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
- bias-pull-down;
- drive-strength = <1>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
- bias-pull-down;
- drive-strength = <2>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
- bias-pull-down;
- drive-strength = <3>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
- bias-pull-down;
- drive-strength = <4>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
- bias-pull-down;
- drive-strength = <5>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
- bias-pull-down;
- drive-strength = <6>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
- bias-pull-down;
- drive-strength = <7>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
- bias-pull-down;
- drive-strength = <8>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
- bias-pull-down;
- drive-strength = <9>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
- bias-pull-down;
- drive-strength = <10>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
- bias-pull-down;
- drive-strength = <11>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
- bias-pull-down;
- drive-strength = <12>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
- bias-pull-down;
- drive-strength = <13>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
- bias-pull-down;
- drive-strength = <14>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
- bias-pull-down;
- drive-strength = <15>;
- };
-
- /omit-if-no-ref/
- pcfg_pull_up_smt: pcfg-pull-up-smt {
- bias-pull-up;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_down_smt: pcfg-pull-down-smt {
- bias-pull-down;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_smt: pcfg-pull-none-smt {
- bias-disable;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
- bias-disable;
- drive-strength = <0>;
- input-schmitt-enable;
- };
-
- /omit-if-no-ref/
- pcfg_output_high: pcfg-output-high {
- output-high;
- };
-
- /omit-if-no-ref/
- pcfg_output_low: pcfg-output-low {
- output-low;
- };
-};
diff --git a/arch/arm/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/dts/stm32mp157c-lxa-mc1.dts
index 1220a77c1b..29852ee9aa 100644
--- a/arch/arm/dts/stm32mp157c-lxa-mc1.dts
+++ b/arch/arm/dts/stm32mp157c-lxa-mc1.dts
@@ -7,6 +7,10 @@
#include "stm32mp151.dtsi"
/ {
+ aliases {
+ state = &state;
+ };
+
chosen {
environment-sd {
compatible = "barebox,environment";
@@ -21,6 +25,16 @@
};
};
+ state: state {
+ compatible = "barebox,state";
+ magic = <0x778ec0f4>;
+ /* backend is fixed up by board code */
+ backend-type = "raw";
+ backend-storage-type = "direct";
+ backend-stridesize = <0x40>;
+
+ #include "bootstate.dtsi"
+ };
};
&panel {
diff --git a/arch/arm/dts/wolfvision-state.dtsi b/arch/arm/dts/wolfvision-state.dtsi
new file mode 100644
index 0000000000..f246a1a4a8
--- /dev/null
+++ b/arch/arm/dts/wolfvision-state.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Common state definition for WolfVision boards.
+ *
+ * Copyright (C) 2024 WolfVision GmbH.
+ */
+
+/ {
+ aliases {
+ state = &state;
+ };
+
+ state: state {
+ compatible = "barebox,state";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ backend-type = "raw";
+ backend = <&barebox_state>;
+ backend-stridesize = <1024>;
+ magic = <0xef784236>;
+
+ bootstate {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ system1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ remaining_attempts@0 {
+ reg = <0x0 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+
+ priority@4 {
+ reg = <0x4 0x4>;
+ type = "uint32";
+ default = <21>;
+ };
+ };
+
+ system2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ remaining_attempts@8 {
+ reg = <0x8 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+
+ priority@c {
+ reg = <0xc 0x4>;
+ type = "uint32";
+ default = <20>;
+ };
+ };
+
+ last_chosen@10 {
+ reg = <0x10 0x4>;
+ type = "uint32";
+ };
+ };
+
+ mac-address@14 {
+ reg = <0x14 0x6>;
+ type = "mac";
+ };
+ };
+};
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-01 06:54:30 +0000