diff options
Diffstat (limited to 'arch/arm/mach-clps711x')
| -rw-r--r-- | arch/arm/mach-clps711x/Kconfig | 11 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/clock.c | 49 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/common.c | 150 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/devices.c | 127 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/clps711x.h | 252 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/devices.h | 7 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/lowlevel.c | 72 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/reset.c | 29 |
9 files changed, 217 insertions, 484 deletions
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index c00514e86d..6cf6bc37a2 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + if ARCH_CLPS711X choice @@ -14,7 +16,6 @@ menu "CLPS711X specific settings" config CLPS711X_RAISE_CPUFREQ bool "Raise CPU frequency to 90 MHz" - depends on MACH_CLEP7212 help Raise CPU frequency to 90 MHz. This operation can be performed only for devices which allow to operate at 90 MHz. @@ -22,12 +23,4 @@ config CLPS711X_RAISE_CPUFREQ endmenu -config ARCH_TEXT_BASE - hex - default 0xc0740000 if MACH_CLEP7212 - -config BAREBOX_MAX_IMAGE_SIZE - hex - default 0x00080000 if MACH_CLEP7212 - endif diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile index 45525343d7..871c5f7e9c 100644 --- a/arch/arm/mach-clps711x/Makefile +++ b/arch/arm/mach-clps711x/Makefile @@ -1,2 +1,4 @@ -obj-y += clock.o devices.o reset.o +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += clock.o common.o lwl-y += lowlevel.o diff --git a/arch/arm/mach-clps711x/clock.c b/arch/arm/mach-clps711x/clock.c index 2c5137c582..4cb0f2bbfa 100644 --- a/arch/arm/mach-clps711x/clock.c +++ b/arch/arm/mach-clps711x/clock.c @@ -1,11 +1,5 @@ -/* - * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> #include <common.h> #include <init.h> @@ -15,19 +9,21 @@ #include <linux/sizes.h> #include <dt-bindings/clock/clps711x-clock.h> -#include <mach/clps711x.h> +#include <mach/clps711x/clps711x.h> #define CLPS711X_OSC_FREQ 3686400 #define CLPS711X_EXT_FREQ 13000000 static struct clk *clks[CLPS711X_CLK_MAX]; +static struct clk_onecell_data clk_data; -static struct clk_div_table tdiv_tbl[] = { +static const struct clk_div_table tdiv_tbl[] = { { .val = 0, .div = 256, }, { .val = 1, .div = 1, }, + { } }; -static __init int clps711x_clk_init(void) +static int clps711x_clk_probe(struct device *dev) { unsigned int f_cpu, f_bus, f_uart, f_timer_ref, pll; u32 tmp; @@ -50,7 +46,7 @@ static __init int clps711x_clk_init(void) f_bus = 36864000 / 2; } - f_uart = f_bus / 10; + f_uart = DIV_ROUND_CLOSEST(f_bus, 10); if (tmp & SYSFLG2_CKMODE) { tmp = readw(SYSCON2); @@ -72,23 +68,26 @@ static __init int clps711x_clk_init(void) clks[CLPS711X_CLK_UART] = clk_fixed("uart", f_uart); clks[CLPS711X_CLK_TIMERREF] = clk_fixed("timer_ref", f_timer_ref); clks[CLPS711X_CLK_TIMER1] = clk_divider_table("timer1", "timer_ref", 0, - IOMEM(SYSCON1), 5, 1, tdiv_tbl, ARRAY_SIZE(tdiv_tbl)); + IOMEM(SYSCON1), 5, 1, tdiv_tbl, 0); clks[CLPS711X_CLK_TIMER2] = clk_divider_table("timer2", "timer_ref", 0, - IOMEM(SYSCON1), 7, 1, tdiv_tbl, ARRAY_SIZE(tdiv_tbl)); + IOMEM(SYSCON1), 7, 1, tdiv_tbl, 0); - clkdev_add_physbase(clks[CLPS711X_CLK_UART], UARTDR1, NULL); - clkdev_add_physbase(clks[CLPS711X_CLK_UART], UARTDR2, NULL); - clkdev_add_physbase(clks[CLPS711X_CLK_TIMER2], TC2D, NULL); + clk_data.clks = clks; + clk_data.clk_num = CLPS711X_CLK_MAX; + of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, &clk_data); return 0; } -postcore_initcall(clps711x_clk_init); -static __init int clps711x_core_init(void) -{ - add_generic_device("clps711x-cs", DEVICE_ID_SINGLE, NULL, - TC2D, SZ_2, IORESOURCE_MEM, NULL); +static const struct of_device_id __maybe_unused clps711x_clk_dt_ids[] = { + { .compatible = "cirrus,ep7209-clk", }, + { } +}; +MODULE_DEVICE_TABLE(of, clps711x_clk_dt_ids); - return 0; -} -coredevice_initcall(clps711x_core_init); +static struct driver clps711x_clk_driver = { + .probe = clps711x_clk_probe, + .name = "clps711x-clk", + .of_compatible = DRV_OF_COMPAT(clps711x_clk_dt_ids), +}; +postcore_platform_driver(clps711x_clk_driver); diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c new file mode 100644 index 0000000000..60db39ad11 --- /dev/null +++ b/arch/arm/mach-clps711x/common.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> + +#include <common.h> +#include <driver.h> +#include <restart.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <mach/clps711x/clps711x.h> + +#define CLPS711X_MAP_ADDR 0x90000000 + +static u32 remap_size = 0; + +static void __noreturn clps711x_restart(struct restart_handler *rst) +{ + shutdown_barebox(); + + asm("mov pc, #0"); + + hang(); +} + +static __init int is_clps711x_compatible(void) +{ + return of_machine_is_compatible("cirrus,ep7209"); +} + +static __init int clps711x_init(void) +{ + char *serial; + + if (!is_clps711x_compatible()) + return 0; + + restart_handler_register_fn("vector", clps711x_restart); + + serial = basprintf("%08x%08x", 0, readl(UNIQID)); + + barebox_set_serial_number(serial); + + free(serial); + + return 0; +} +postcore_initcall(clps711x_init); + +static int __init clps711x_bus_map(void) +{ + if (is_clps711x_compatible() && remap_size) + map_io_sections(0, (void *)CLPS711X_MAP_ADDR, remap_size); + + return 0; +} +postmmu_initcall(clps711x_bus_map); + +/* Scan for devices that start at zero address and maps them + * to a different unused address. + * To start the kernel, a fixup is used that rewrites the address + * of the patched device to its original state. + */ + +static void clps711x_bus_patch(struct device_node *node, + u32 compare, u32 change) +{ + const __be32 *ranges; + int rsize; + + ranges = of_get_property(node, "ranges", &rsize); + + if (ranges) { + int banks = rsize / (sizeof(u32) * 4); + __be32 *fixed, *fixedptr; + + fixed = xmalloc(rsize); + fixedptr = fixed; + + while (banks--) { + u32 bank, cell, addr, size; + + bank = be32_to_cpu(*ranges++); + cell = be32_to_cpu(*ranges++); + addr = be32_to_cpu(*ranges++); + size = be32_to_cpu(*ranges++); + + if (addr == compare) { + addr = change; + remap_size = size; + } + + *fixedptr++ = cpu_to_be32(bank); + *fixedptr++ = cpu_to_be32(cell); + *fixedptr++ = cpu_to_be32(addr); + *fixedptr++ = cpu_to_be32(size); + } + + of_set_property(node, "ranges", fixed, rsize, 0); + + free(fixed); + } +} + +static int clps711x_bus_fixup(struct device_node *root, void *context) +{ + struct device_node *node = context; + + if (remap_size) + clps711x_bus_patch(node, CLPS711X_MAP_ADDR, 0); + + return 0; +} + +static int clps711x_bus_probe(struct device *dev) +{ + u32 mcfg; + + /* Setup bus timings */ + if (!of_property_read_u32(dev->of_node, + "barebox,ep7209-memcfg1", &mcfg)) + writel(mcfg, MEMCFG1); + if (!of_property_read_u32(dev->of_node, + "barebox,ep7209-memcfg2", &mcfg)) + writel(mcfg, MEMCFG2); + + clps711x_bus_patch(dev->of_node, 0, CLPS711X_MAP_ADDR); + + of_platform_populate(dev->of_node, NULL, dev); + + of_register_fixup(clps711x_bus_fixup, dev->of_node); + + return 0; +} + +static const struct of_device_id __maybe_unused clps711x_bus_dt_ids[] = { + { .compatible = "cirrus,ep7209-bus", }, + { } +}; +MODULE_DEVICE_TABLE(of, clps711x_bus_dt_ids); + +static struct driver clps711x_bus_driver = { + .name = "clps711x-bus", + .probe = clps711x_bus_probe, + .of_compatible = DRV_OF_COMPAT(clps711x_bus_dt_ids), +}; + +static int __init clps711x_bus_init(void) +{ + return platform_driver_register(&clps711x_bus_driver); +} +core_initcall(clps711x_bus_init); diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c deleted file mode 100644 index 8eacc70018..0000000000 --- a/arch/arm/mach-clps711x/devices.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include <common.h> -#include <init.h> -#include <linux/sizes.h> - -#include <asm/io.h> -#include <asm/memory.h> - -#include <mach/clps711x.h> -#include <mach/devices.h> - -static int clps711x_mem_init(void) -{ - ulong memsize = get_ram_size((ulong *)SDRAM0_BASE, SZ_64M); - - arm_add_mem_device("ram0", SDRAM0_BASE, memsize); - - return 0; -} -mem_initcall(clps711x_mem_init); - -inline static void _clps711x_setup_memcfg(int bank, u32 addr, u32 val) -{ - u32 tmp = readl(addr); - - tmp &= ~(0xff << (bank * 8)); - tmp |= val << (bank * 8); - - writel(tmp, addr); -} - -void clps711x_setup_memcfg(int bank, u32 val) -{ - switch (bank) { - case 0 ... 3: - _clps711x_setup_memcfg(bank, MEMCFG1, val); - break; - case 4 ... 5: - _clps711x_setup_memcfg(bank - 4, MEMCFG2, val); - break; - } -} - -static struct resource uart0_resources[] = { - DEFINE_RES_MEM(UARTDR1, SZ_128), -}; - -static struct resource uart1_resources[] = { - DEFINE_RES_MEM(UARTDR2, SZ_128), -}; - -void clps711x_add_uart(unsigned int id) -{ - switch (id) { - case 0: - add_generic_device_res("clps711x-uart", 0, uart0_resources, - ARRAY_SIZE(uart0_resources), NULL); - break; - case 1: - add_generic_device_res("clps711x-uart", 1, uart1_resources, - ARRAY_SIZE(uart1_resources), NULL); - break; - } -} - -static struct resource gpio0_resources[] = { - DEFINE_RES_MEM(PADR, SZ_1), - DEFINE_RES_MEM(PADDR, SZ_1), -}; - -static struct resource gpio1_resources[] = { - DEFINE_RES_MEM(PBDR, SZ_1), - DEFINE_RES_MEM(PBDDR, SZ_1), -}; - -static struct resource gpio2_resources[] = { - DEFINE_RES_MEM(PCDR, SZ_1), - DEFINE_RES_MEM(PCDDR, SZ_1), -}; - -static struct resource gpio3_resources[] = { - DEFINE_RES_MEM(PDDR, SZ_1), - DEFINE_RES_MEM(PDDDR, SZ_1), -}; - -static struct resource gpio4_resources[] = { - DEFINE_RES_MEM(PEDR, SZ_1), - DEFINE_RES_MEM(PEDDR, SZ_1), -}; - -static __init int clps711x_gpio_init(void) -{ - add_generic_device_res("clps711x-gpio", 0, gpio0_resources, - ARRAY_SIZE(gpio0_resources), NULL); - add_generic_device_res("clps711x-gpio", 1, gpio1_resources, - ARRAY_SIZE(gpio1_resources), NULL); - add_generic_device_res("clps711x-gpio", 2, gpio2_resources, - ARRAY_SIZE(gpio2_resources), NULL); - add_generic_device_res("clps711x-gpio", 3, gpio3_resources, - ARRAY_SIZE(gpio3_resources), NULL); - add_generic_device_res("clps711x-gpio", 4, gpio4_resources, - ARRAY_SIZE(gpio4_resources), NULL); - - return 0; -} -coredevice_initcall(clps711x_gpio_init); - -static __init int clps711x_syscon_init(void) -{ - /* SYSCON1, SYSFLG1 */ - add_generic_device("syscon", 1, NULL, SYSCON1, SZ_128, - IORESOURCE_MEM, NULL); - /* SYSCON2, SYSFLG2 */ - add_generic_device("syscon", 2, NULL, SYSCON2, SZ_128, - IORESOURCE_MEM, NULL); - - return 0; -} -postcore_initcall(clps711x_syscon_init); diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h deleted file mode 100644 index 957b2b8477..0000000000 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Hardware definitions for Cirrus Logic CLPS711X - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __MACH_CLPS711X_H -#define __MACH_CLPS711X_H - -#define CS0_BASE (0x00000000) -#define CS1_BASE (0x10000000) -#define CS2_BASE (0x20000000) -#define CS3_BASE (0x30000000) -#define CS4_BASE (0x40000000) -#define CS5_BASE (0x50000000) -#define CS6_BASE (0x60000000) -#define CS7_BASE (0x70000000) -#define REGS_BASE (0x80000000) -#define SDRAM0_BASE (0xc0000000) -#define SDRAM1_BASE (0xd0000000) - -#define PADR (REGS_BASE + 0x0000) -#define PBDR (REGS_BASE + 0x0001) -#define PCDR (REGS_BASE + 0x0002) -#define PDDR (REGS_BASE + 0x0003) -#define PADDR (REGS_BASE + 0x0040) -#define PBDDR (REGS_BASE + 0x0041) -#define PCDDR (REGS_BASE + 0x0042) -#define PDDDR (REGS_BASE + 0x0043) -#define PEDR (REGS_BASE + 0x0083) -#define PEDDR (REGS_BASE + 0x00c3) -#define SYSCON1 (REGS_BASE + 0x0100) -#define SYSFLG1 (REGS_BASE + 0x0140) -#define MEMCFG1 (REGS_BASE + 0x0180) -#define MEMCFG2 (REGS_BASE + 0x01c0) -#define DRFPR (REGS_BASE + 0x0200) -#define INTSR1 (REGS_BASE + 0x0240) -#define INTMR1 (REGS_BASE + 0x0280) -#define LCDCON (REGS_BASE + 0x02c0) -#define TC1D (REGS_BASE + 0x0300) -#define TC2D (REGS_BASE + 0x0340) -#define RTCDR (REGS_BASE + 0x0380) -#define RTCMR (REGS_BASE + 0x03c0) -#define PMPCON (REGS_BASE + 0x0400) -#define CODR (REGS_BASE + 0x0440) -#define UARTDR1 (REGS_BASE + 0x0480) -#define UBRLCR1 (REGS_BASE + 0x04c0) -#define SYNCIO (REGS_BASE + 0x0500) -#define PALLSW (REGS_BASE + 0x0540) -#define PALMSW (REGS_BASE + 0x0580) -#define STFCLR (REGS_BASE + 0x05c0) -#define BLEOI (REGS_BASE + 0x0600) -#define MCEOI (REGS_BASE + 0x0640) -#define TEOI (REGS_BASE + 0x0680) -#define TC1EOI (REGS_BASE + 0x06c0) -#define TC2EOI (REGS_BASE + 0x0700) -#define RTCEOI (REGS_BASE + 0x0740) -#define UMSEOI (REGS_BASE + 0x0780) -#define COEOI (REGS_BASE + 0x07c0) -#define HALT (REGS_BASE + 0x0800) -#define STDBY (REGS_BASE + 0x0840) - -#define FBADDR (REGS_BASE + 0x1000) -#define SYSCON2 (REGS_BASE + 0x1100) -#define SYSFLG2 (REGS_BASE + 0x1140) -#define INTSR2 (REGS_BASE + 0x1240) -#define INTMR2 (REGS_BASE + 0x1280) -#define UARTDR2 (REGS_BASE + 0x1480) -#define UBRLCR2 (REGS_BASE + 0x14c0) -#define SS2DR (REGS_BASE + 0x1500) -#define SRXEOF (REGS_BASE + 0x1600) -#define SS2POP (REGS_BASE + 0x16c0) -#define KBDEOI (REGS_BASE + 0x1700) - -#define DAIR (REGS_BASE + 0x2000) -#define DAIDR0 (REGS_BASE + 0x2040) -#define DAIDR1 (REGS_BASE + 0x2080) -#define DAIDR2 (REGS_BASE + 0x20c0) -#define DAISR (REGS_BASE + 0x2100) -#define SYSCON3 (REGS_BASE + 0x2200) -#define INTSR3 (REGS_BASE + 0x2240) -#define INTMR3 (REGS_BASE + 0x2280) -#define LEDFLSH (REGS_BASE + 0x22c0) -#define SDCONF (REGS_BASE + 0x2300) -#define SDRFPR (REGS_BASE + 0x2340) -#define UNIQID (REGS_BASE + 0x2440) -#define DAI64FS (REGS_BASE + 0x2600) -#define PLLW (REGS_BASE + 0x2610) -#define PLLR (REGS_BASE + 0xa5a8) -#define RANDID0 (REGS_BASE + 0x2700) -#define RANDID1 (REGS_BASE + 0x2704) -#define RANDID2 (REGS_BASE + 0x2708) -#define RANDID3 (REGS_BASE + 0x270c) - -#define SYSCON1_KBDSCAN(x) ((x) & 15) -#define SYSCON1_KBDSCANMASK (15) -#define SYSCON1_TC1M (1 << 4) -#define SYSCON1_TC1S (1 << 5) -#define SYSCON1_TC2M (1 << 6) -#define SYSCON1_TC2S (1 << 7) -#define SYSCON1_BZTOG (1 << 9) -#define SYSCON1_BZMOD (1 << 10) -#define SYSCON1_DBGEN (1 << 11) -#define SYSCON1_LCDEN (1 << 12) -#define SYSCON1_CDENTX (1 << 13) -#define SYSCON1_CDENRX (1 << 14) -#define SYSCON1_SIREN (1 << 15) -#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) -#define SYSCON1_ADCKSEL_MASK (3 << 16) -#define SYSCON1_EXCKEN (1 << 18) -#define SYSCON1_WAKEDIS (1 << 19) -#define SYSCON1_IRTXM (1 << 20) - -#define SYSFLG1_MCDR (1 << 0) -#define SYSFLG1_DCDET (1 << 1) -#define SYSFLG1_WUDR (1 << 2) -#define SYSFLG1_WUON (1 << 3) -#define SYSFLG1_CTS (1 << 8) -#define SYSFLG1_DSR (1 << 9) -#define SYSFLG1_DCD (1 << 10) -#define SYSFLG1_NBFLG (1 << 12) -#define SYSFLG1_RSTFLG (1 << 13) -#define SYSFLG1_PFFLG (1 << 14) -#define SYSFLG1_CLDFLG (1 << 15) -#define SYSFLG1_CRXFE (1 << 24) -#define SYSFLG1_CTXFF (1 << 25) -#define SYSFLG1_SSIBUSY (1 << 26) -#define SYSFLG1_ID (1 << 29) -#define SYSFLG1_VERID(x) (((x) >> 30) & 3) -#define SYSFLG1_VERID_MASK (3 << 30) - -#define SYSFLG2_SSRXOF (1 << 0) -#define SYSFLG2_RESVAL (1 << 1) -#define SYSFLG2_RESFRM (1 << 2) -#define SYSFLG2_SS2RXFE (1 << 3) -#define SYSFLG2_SS2TXFF (1 << 4) -#define SYSFLG2_SS2TXUF (1 << 5) -#define SYSFLG2_CKMODE (1 << 6) - -#define LCDCON_GSEN (1 << 30) -#define LCDCON_GSMD (1 << 31) - -#define SYSCON2_SERSEL (1 << 0) -#define SYSCON2_KBD6 (1 << 1) -#define SYSCON2_DRAMZ (1 << 2) -#define SYSCON2_KBWEN (1 << 3) -#define SYSCON2_SS2TXEN (1 << 4) -#define SYSCON2_PCCARD1 (1 << 5) -#define SYSCON2_PCCARD2 (1 << 6) -#define SYSCON2_SS2RXEN (1 << 7) -#define SYSCON2_SS2MAEN (1 << 9) -#define SYSCON2_OSTB (1 << 12) -#define SYSCON2_CLKENSL (1 << 13) -#define SYSCON2_BUZFREQ (1 << 14) - -#define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8) -#define SYNCIO_SMCKEN (1 << 13) -#define SYNCIO_TXFRMEN (1 << 14) - -#define DAIR_RESERVED (0x0404) -#define DAIR_DAIEN (1 << 16) -#define DAIR_ECS (1 << 17) -#define DAIR_LCTM (1 << 19) -#define DAIR_LCRM (1 << 20) -#define DAIR_RCTM (1 << 21) -#define DAIR_RCRM (1 << 22) -#define DAIR_LBM (1 << 23) - -#define DAIDR2_FIFOEN (1 << 15) -#define DAIDR2_FIFOLEFT (0x0d << 16) -#define DAIDR2_FIFORIGHT (0x11 << 16) - -#define DAISR_RCTS (1 << 0) -#define DAISR_RCRS (1 << 1) -#define DAISR_LCTS (1 << 2) -#define DAISR_LCRS (1 << 3) -#define DAISR_RCTU (1 << 4) -#define DAISR_RCRO (1 << 5) -#define DAISR_LCTU (1 << 6) -#define DAISR_LCRO (1 << 7) -#define DAISR_RCNF (1 << 8) -#define DAISR_RCNE (1 << 9) -#define DAISR_LCNF (1 << 10) -#define DAISR_LCNE (1 << 11) -#define DAISR_FIFO (1 << 12) - -#define DAI64FS_I2SF64 (1 << 0) -#define DAI64FS_AUDIOCLKEN (1 << 1) -#define DAI64FS_AUDIOCLKSRC (1 << 2) -#define DAI64FS_MCLK256EN (1 << 3) -#define DAI64FS_LOOPBACK (1 << 5) -#define DAI64FS_AUDIV_MASK (0x7f) -#define DAI64FS_AUDIV(x) (((x) & DAI64FS_AUDIV_MASK) << 8) - -#define SYSCON3_ADCCON (1 << 0) -#define SYSCON3_CLKCTL0 (1 << 1) -#define SYSCON3_CLKCTL1 (1 << 2) -#define SYSCON3_DAISEL (1 << 3) -#define SYSCON3_ADCCKNSEN (1 << 4) -#define SYSCON3_VERSN(x) (((x) >> 5) & 7) -#define SYSCON3_VERSN_MASK (7 << 5) -#define SYSCON3_FASTWAKE (1 << 8) -#define SYSCON3_DAIEN (1 << 9) -#define SYSCON3_128FS SYSCON3_DAIEN -#define SYSCON3_ENPD67 (1 << 10) - -#define SDCONF_ACTIVE (1 << 10) -#define SDCONF_CLKCTL (1 << 9) -#define SDCONF_WIDTH_4 (0 << 7) -#define SDCONF_WIDTH_8 (1 << 7) -#define SDCONF_WIDTH_16 (2 << 7) -#define SDCONF_WIDTH_32 (3 << 7) -#define SDCONF_SIZE_16 (0 << 5) -#define SDCONF_SIZE_64 (1 << 5) -#define SDCONF_SIZE_128 (2 << 5) -#define SDCONF_SIZE_256 (3 << 5) -#define SDCONF_CASLAT_2 (2) -#define SDCONF_CASLAT_3 (3) - -#define MEMCFG_BUS_WIDTH_32 (1) -#define MEMCFG_BUS_WIDTH_16 (0) -#define MEMCFG_BUS_WIDTH_8 (3) - -#define MEMCFG_SQAEN (1 << 6) -#define MEMCFG_CLKENB (1 << 7) - -#define MEMCFG_WAITSTATE_8_3 (0 << 2) -#define MEMCFG_WAITSTATE_7_3 (1 << 2) -#define MEMCFG_WAITSTATE_6_3 (2 << 2) -#define MEMCFG_WAITSTATE_5_3 (3 << 2) -#define MEMCFG_WAITSTATE_4_2 (4 << 2) -#define MEMCFG_WAITSTATE_3_2 (5 << 2) -#define MEMCFG_WAITSTATE_2_2 (6 << 2) -#define MEMCFG_WAITSTATE_1_2 (7 << 2) -#define MEMCFG_WAITSTATE_8_1 (8 << 2) -#define MEMCFG_WAITSTATE_7_1 (9 << 2) -#define MEMCFG_WAITSTATE_6_1 (10 << 2) -#define MEMCFG_WAITSTATE_5_1 (11 << 2) -#define MEMCFG_WAITSTATE_4_0 (12 << 2) -#define MEMCFG_WAITSTATE_3_0 (13 << 2) -#define MEMCFG_WAITSTATE_2_0 (14 << 2) -#define MEMCFG_WAITSTATE_1_0 (15 << 2) - -void clps711x_barebox_entry(u32, void *); - -#endif diff --git a/arch/arm/mach-clps711x/include/mach/devices.h b/arch/arm/mach-clps711x/include/mach/devices.h deleted file mode 100644 index 18a251a1d9..0000000000 --- a/arch/arm/mach-clps711x/include/mach/devices.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __MACH_DEVICES_H -#define __MACH_DEVICES_H - -void clps711x_setup_memcfg(int bank, u32 val); -void clps711x_add_uart(unsigned int id); - -#endif diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c index 35b8b35e87..2ede50538a 100644 --- a/arch/arm/mach-clps711x/lowlevel.c +++ b/arch/arm/mach-clps711x/lowlevel.c @@ -1,25 +1,31 @@ -/* - * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> +#include <asm/io.h> +#include <asm/barebox-arm.h> #include <common.h> -#include <init.h> +#include <debug_ll.h> #include <linux/sizes.h> +#include <mach/clps711x/clps711x.h> -#include <asm/io.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> +#define DEBUG_LL_BAUDRATE (57600) + +static inline void setup_uart(const u32 bus_speed) +{ + u32 baud_base = DIV_ROUND_CLOSEST(bus_speed, 10); + u32 baud_divisor = + DIV_ROUND_CLOSEST(baud_base, DEBUG_LL_BAUDRATE * 16) - 1; + + writel(baud_divisor | UBRLCR_FIFOEN | UBRLCR_WRDLEN8, UBRLCR1); + writel(0, STFCLR); + writel(SYSCON_UARTEN, SYSCON1); -#include <mach/clps711x.h> + putc_ll('>'); +} -void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data) +void clps711x_start(void *fdt) { - u32 cpu, bus; + u32 bus, pll; /* Check if we running from external 13 MHz clock */ if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) { @@ -27,24 +33,17 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data) writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3); asm("nop"); - /* Check valid multiplier, default to 74 MHz */ - if ((pllmult < 20) || (pllmult > 50)) - pllmult = 40; - - /* Setup PLL */ - writel(pllmult << 24, PLLW); - asm("nop"); + if (IS_ENABLED(CONFIG_CLPS711X_RAISE_CPUFREQ)) { + /* Setup PLL to 92160000 Hz */ + writel(50 << 24, PLLW); + asm("nop"); + } - /* Check for old CPUs without PLL */ - if ((readl(PLLR) >> 24) != pllmult) - cpu = 73728000; + pll = readl(PLLR) >> 24; + if (pll) + bus = (pll * 3686400) / 4; else - cpu = pllmult * 3686400; - - if (cpu >= 36864000) - bus = cpu / 2; - else - bus = 36864000 / 2; + bus = 73728000 / 4; } else { bus = 13000000; /* Setup bus wait state scaling factor to 1 */ @@ -52,6 +51,13 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data) asm("nop"); } + + /* Disable UART, IrDa, LCD */ + writel(0, SYSCON1); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(bus); + /* CLKEN select, SDRAM width=32 */ writel(SYSCON2_CLKENSL, SYSCON2); @@ -62,12 +68,10 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult, void *data) /* Setup Refresh Rate (64ms 8K Blocks) */ writel((64 * bus) / (8192 * 1000), SDRFPR); - /* Disable UART, IrDa, LCD */ - writel(0, SYSCON1); /* Disable PWM */ writew(0, PMPCON); /* Disable LED flasher */ writew(0, LEDFLSH); - barebox_arm_entry(SDRAM0_BASE, SZ_8M, data); + barebox_arm_entry(SDRAM0_BASE, SZ_8M, fdt); } diff --git a/arch/arm/mach-clps711x/reset.c b/arch/arm/mach-clps711x/reset.c deleted file mode 100644 index 90ddb8f5d2..0000000000 --- a/arch/arm/mach-clps711x/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include <common.h> -#include <init.h> -#include <restart.h> - -static void __noreturn clps711x_restart_soc(struct restart_handler *rst) -{ - shutdown_barebox(); - - asm("mov pc, #0"); - - hang(); -} - -static int restart_register_feature(void) -{ - restart_handler_register_fn("vector", clps711x_restart_soc); - - return 0; -} -coredevice_initcall(restart_register_feature); |