diff options
Diffstat (limited to 'arch/arm/mach-mxs')
24 files changed, 2801 insertions, 0 deletions
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig new file mode 100644 index 0000000000..f9cefaf907 --- /dev/null +++ b/arch/arm/mach-mxs/Kconfig @@ -0,0 +1,85 @@ +if ARCH_MXS + +config ARCH_TEXT_BASE + hex + default 0x41000000 if MACH_MX23EVK + default 0x42000000 if MACH_CHUMBY + default 0x47000000 if MACH_TX28 + +config BOARDINFO + default "Freescale i.MX23-EVK" if MACH_MX23EVK + default "Chumby Falconwing" if MACH_CHUMBY + default "Karo TX28" if MACH_TX28 + +comment "Freescale i.MX System-on-Chip" + +choice + prompt "Freescale i.MX Processor" + +config ARCH_IMX23 + bool "i.MX23" + select CPU_ARM926T + +config ARCH_IMX28 + bool "i.MX28" + select CPU_ARM926T + select ARCH_HAS_FEC_IMX + +endchoice + +if ARCH_IMX23 + +choice + prompt "i.MX23 Board Type" + +config MACH_MX23EVK + bool "mx23-evk" + help + Say Y here if you are using the Freescale i.MX23-EVK board + +config MACH_CHUMBY + bool "Chumby Falconwing" + select HAVE_MMU + help + Say Y here if you are using the "chumby one" aka falconwing from + Chumby Industries + +endchoice + +endif + +if ARCH_IMX28 + +choice + prompt "i.MX28 Board Type" + +config MACH_TX28 + bool "KARO tx28" + select HAVE_MMU + help + Say Y here if you are using the KARO TX28 CPU module. + +endchoice + +endif + +menu "Board specific settings " + +if MACH_TX28 + +choice + prompt "TX28 Base Board Type" + +config MACH_TX28STK5 + bool "TX28-stk5" + help + Select this entry if you are running the TX28 CPU module on the + KARO TX28 Starterkit5. + +endchoice + +endif + +endmenu + +endif diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile new file mode 100644 index 0000000000..f70a9944cf --- /dev/null +++ b/arch/arm/mach-mxs/Makefile @@ -0,0 +1,4 @@ +obj-y += imx.o iomux-imx.o reset-imx.o +obj-$(CONFIG_DRIVER_VIDEO_STM) += imx_lcd_clk.o +obj-$(CONFIG_ARCH_IMX23) += speed-imx23.o clocksource-imx23.o usb.o +obj-$(CONFIG_ARCH_IMX28) += speed-imx28.o clocksource-imx28.o diff --git a/arch/arm/mach-mxs/clocksource-imx23.c b/arch/arm/mach-mxs/clocksource-imx23.c new file mode 100644 index 0000000000..f7c94c1d75 --- /dev/null +++ b/arch/arm/mach-mxs/clocksource-imx23.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <init.h> +#include <clock.h> +#include <notifier.h> +#include <mach/imx-regs.h> +#include <mach/clock.h> +#include <asm/io.h> + +#define TIMROTCTRL 0x00 +#define TIMCTRL1 0x40 +#define TIMCTRL1_SET 0x44 +#define TIMCTRL1_CLR 0x48 +#define TIMCTRL1_TOG 0x4c +# define TIMCTRL_RELOAD (1 << 6) +# define TIMCTRL_UPDATE (1 << 7) +# define TIMCTRL_PRESCALE(x) ((x & 0x3) << 4) +# define TIMCTRL_SELECT(x) (x & 0xf) +#define TIMCOUNT1 0x50 + +static const unsigned long timer_base = IMX_TIM1_BASE; + +#define CLOCK_TICK_RATE (32000) + +static uint64_t imx23_clocksource_read(void) +{ + /* only the upper bits are the valid */ + return ~(readl(timer_base + TIMCOUNT1) >> 16); +} + +static struct clocksource cs = { + .read = imx23_clocksource_read, + .mask = CLOCKSOURCE_MASK(16), + .shift = 10, +}; + +static int imx23_clocksource_clock_change(struct notifier_block *nb, unsigned long event, void *data) +{ + cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE/*imx_get_xclk()*/, cs.shift); + return 0; +} + +static struct notifier_block imx23_clock_notifier = { + .notifier_call = imx23_clocksource_clock_change, +}; + +static int clocksource_init(void) +{ + /* enable the whole timer block */ + writel(0x3e000000, timer_base + TIMROTCTRL); + /* setup general purpose timer 1 */ + writel(0x00000000, timer_base + TIMCTRL1); + writel(TIMCTRL_UPDATE, timer_base + TIMCTRL1); + writel(0x0000ffff, timer_base + TIMCOUNT1); + + writel(TIMCTRL_UPDATE | TIMCTRL_RELOAD | TIMCTRL_PRESCALE(0) | TIMCTRL_SELECT(8), timer_base + TIMCTRL1); + cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE/*imx_get_xclk()*/, cs.shift); + init_clock(&cs); + + clock_register_client(&imx23_clock_notifier); + return 0; +} + +core_initcall(clocksource_init); diff --git a/arch/arm/mach-mxs/clocksource-imx28.c b/arch/arm/mach-mxs/clocksource-imx28.c new file mode 100644 index 0000000000..15ae951004 --- /dev/null +++ b/arch/arm/mach-mxs/clocksource-imx28.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <clock.h> +#include <notifier.h> +#include <mach/imx-regs.h> +#include <mach/clock.h> +#include <asm/io.h> + +#define TIMROTCTRL 0x00 +# define TIMROTCTRL_SFTRST +# define TIMROTCTRL_CLKGATE +# define TIMROTCTRL_DIVIDER(x) ((x & 0x3f) << 16) + +#define TIMCTRL1 0x60 +#define TIMCTRL1_SET 0x64 +#define TIMCTRL1_CLR 0x68 +#define TIMCTRL1_TOG 0x6c +# define TIMCTRL_RELOAD (1 << 6) +# define TIMCTRL_UPDATE (1 << 7) +# define TIMCTRL_PRESCALE(x) ((x & 0x3) << 4) +# define TIMCTRL_SELECT(x) (x & 0xf) +#define TIMCOUNT1 0x70 +#define TIMFIX1 0x80 + +static const void __iomem * timer_base = (void *)IMX_TIM1_BASE; + +/* we are using the 32 kHz reference */ +#define CLOCK_TICK_RATE 32000 + +static uint64_t imx28_clocksource_read(void) +{ + return ~(readl(timer_base + TIMCOUNT1)); +} + +static struct clocksource imx28_cs = { + .read = imx28_clocksource_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 17, +}; + +static int imx28_clocksource_init(void) +{ + /* enable the whole timer block */ + writel(0x00000000, timer_base + TIMROTCTRL); + /* setup start value of the general purpose timer */ + writel(0x00000000, timer_base + TIMCTRL1); + writel(TIMCTRL_UPDATE, timer_base + TIMCTRL1); + /* setup the reload value of the general purpose timer */ + writel(0xffffffff, timer_base + TIMFIX1); + + writel(TIMCTRL_UPDATE | TIMCTRL_RELOAD | TIMCTRL_PRESCALE(0) | + TIMCTRL_SELECT(0xb), timer_base + TIMCTRL1); + imx28_cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE, imx28_cs.shift); + init_clock(&imx28_cs); + + return 0; +} + +core_initcall(imx28_clocksource_init); diff --git a/arch/arm/mach-mxs/imx.c b/arch/arm/mach-mxs/imx.c new file mode 100644 index 0000000000..14a4249893 --- /dev/null +++ b/arch/arm/mach-mxs/imx.c @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +extern void imx_dump_clocks(void); + +static int do_clocks(struct command *cmdtp, int argc, char *argv[]) +{ + imx_dump_clocks(); + + return 0; +} + +BAREBOX_CMD_START(dump_clocks) + .cmd = do_clocks, + .usage = "show clock frequencies", +BAREBOX_CMD_END diff --git a/arch/arm/mach-mxs/imx_lcd_clk.c b/arch/arm/mach-mxs/imx_lcd_clk.c new file mode 100644 index 0000000000..65bfc6ee3d --- /dev/null +++ b/arch/arm/mach-mxs/imx_lcd_clk.c @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <mach/imx-regs.h> +#include <mach/clock.h> +#include <asm/io.h> + +#ifdef CONFIG_ARCH_IMX23 + +# define HW_CLKCTRL_DIS_LCDIF 0x060 +# define CLKCTRL_DIS_LCDIF_GATE (1 << 31) +# define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) +# define MASK_DIS_LCDIF_DIV 0xfff +# define SET_DIS_LCDIF_DIV(x) ((x) & MASK_DIS_LCDIF_DIV) +# define GET_DIS_LCDIF_DIV(x) ((x) & MASK_DIS_LCDIF_DIV) + +# define HW_CLKCTRL_FRAC 0xf0 +# define MASK_PIXFRAC 0x3f +# define GET_PIXFRAC(x) (((x) >> 16) & MASK_PIXFRAC) +# define SET_PIXFRAC(x) (((x) & MASK_PIXFRAC) << 16) +# define CLKCTRL_FRAC_CLKGATEPIX (1 << 23) + +# define HW_CLKCTRL_CLKSEQ 0x110 +# define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 1) + +#endif + +#ifdef CONFIG_ARCH_IMX28 + +# define HW_CLKCTRL_DIS_LCDIF 0x120 +# define CLKCTRL_DIS_LCDIF_GATE (1 << 31) +# define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) +# define MASK_DIS_LCDIF_DIV 0x1fff +# define SET_DIS_LCDIF_DIV(x) ((x) & MASK_DIS_LCDIF_DIV) +# define GET_DIS_LCDIF_DIV(x) ((x) & MASK_DIS_LCDIF_DIV) + +/* note: On i.MX28 this is called 'FRAC1' */ +# define HW_CLKCTRL_FRAC 0x1c0 +# define MASK_PIXFRAC 0x3f +# define GET_PIXFRAC(x) ((x) & MASK_PIXFRAC) +# define SET_PIXFRAC(x) ((x) & MASK_PIXFRAC) +# define CLKCTRL_FRAC_CLKGATEPIX (1 << 7) + +# define HW_CLKCTRL_CLKSEQ 0x1d0 +# define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) + +#endif + +unsigned imx_get_lcdifclk(void) +{ + unsigned rate = (imx_get_mpllclk() / 1000) * 18U; + unsigned div; + + div = GET_PIXFRAC(readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC)); + if (div != 0U) { + rate /= div; + div = GET_DIS_LCDIF_DIV(readl(IMX_CCM_BASE + + HW_CLKCTRL_DIS_LCDIF)); + if (div != 0U) + rate /= div; + else + pr_debug("LCDIF clock has divisor 0!\n"); + } else + pr_debug("LCDIF clock has frac divisor 0!\n"); + + return rate * 1000; +} + +/* + * The source of the pixel clock can be the external 24 MHz crystal or the + * internal PLL running at 480 MHz. In order to support at least VGA sized + * displays/resolutions this routine forces the PLL as the clock source. + */ +unsigned imx_set_lcdifclk(unsigned nc) +{ + unsigned frac, best_frac = 0, div, best_div = 0, result; + int delta, best_delta = 0xffffff; + unsigned i, parent_rate = imx_get_mpllclk() / 1000; + uint32_t reg; + +#define SH_DIV(NOM, DEN, LSH) ((((NOM) / (DEN)) << (LSH)) + \ + DIV_ROUND_CLOSEST(((NOM) % (DEN)) << (LSH), DEN)) +#define SHIFT 4 + + nc /= 1000; + nc <<= SHIFT; + + for (frac = 18; frac <= 35; ++frac) { + for (div = 1; div <= 255; ++div) { + result = DIV_ROUND_CLOSEST(parent_rate * + SH_DIV(18U, frac, SHIFT), div); + delta = nc - result; + if (abs(delta) < abs(best_delta)) { + best_delta = delta; + best_frac = frac; + best_div = div; + } + } + } + + if (best_delta == 0xffffff) { + pr_debug("Unable to match the pixelclock\n"); + return 0; + } + + pr_debug("Programming PFD=%u,DIV=%u ref_pix=%u MHz PIXCLK=%u kHz\n", + best_frac, best_div, 480 * 18 / best_frac, + 480000 * 18 / best_frac / best_div); + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC); + reg &= ~SET_PIXFRAC(MASK_PIXFRAC); + reg |= SET_PIXFRAC(best_frac); + writel(reg, IMX_CCM_BASE + HW_CLKCTRL_FRAC); + writel(reg & ~CLKCTRL_FRAC_CLKGATEPIX, IMX_CCM_BASE + HW_CLKCTRL_FRAC); + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF) & ~MASK_DIS_LCDIF_DIV; + reg &= ~CLKCTRL_DIS_LCDIF_GATE; + reg |= SET_DIS_LCDIF_DIV(best_div); + writel(reg, IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF); + + /* Wait for divider update */ + for (i = 0; i < 10000; i++) { + if (!(readl(IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF) & + CLKCTRL_DIS_LCDIF_BUSY)) + break; + } + + if (i >= 10000) { + pr_debug("Setting LCD clock failed\n"); + return 0; + } + + writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, + IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + BIT_CLR); + + return imx_get_lcdifclk(); +} diff --git a/arch/arm/mach-mxs/include/mach/clock-imx23.h b/arch/arm/mach-mxs/include/mach/clock-imx23.h new file mode 100644 index 0000000000..723f343566 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/clock-imx23.h @@ -0,0 +1,28 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MACH_CLOCK_IMX23_H +# define MACH_CLOCK_IMX23_H + +unsigned imx_get_mpllclk(void); +unsigned imx_get_emiclk(void); +unsigned imx_get_ioclk(void); +unsigned imx_get_armclk(void); +unsigned imx_get_hclk(void); +unsigned imx_get_xclk(void); +unsigned imx_get_sspclk(unsigned); +unsigned imx_set_sspclk(unsigned, unsigned, int); +unsigned imx_set_ioclk(unsigned); +unsigned imx_set_lcdifclk(unsigned); +unsigned imx_get_lcdifclk(void); + +#endif /* MACH_CLOCK_IMX23_H */ diff --git a/arch/arm/mach-mxs/include/mach/clock-imx28.h b/arch/arm/mach-mxs/include/mach/clock-imx28.h new file mode 100644 index 0000000000..45fb043ac4 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/clock-imx28.h @@ -0,0 +1,31 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MACH_CLOCK_IMX28_H +#define MACH_CLOCK_IMX28_H + +unsigned imx_get_mpllclk(void); +unsigned imx_get_emiclk(void); +unsigned imx_get_ioclk(unsigned); +unsigned imx_get_armclk(void); +unsigned imx_get_hclk(void); +unsigned imx_get_xclk(void); +unsigned imx_get_sspclk(unsigned); +unsigned imx_set_sspclk(unsigned, unsigned, int); +unsigned imx_set_ioclk(unsigned, unsigned); +unsigned imx_set_lcdifclk(unsigned); +unsigned imx_get_lcdifclk(void); +unsigned imx_get_fecclk(void); +void imx_enable_enetclk(void); + +#endif /* MACH_CLOCK_IMX28_H */ + diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h new file mode 100644 index 0000000000..bd1fa7c849 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/clock.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MACH_CLOCK_H +# define __MACH_CLOCK_H + +#if defined CONFIG_ARCH_IMX23 +# include <mach/clock-imx23.h> +#endif +#if defined CONFIG_ARCH_IMX28 +# include <mach/clock-imx28.h> +#endif + +#endif /* __MACH_CLOCK_H */ diff --git a/arch/arm/mach-mxs/include/mach/fb.h b/arch/arm/mach-mxs/include/mach/fb.h new file mode 100644 index 0000000000..5346306311 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/fb.h @@ -0,0 +1,48 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_FB_H +# define __MACH_FB_H + +#include <fb.h> + +#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ +#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ +#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ +#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ + +/** LC display uses active high data enable signal */ +#define FB_SYNC_DE_HIGH_ACT (1 << 27) +/** LC display will latch its data at clock's rising edge */ +#define FB_SYNC_CLK_INVERT (1 << 28) +/** output RGB digital data inverted */ +#define FB_SYNC_DATA_INVERT (1 << 29) +/** Stop clock if no data is sent (required for passive displays) */ +#define FB_SYNC_CLK_IDLE_DIS (1 << 30) +/** swap RGB to BGR */ +#define FB_SYNC_SWAP_RGB (1 << 31) + +struct imx_fb_platformdata { + struct fb_videomode *mode_list; + unsigned mode_cnt; + + unsigned dotclk_delay; /**< refer manual HW_LCDIF_VDCTRL4 register */ + unsigned ld_intf_width; /**< refer STMLCDIF_* macros */ + + void *fixed_screen; /**< if != NULL use this as framebuffer memory */ + unsigned fixed_screen_size; /**< framebuffer memory size for fixed_screen */ + + void (*enable)(int enable); /**< hook to enable backlight */ +}; + +#endif /* __MACH_FB_H */ + diff --git a/arch/arm/mach-mxs/include/mach/generic.h b/arch/arm/mach-mxs/include/mach/generic.h new file mode 100644 index 0000000000..50f25c5d1b --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/generic.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifdef CONFIG_ARCH_IMX23 +# define cpu_is_mx23() (1) +#else +# define cpu_is_mx23() (0) +#endif + +#ifdef CONFIG_ARCH_IMX28 +# define cpu_is_mx28() (1) +#else +# define cpu_is_mx28() (0) +#endif diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h new file mode 100644 index 0000000000..c419926214 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/gpio.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_MACH_GPIO_H +#define __ASM_MACH_GPIO_H + +#include <types.h> + +#if defined CONFIG_ARCH_IMX23 +# include <mach/iomux-imx23.h> +#endif +#if defined CONFIG_ARCH_IMX28 +# include <mach/iomux-imx28.h> +#endif + +void imx_gpio_mode(uint32_t); +void gpio_set_value(unsigned, int); +int gpio_direction_input(unsigned); +int gpio_direction_output(unsigned, int); +int gpio_get_value(unsigned); + +#endif /* __ASM_MACH_GPIO_H */ diff --git a/arch/arm/mach-mxs/include/mach/imx-regs.h b/arch/arm/mach-mxs/include/mach/imx-regs.h new file mode 100644 index 0000000000..9b33a0656c --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/imx-regs.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_REGS_H +# define _IMX_REGS_H + +/* Note: Some registers do not support this bit change feature! */ +#define BIT_SET 0x04 +#define BIT_CLR 0x08 +#define BIT_TGL 0x0C + +#if defined CONFIG_ARCH_IMX23 +# include <mach/imx23-regs.h> +#endif + +#if defined CONFIG_ARCH_IMX28 +# include <mach/imx28-regs.h> +#endif + +#endif /* _IMX_REGS_H */ diff --git a/arch/arm/mach-mxs/include/mach/imx23-regs.h b/arch/arm/mach-mxs/include/mach/imx23-regs.h new file mode 100644 index 0000000000..cc8c03e8bb --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/imx23-regs.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MX23_REGS_H +#define __ASM_ARCH_MX23_REGS_H + +/* + * sanity check + */ +#ifndef _IMX_REGS_H +# error "Please do not include directly. Use imx-regs.h instead." +#endif + +#define IMX_MEMORY_BASE 0x40000000 +#define IMX_UART1_BASE 0x8006c000 +#define IMX_UART2_BASE 0x8006e000 +#define IMX_DBGUART_BASE 0x80070000 +#define IMX_TIM1_BASE 0x80068000 +#define IMX_IOMUXC_BASE 0x80018000 +#define IMX_WDT_BASE 0x8005c000 +#define IMX_CCM_BASE 0x80040000 +#define IMX_I2C1_BASE 0x80058000 +#define IMX_SSP1_BASE 0x80010000 +#define IMX_FB_BASE 0x80030000 +#define IMX_SSP2_BASE 0x80034000 +#define IMX_POWER_BASE 0x80044000 +#define IMX_USBPHY_BASE 0x8007c000 +#define IMX_DIGCTL_BASE 0x8001c000 +#define IMX_USB_BASE 0x80080000 + +#endif /* __ASM_ARCH_MX23_REGS_H */ diff --git a/arch/arm/mach-mxs/include/mach/imx28-regs.h b/arch/arm/mach-mxs/include/mach/imx28-regs.h new file mode 100644 index 0000000000..0c97c4c2f2 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/imx28-regs.h @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_MX28_REGS_H +#define __ASM_ARCH_MX28_REGS_H + +/* + * sanity check + */ +#ifndef _IMX_REGS_H +# error "Please do not include directly. Use imx-regs.h instead." +#endif + +#define IMX_SRAM_BASE 0x00000000 +#define IMX_MEMORY_BASE 0x40000000 + +#define IMX_NFC_BASE 0x8000C000 +#define IMX_SSP0_BASE 0x80010000 +#define IMX_SSP1_BASE 0x80012000 +#define IMX_SSP2_BASE 0x80014000 +#define IMX_SSP3_BASE 0x80016000 +#define IMX_IOMUXC_BASE 0x80018000 +#define IMX_FB_BASE 0x80030000 +#define IMX_CCM_BASE 0x80040000 +#define IMX_WDT_BASE 0x80056000 +#define IMX_I2C0_BASE 0x80058000 +#define IMX_I2C1_BASE 0x8005a000 +#define IMX_TIM1_BASE 0x80068000 +#define IMX_UART0_BASE 0x8006a000 +#define IMX_UART1_BASE 0x8006c000 +#define IMX_UART2_BASE 0x8006e000 +#define IMX_UART3_BASE 0x80070000 +#define IMX_UART4_BASE 0x80072000 +#define IMX_DBGUART_BASE 0x80074000 +#define IMX_FEC0_BASE 0x800F0000 +#define IMX_FEC1_BASE 0x800F4000 + +#endif /* __ASM_ARCH_MX28_REGS_H */ diff --git a/arch/arm/mach-mxs/include/mach/iomux-imx23.h b/arch/arm/mach-mxs/include/mach/iomux-imx23.h new file mode 100644 index 0000000000..bebaf56571 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/iomux-imx23.h @@ -0,0 +1,424 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +/* 3322222222221111111111 + * 10987654321098765432109876543210 + * ^^^_ Register Number + * ^^^^____ Bit offset + * ^^________ Function + * ^__________ Drive strength feature present + * ^___________ Pull up / bit keeper present + * ^^____________ Drive strength setting + * ^______________ Pull up / bit keeper setting + * ^_______________ Voltage select present + * ^________________ Voltage selection + * ^____________________ direction if enabled as GPIO (1 = output) + * ^_____________________ initial output value if enabled as GPIO and configured as output + */ +#ifndef __ASM_MACH_IOMUX_H +#define __ASM_MACH_IOMUX_H + +/* control pad's function */ +#define FBIT_SHIFT (3) +#define PORTF(bank,bit) (((bit) << FBIT_SHIFT) | (bank)) +#define GET_PORTF(x) ((x) & 0x7) +#define GET_FBITPOS(x) (((x) >> FBIT_SHIFT) & 0xf) +#define GET_GPIO_NO(x) ((GET_PORTF(x) << 4) + GET_FBITPOS(m)) +#define FUNC_SHIFT 7 +#define FUNC(x) ((x) << FUNC_SHIFT) +#define GET_FUNC(x) (((x) >> FUNC_SHIFT) & 3) +#define IS_GPIO (3) + +/* control pad's GPIO feature if enabled */ +#define GPIO_OUT (1 << 19) +#define GPIO_VALUE(x) ((x) << 20) +#define GPIO_IN (0 << 19) +#define GET_GPIODIR(x) (!!((x) & (1 << 19))) +#define GET_GPIOVAL(x) (!!((x) & (1 << 20))) + +/* control pad's drive strength */ +#define SE (1 << 9) +#define SE_PRESENT(x) (!!((x) & SE)) +#define STRENGTH(x) ((x) << 11) +#define S4MA 0 /* used to define a 4 mA drive strength */ +#define S8MA 1 /* used to define a 8 mA drive strength */ +#define S12MA 2 /* used to define a 12 mA drive strength */ +#define S16MA 3 /* used to define a 16 mA drive strength, not all pads can drive this current! */ +#define GET_STRENGTH(x) (((x) >> 11) & 0x3) + +/* control pad's pull up / bit keeper feature */ +#define PE (1 << 10) +#define PE_PRESENT(x) (!!((x) & PE)) +#define PULLUP(x) ((x) << 13) +#define GET_PULLUP(x) (!!((x) & (1 << 13))) + +/* control pad's voltage feature */ +#define VE (1 << 14) +#define VE_PRESENT(x) (!!((x) & VE)) +#define VE_1_8V (0 << 15) +#define VE_2_5V (0 << 15) /* don't ask my why, RTFM */ +#define GET_VOLTAGE(x) (!!((x) & (1 << 15))) + +/* Bank 0, pins 0 ... 15, GPIO pins 0 ... 15 */ +#define GPMI_D15 (FUNC(0) | PORTF(0, 15) | SE | PE) +#define GPMI_D15_AUART2_TX (FUNC(1) | PORTF(0, 15) | SE | PE) +#define GPMI_D15_GPMI_CE3N (FUNC(2) | PORTF(0, 15) | SE | PE) +#define GPMI_D15_GPIO (FUNC(3) | PORTF(0, 15) | SE | PE) +#define GPMI_D14 (FUNC(0) | PORTF(0, 14) | SE) +#define GPMI_D14_AUART2_RX (FUNC(1) | PORTF(0, 14) | SE) +#define GPMI_D14_GPIO (FUNC(3) | PORTF(0, 14) | SE) +#define GPMI_D13 (FUNC(0) | PORTF(0, 13) | SE) +#define GPMI_D13_LCD_D23 (FUNC(1) | PORTF(0, 13) | SE) +#define GPMI_D13_GPIO (FUNC(3) | PORTF(0, 13) | SE) +#define GPMI_D12 (FUNC(0) | PORTF(0, 12) | SE) +#define GPMI_D12_LCD_D22 (FUNC(1) | PORTF(0, 12) | SE) +#define GPMI_D12_GPIO (FUNC(3) | PORTF(0, 12) | SE) +#define GPMI_D11 (FUNC(0) | PORTF(0, 11) | SE | PE) +#define GPMI_D11_LCD_D21 (FUNC(1) | PORTF(0, 11) | SE | PE) +#define GPMI_D11_SSP1_D7 (FUNC(2) | PORTF(0, 11) | SE | PE) +#define GPMI_D11_GPIO (FUNC(3) | PORTF(0, 11) | SE | PE) +#define GPMI_D10 (FUNC(0) | PORTF(0, 10) | SE | PE) +#define GPMI_D10_LCD_D20 (FUNC(1) | PORTF(0, 10) | SE | PE) +#define GPMI_D10_SSP1_D6 (FUNC(2) | PORTF(0, 10) | SE | PE) +#define GPMI_D10_GPIO (FUNC(3) | PORTF(0, 10) | SE | PE) +#define GPMI_D09 (FUNC(0) | PORTF(0, 9) | SE | PE) +#define GPMI_D09_LCD_D19 (FUNC(1) | PORTF(0, 9) | SE | PE) +#define GPMI_D09_SSP1_D5 (FUNC(2) | PORTF(0, 9) | SE | PE) +#define GPMI_D09_GPIO (FUNC(3) | PORTF(0, 9) | SE | PE) +#define GPMI_D08 (FUNC(0) | PORTF(0, 8) | SE | PE) +#define GPMI_D08_LCD_D18 (FUNC(1) | PORTF(0, 8) | SE | PE) +#define GPMI_D08_SSP1_D4 (FUNC(2) | PORTF(0, 8) | SE | PE) +#define GPMI_D08_GPIO (FUNC(3) | PORTF(0, 8) | SE | PE) +#define GPMI_D07 (FUNC(0) | PORTF(0, 7) | SE | PE) +#define GPMI_D07_LCD_D15 (FUNC(1) | PORTF(0, 7) | SE | PE) +#define GPMI_D07_SSP2_D7 (FUNC(2) | PORTF(0, 7) | SE | PE) +#define GPMI_D07_GPIO (FUNC(3) | PORTF(0, 7) | SE | PE) +#define GPMI_D06 (FUNC(0) | PORTF(0, 6) | SE | PE) +#define GPMI_D06_LCD_D14 (FUNC(1) | PORTF(0, 6) | SE | PE) +#define GPMI_D06_SSP2_D6 (FUNC(2) | PORTF(0, 6) | SE | PE) +#define GPMI_D06_GPIO (FUNC(3) | PORTF(0, 6) | SE | PE) +#define GPMI_D05 (FUNC(0) | PORTF(0, 5) | SE | PE) +#define GPMI_D05_LCD_D13 (FUNC(1) | PORTF(0, 5) | SE | PE) +#define GPMI_D05_SSP2_D5 (FUNC(2) | PORTF(0, 5) | SE | PE) +#define GPMI_D05_GPIO (FUNC(3) | PORTF(0, 5) | SE | PE) +#define GPMI_D04 (FUNC(0) | PORTF(0, 4) | SE | PE) +#define GPMI_D04_LCD_D12 (FUNC(1) | PORTF(0, 4) | SE | PE) +#define GPMI_D04_SSP2_D4 (FUNC(2) | PORTF(0, 4) | SE | PE) +#define GPMI_D04_GPIO (FUNC(3) | PORTF(0, 4) | SE | PE) +#define GPMI_D03 (FUNC(0) | PORTF(0, 3) | SE | PE) +#define GPMI_D03_LCD_D11 (FUNC(1) | PORTF(0, 3) | SE | PE) +#define GPMI_D03_SSP2_D3 (FUNC(2) | PORTF(0, 3) | SE | PE) +#define GPMI_D03_GPIO (FUNC(3) | PORTF(0, 3) | SE | PE) +#define GPMI_D02 (FUNC(0) | PORTF(0, 2) | SE | PE) +#define GPMI_D02_LCD_D10 (FUNC(1) | PORTF(0, 2) | SE | PE) +#define GPMI_D02_SSP2_D2 (FUNC(2) | PORTF(0, 2) | SE | PE) +#define GPMI_D02_GPIO (FUNC(3) | PORTF(0, 2) | SE | PE) +#define GPMI_D01 (FUNC(0) | PORTF(0, 1) | SE | PE) +#define GPMI_D01_LCD_D9 (FUNC(1) | PORTF(0, 1) | SE | PE) +#define GPMI_D01_SSP2_D1 (FUNC(2) | PORTF(0, 1) | SE | PE) +#define GPMI_D01_GPIO (FUNC(3) | PORTF(0, 1) | SE | PE) +#define GPMI_D00 (FUNC(0) | PORTF(0, 0) | SE | PE) +#define GPMI_D00_LCD_D8 (FUNC(1) | PORTF(0, 0) | SE | PE) +#define GPMI_D00_SSP2_D0 (FUNC(2) | PORTF(0, 0) | SE | PE) +#define GPMI_D00_GPIO (FUNC(3) | PORTF(0, 0) | SE | PE) + +/* Bank 0, pins 16 ... 31 GPIO pins 16 ... 31 */ +#define I2C_SDA (FUNC(0) | PORTF(1, 15) | SE) +#define I2C_SDA_GPMI_CE2N (FUNC(1) | PORTF(1, 15) | SE) +#define I2C_SDA_AUART1_RX (FUNC(2) | PORTF(1, 15) | SE) +#define I2C_SDA_GPIO (FUNC(3) | PORTF(1, 15) | SE) +#define I2C_CLK (FUNC(0) | PORTF(1, 14) | SE | PE) +#define I2C_CLK_GPMI_RDY2 (FUNC(1) | PORTF(1, 14) | SE | PE) +#define I2C_CLK_AUART1_TX (FUNC(2) | PORTF(1, 14) | SE | PE) +#define I2C_CLK_GPIO (FUNC(3) | PORTF(1, 14) | SE | PE) +#define AUART1_TX (FUNC(0) | PORTF(1, 13) | SE | PE) +#define AUART1_TX_SSP1_D7 (FUNC(2) | PORTF(1, 13) | SE | PE) +#define AUART1_TX_GPIO (FUNC(3) | PORTF(1, 13) | SE | PE) +#define AUART1_RX (FUNC(0) | PORTF(1, 12) | SE | PE) +#define AUART1_RX_SSP1_D6 (FUNC(2) | PORTF(1, 12) | SE | PE) +#define AUART1_RX_GPIO (FUNC(3) | PORTF(1, 12) | SE | PE) +#define AUART1_RTS (FUNC(0) | PORTF(1, 11) | SE | PE) +#define AUART1_RTS_SSP1_D5 (FUNC(2) | PORTF(1, 11) | SE | PE) +#define AUART1_RTS_GPIO (FUNC(3) | PORTF(1, 11) | SE | PE) +#define AUART1_CTS (FUNC(0) | PORTF(1, 10) | SE | PE) +#define AUART1_CTS_SSP1_D4 (FUNC(2) | PORTF(1, 10) | SE | PE) +#define AUART1_CTS_GPIO (FUNC(3) | PORTF(1, 10) | SE | PE) +#define GPMI_RDN (FUNC(0) | PORTF(1, 9) | SE) +#define GPMI_RDN_GPIO (FUNC(3) | PORTF(1, 9) | SE) +#define GPMI_WRN (FUNC(0) | PORTF(1, 8) | SE) +#define GPMI_WRN_SSP2_SCK (FUNC(2) | PORTF(1, 8) | SE) +#define GPMI_WRN_GPIO (FUNC(3) | PORTF(1, 8) | SE) +#define GPMI_WPM (FUNC(0) | PORTF(1, 7) | SE) +#define GPMI_WPM_GPIO (FUNC(3) | PORTF(1, 7) | SE) +#define GPMI_RDY3 (FUNC(0) | PORTF(1, 6) | SE | PE) +#define GPMI_RDY3_GPIO (FUNC(3) | PORTF(1, 6) | SE | PE) +#define GPMI_RDY2 (FUNC(0) | PORTF(1, 5) | SE | PE) +#define GPMI_RDY2_GPIO (FUNC(3) | PORTF(1, 5) | SE | PE) +#define GPMI_RDY1 (FUNC(0) | PORTF(1, 4) | SE | PE) +#define GPMI_RDY1_SSP2_CMD (FUNC(2) | PORTF(1, 4) | SE | PE) +#define GPMI_RDY1_GPIO (FUNC(3) | PORTF(1, 4) | SE | PE) +#define GPMI_RDY0 (FUNC(0) | PORTF(1, 3) | SE | PE) +#define GPMI_RDY0_SSP2_DETECT (FUNC(2) | PORTF(1, 3) | SE | PE) +#define GPMI_RDY0_GPIO (FUNC(3) | PORTF(1, 3) | SE | PE) +#define GPMI_CE2N (FUNC(0) | PORTF(1, 2) | SE | PE) +#define GPMI_CE2N_GPIO (FUNC(3) | PORTF(1, 2) | SE | PE) +#define GPMI_ALE (FUNC(0) | PORTF(1, 1) | SE) +#define GPMI_ALE_LCD_D17 (FUNC(1) | PORTF(1, 1) | SE) +#define GPMI_ALE_GPIO (FUNC(3) | PORTF(1, 1) | SE) +#define GPMI_CLE (FUNC(0) | PORTF(1, 0) | SE) +#define GPMI_CLE_LCD_D16 (FUNC(1) | PORTF(1, 1) | SE) +#define GPMI_CLE_GPIO (FUNC(3) | PORTF(1, 0) | SE) + +/* Bank 1, pins 0 ... 15 GPIO pins 32 ... 47 */ +#define LCD_D15 (FUNC(0) | PORTF(2, 15) | SE) +#define LCD_D15_ETM_DA7 (FUNC(1) | PORTF(2, 15) | SE) +#define LCD_D15_SAIF1_SDATA1 (FUNC(2) | PORTF(2, 15) | SE) +#define LCD_D15_GPIO (FUNC(3) | PORTF(2, 15) | SE) +#define LCD_D14 (FUNC(0) | PORTF(2, 14) | SE) +#define LCD_D14_ETM_DA6 (FUNC(1) | PORTF(2, 14) | SE) +#define LCD_D14_SAIF1_SDATA2 (FUNC(2) | PORTF(2, 14) | SE) +#define LCD_D14_GPIO (FUNC(3) | PORTF(2, 14) | SE) +#define LCD_D13 (FUNC(0) | PORTF(2, 13) | SE) +#define LCD_D13_ETM_DA5 (FUNC(1) | PORTF(2, 13) | SE) +#define LCD_D13_SAIF2_SDATA2 (FUNC(2) | PORTF(2, 13) | SE) +#define LCD_D13_GPIO (FUNC(3) | PORTF(2, 13) | SE) +#define LCD_D12 (FUNC(0) | PORTF(2, 12) | SE) +#define LCD_D12_ETM_DA4 (FUNC(1) | PORTF(2, 12) | SE) +#define LCD_D12_SAIF2_SDATA1 (FUNC(2) | PORTF(2, 12) | SE) +#define LCD_D12_GPIO (FUNC(3) | PORTF(2, 12) | SE) +#define LCD_D11 (FUNC(0) | PORTF(2, 11) | SE) +#define LCD_D11_ETM_DA3 (FUNC(1) | PORTF(2, 11) | SE) +#define LCD_D11_SAIF_LRCLK (FUNC(2) | PORTF(2, 11) | SE) +#define LCD_D11_GPIO (FUNC(3) | PORTF(2, 11) | SE) +#define LCD_D10 (FUNC(0) | PORTF(2, 10) | SE) +#define LCD_D10_ETM_DA2 (FUNC(1) | PORTF(2, 10) | SE) +#define LCD_D10_SAIF_BITCLK (FUNC(2) | PORTF(2, 10) | SE) +#define LCD_D10_GPIO (FUNC(3) | PORTF(2, 10) | SE) +#define LCD_D9 (FUNC(0) | PORTF(2, 9) | SE) +#define LCD_D9_ETM_DA1 (FUNC(1) | PORTF(2, 9) | SE) +#define LCD_D9_SAIF1_SDATA0 (FUNC(2) | PORTF(2, 9) | SE) +#define LCD_D9_GPIO (FUNC(3) | PORTF(2, 9) | SE) +#define LCD_D8 (FUNC(0) | PORTF(2, 8) | SE) +#define LCD_D8_ETM_DA0 (FUNC(1) | PORTF(2, 8) | SE) +#define LCD_D8_SAIF2_SDATA0 (FUNC(2) | PORTF(2, 8) | SE) +#define LCD_D8_GPIO (FUNC(3) | PORTF(2, 8) | SE) +#define LCD_D7 (FUNC(0) | PORTF(2, 7) | SE) +#define LCD_D7_ETM_DA15 (FUNC(1) | PORTF(2, 7) | SE) +#define LCD_D7_GPIO (FUNC(3) | PORTF(2, 7) | SE) +#define LCD_D6 (FUNC(0) | PORTF(2, 6) | SE) +#define LCD_D6_ETM_DA14 (FUNC(1) | PORTF(2, 6) | SE) +#define LCD_D6_GPIO (FUNC(3) | PORTF(2, 6) | SE) +#define LCD_D5 (FUNC(0) | PORTF(2, 5) | SE) +#define LCD_D5_ETM_DA13 (FUNC(1) | PORTF(2, 5) | SE) +#define LCD_D5_GPIO (FUNC(3) | PORTF(2, 5) | SE) +#define LCD_D4 (FUNC(0) | PORTF(2, 4) | SE) +#define LCD_D4_ETM_DA12 (FUNC(1) | PORTF(2, 4) | SE) +#define LCD_D4_GPIO (FUNC(3) | PORTF(2, 4) | SE) +#define LCD_D3 (FUNC(0) | PORTF(2, 3) | SE) +#define LCD_D3_ETM_DA11 (FUNC(1) | PORTF(2, 3) | SE) +#define LCD_D3_GPIO (FUNC(3) | PORTF(2, 3) | SE) +#define LCD_D2 (FUNC(0) | PORTF(2, 2) | SE) +#define LCD_D2_ETM_DA10 (FUNC(1) | PORTF(2, 2) | SE) +#define LCD_D2_GPIO (FUNC(3) | PORTF(2, 2) | SE) +#define LCD_D1 (FUNC(0) | PORTF(2, 1) | SE) +#define LCD_D1_ETM_DA9 (FUNC(1) | PORTF(2, 1) | SE) +#define LCD_D1_GPIO (FUNC(3) | PORTF(2, 1) | SE) +#define LCD_D0 (FUNC(0) | PORTF(2, 0) | SE) +#define LCD_D0_ETM_DA8 (FUNC(1) | PORTF(2, 0) | SE) +#define LCD_D0_GPIO (FUNC(3) | PORTF(2, 0) | SE) + +/* Bank 1, pins 16 ... 30 GPIO pins 48 ... 63 */ +#define PWM4 (FUNC(0) | PORTF(3, 14) | SE) +#define PWM4_ETM_CLK (FUNC(1) | PORTF(3, 14) | SE) +#define PWM4_AUART1_RTS (FUNC(2) | PORTF(3, 14) | SE) +#define PWM4_GPIO (FUNC(3) | PORTF(3, 14) | SE) +#define PWM3 (FUNC(0) | PORTF(3, 13) | SE) +#define PWM3_ETM_TCTL (FUNC(1) | PORTF(3, 13) | SE) +#define PWM3_AUART1_CTS (FUNC(2) | PORTF(3, 13) | SE) +#define PWM3_GPIO (FUNC(3) | PORTF(3, 13) | SE) +#define PWM2 (FUNC(0) | PORTF(3, 12) | SE | PE) +#define PWM2_GPMI_READY3 (FUNC(1) | PORTF(3, 12) | SE | PE) +#define PWM2_GPIO (FUNC(3) | PORTF(3, 12) | SE | PE) +#define PWM1 (FUNC(0) | PORTF(3, 11) | SE) +#define PWM1_TIMROT2 (FUNC(1) | PORTF(3, 11) | SE) +#define PWM1_DUART_TX (FUNC(2) | PORTF(3, 11) | SE) +#define PWM1_GPIO (FUNC(3) | PORTF(3, 11) | SE) +#define PWM0 (FUNC(0) | PORTF(3, 10) | SE) +#define PWM0_TIMROT1 (FUNC(1) | PORTF(3, 10) | SE) +#define PWM0_DUART_RX (FUNC(2) | PORTF(3, 10) | SE) +#define PWM0_GPIO (FUNC(3) | PORTF(3, 10) | SE) +#define LCD_VSYNC (FUNC(0) | PORTF(3, 9) | SE) +#define LCD_VSYNC_LCD_BUSY (FUNC(1) | PORTF(3, 9) | SE) +#define LCD_VSYNC_GPIO (FUNC(3) | PORTF(3, 9) | SE) +#define LCD_HSYNC (FUNC(0) | PORTF(3, 8) | SE) +#define LCD_HSYNC_I2C_SD (FUNC(1) | PORTF(3, 8) | SE) +#define LCD_HSYNC_GPIO (FUNC(3) | PORTF(3, 8) | SE) +#define LCD_ENABE (FUNC(0) | PORTF(3, 7) | SE) +#define LCD_ENABE_I2C_CLK (FUNC(1) | PORTF(3, 7) | SE) +#define LCD_ENABE_GPIO (FUNC(3) | PORTF(3, 7) | SE) +#define LCD_DOTCLOCK (FUNC(0) | PORTF(3, 6) | SE | PE) +#define LCD_DOTCLOCK_GPMI_READY3 (FUNC(1) | PORTF(3, 6) | SE | PE) +#define LCD_DOTCLOCK_GPIO (FUNC(3) | PORTF(3, 6) | SE | PE) +#define LCD_CS (FUNC(0) | PORTF(3, 5) | SE) +#define LCD_CS_GPIO (FUNC(3) | PORTF(3, 5) | SE) +#define LCD_WR (FUNC(0) | PORTF(3, 4) | SE) +#define LCD_WR_GPIO (FUNC(3) | PORTF(3, 4) | SE) +#define LCD_RS (FUNC(0) | PORTF(3, 3) | SE) +#define LCD_RS_ETM_TCLK (FUNC(1) | PORTF(3, 3) | SE) +#define LCD_RS_GPIO (FUNC(3) | PORTF(3, 3) | SE) +#define LCD_RESET (FUNC(0) | PORTF(3, 2) | SE | PE) +#define LCD_RESET_ETM_TCTL (FUNC(1) | PORTF(3, 2) | SE | PE) +#define LCD_RESET_GPMI_CE3N (FUNC(2) | PORTF(3, 2) | SE | PE) +#define LCD_RESET_GPIO (FUNC(3) | PORTF(3, 2) | SE | PE) +#define LCD_D17 (FUNC(0) | PORTF(3, 1) | SE) +#define LCD_D17_GPIO (FUNC(3) | PORTF(3, 1) | SE) +#define LCD_D16 (FUNC(0) | PORTF(3, 0) | SE) +#define LCD_D16_SAIF_ALT_BITCLK (FUNC(2) | PORTF(3, 0) | SE) +#define LCD_D16_GPIO (FUNC(3) | PORTF(3, 0) | SE) + +/* Bank 2, pins 0 ... 15 GPIO pins 64 ... 79 */ +#define EMI_A6 (FUNC(0) | PORTF(4, 15) | SE | VE) +#define EMI_A6_GPIO (FUNC(3) | PORTF(4, 15) | SE | VE) +#define EMI_A5 (FUNC(0) | PORTF(4, 14) | SE | VE) +#define EMI_A5_GPIO (FUNC(3) | PORTF(4, 14) | SE | VE) +#define EMI_A4 (FUNC(0) | PORTF(4, 13) | SE | VE) +#define EMI_A4_GPIO (FUNC(3) | PORTF(4, 13) | SE | VE) +#define EMI_A3 (FUNC(0) | PORTF(4, 12) | SE | VE) +#define EMI_A3_GPIO (FUNC(3) | PORTF(4, 12) | SE | VE) +#define EMI_A2 (FUNC(0) | PORTF(4, 11) | SE | VE) +#define EMI_A2_GPIO (FUNC(3) | PORTF(4, 11) | SE | VE) +#define EMI_A1 (FUNC(0) | PORTF(4, 10) | SE | VE) +#define EMI_A1_GPIO (FUNC(3) | PORTF(4, 10) | SE | VE) +#define EMI_A0 (FUNC(0) | PORTF(4, 9) | SE | VE) +#define EMI_A0_GPIO (FUNC(3) | PORTF(4, 9) | SE | VE) +#define ROTARYB (FUNC(0) | PORTF(4, 8) | SE | PE) +#define ROTARYB_AUART2_CTS (FUNC(1) | PORTF(4, 8) | SE | PE) +#define ROTARYB_GPMI_CE3N (FUNC(2) | PORTF(4, 8) | SE | PE) +#define ROTARYB_GPIO (FUNC(3) | PORTF(4, 8) | SE | PE) +#define ROTARYA (FUNC(0) | PORTF(4, 7) | SE) +#define ROTARYA_AUART2_RTS (FUNC(1) | PORTF(4, 7) | SE) +#define ROTARYA_SPDIF (FUNC(2) | PORTF(4, 7) | SE) +#define ROTARYA_GPIO (FUNC(3) | PORTF(4, 7) | SE) +#define SSP1_SCK (FUNC(0) | PORTF(4, 6) | SE) +#define SSP1_SCK_ALT_JTAG_TRST (FUNC(2) | PORTF(4, 6) | SE) +#define SSP1_SCK_GPIO (FUNC(3) | PORTF(4, 6) | SE) +#define SSP1_DATA3 (FUNC(0) | PORTF(4, 5) | SE | PE) +#define SSP1_DATA3_ALT_JTAG_TMS (FUNC(2) | PORTF(4, 5) | SE | PE) +#define SSP1_DATA3_GPIO (FUNC(3) | PORTF(4, 5) | SE | PE) +#define SSP1_DATA2 (FUNC(0) | PORTF(4, 4) | SE | PE) +#define SSP1_DATA2_I2C_SD (FUNC(1) | PORTF(4, 4) | SE | PE) +#define SSP1_DATA2_ALT_JTAG_RTCK (FUNC(2) | PORTF(4, 4) | SE | PE) +#define SSP1_DATA2_GPIO (FUNC(3) | PORTF(4, 4) | SE | PE) +#define SSP1_DATA1 (FUNC(0) | PORTF(4, 3) | SE | PE) +#define SSP1_DATA1_I2C_CLK (FUNC(1) | PORTF(4, 3) | SE | PE) +#define SSP1_DATA1_ALT_JTAG_TCK (FUNC(2) | PORTF(4, 3) | SE | PE) +#define SSP1_DATA1_GPIO (FUNC(3) | PORTF(4, 3) | SE | PE) +#define SSP1_DATA0 (FUNC(0) | PORTF(4, 2) | SE | PE) +#define SSP1_DATA0_ALT_JTAG_TDI (FUNC(2) | PORTF(4, 2) | SE | PE) +#define SSP1_DATA0_GPIO (FUNC(3) | PORTF(4, 2) | SE | PE) +#define SSP1_DETECT (FUNC(0) | PORTF(4, 1) | SE | PE) +#define SSP1_DETECT_GPMI_CE3N (FUNC(1) | PORTF(4, 1) | SE | PE) +#define SSP1_DETECT_USB_ID (FUNC(2) | PORTF(4, 1) | SE | PE) +#define SSP1_DETECT_GPIO (FUNC(3) | PORTF(4, 1) | SE | PE) +#define SSP1_CMD (FUNC(0) | PORTF(4, 0) | SE | PE) +#define SSP1_CMD_JTAG_TDO (FUNC(2) | PORTF(4, 0) | SE | PE) +#define SSP1_CMD_GPIO (FUNC(3) | PORTF(4, 0) | SE | PE) + +/* Bank 2, pins 16 ... 31 GPIO pins 80 ... 95 */ +#define EMI_WEN (FUNC(0) | PORTF(5, 15) | SE | VE) +#define EMI_WEN_GPIO (FUNC(3) | PORTF(5, 15) | SE | VE) +#define EMI_RASN (FUNC(0) | PORTF(5, 14) | SE | VE) +#define EMI_RASN_GPIO (FUNC(3) | PORTF(5, 14) | SE | VE) +#define EMI_CKE (FUNC(0) | PORTF(5, 13) | SE | VE) +#define EMI_CKE_GPIO (FUNC(3) | PORTF(5, 13) | SE | VE) +#define GPMI_CE0N (FUNC(0) | PORTF(5, 12) | SE) +#define GPMI_CE0N_GPIO (FUNC(3) | PORTF(5, 12) | SE) +#define GPMI_CE1N (FUNC(0) | PORTF(5, 11) | SE | PE) +#define GPMI_CE1N_GPIO (FUNC(3) | PORTF(5, 11) | SE | PE) +#define EMI_CE1N (FUNC(0) | PORTF(5, 10) | SE | VE | PE) +#define EMI_CE1N_GPIO (FUNC(3) | PORTF(5, 10) | SE | VE | PE) +#define EMI_CE0N (FUNC(0) | PORTF(5, 9) | SE | VE) +#define EMI_CE0N_GPIO (FUNC(3) | PORTF(5, 9) | SE | VE) +#define EMI_CASN (FUNC(0) | PORTF(5, 8) | SE | VE) +#define EMI_CASN_GPIO (FUNC(3) | PORTF(5, 8) | SE | VE) +#define EMI_BA1 (FUNC(0) | PORTF(5, 7) | SE | VE) +#define EMI_BA1_GPIO (FUNC(3) | PORTF(5, 7) | SE | VE) +#define EMI_BA0 (FUNC(0) | PORTF(5, 6) | SE | VE) +#define EMI_BA0_GPIO (FUNC(3) | PORTF(5, 6) | SE | VE) +#define EMI_A12 (FUNC(0) | PORTF(5, 5) | SE | VE) +#define EMI_A12_GPIO (FUNC(3) | PORTF(5, 5) | SE | VE) +#define EMI_A11 (FUNC(0) | PORTF(5, 4) | SE | VE) +#define EMI_A11_GPIO (FUNC(3) | PORTF(5, 4) | SE | VE) +#define EMI_A10 (FUNC(0) | PORTF(5, 3) | SE | VE) +#define EMI_A10_GPIO (FUNC(3) | PORTF(5, 3) | SE | VE) +#define EMI_A9 (FUNC(0) | PORTF(5, 2) | SE | VE) +#define EMI_A9_GPIO (FUNC(3) | PORTF(5, 2) | SE | VE) +#define EMI_A8 (FUNC(0) | PORTF(5, 1) | SE | VE) +#define EMI_A8_GPIO (FUNC(3) | PORTF(5, 1) | SE | VE) +#define EMI_A7 (FUNC(0) | PORTF(5, 0) | SE | VE) +#define EMI_A7_GPIO (FUNC(3) | PORTF(5, 0) | SE | VE) + +/* Bank 3, pins 0 ... 15 GPIO pins 96 ... 111 */ +#define EMI_D15 (FUNC(0) | PORTF(6, 15) | SE | VE | PE) +#define EMI_D15_DISABLED (FUNC(3) | PORTF(6, 15) | SE | VE | PE) +#define EMI_D14 (FUNC(0) | PORTF(6, 14) | SE | VE | PE) +#define EMI_D14_DISABLED (FUNC(3) | PORTF(6, 14) | SE | VE | PE) +#define EMI_D13 (FUNC(0) | PORTF(6, 13) | SE | VE | PE) +#define EMI_D13_DISABLED (FUNC(3) | PORTF(6, 13) | SE | VE | PE) +#define EMI_D12 (FUNC(0) | PORTF(6, 12) | SE | VE | PE) +#define EMI_D12_DISABLED (FUNC(3) | PORTF(6, 12) | SE | VE | PE) +#define EMI_D11 (FUNC(0) | PORTF(6, 11) | SE | VE | PE) +#define EMI_D11_DISABLED (FUNC(3) | PORTF(6, 11) | SE | VE | PE) +#define EMI_D10 (FUNC(0) | PORTF(6, 10) | SE | VE | PE) +#define EMI_D10_DISABLED (FUNC(3) | PORTF(6, 10) | SE | VE | PE) +#define EMI_D9 (FUNC(0) | PORTF(6, 9) | SE | VE | PE) +#define EMI_D9_DISABLED (FUNC(3) | PORTF(6, 9) | SE | VE | PE) +#define EMI_D8 (FUNC(0) | PORTF(6, 8) | SE | VE | PE) +#define EMI_D8_DISABLED (FUNC(3) | PORTF(6, 8) | SE | VE | PE) +#define EMI_D7 (FUNC(0) | PORTF(6, 7) | SE | VE | PE) +#define EMI_D7_DISABLED (FUNC(3) | PORTF(6, 7) | SE | VE | PE) +#define EMI_D6 (FUNC(0) | PORTF(6, 6) | SE | VE | PE) +#define EMI_D6_DISABLED (FUNC(3) | PORTF(6, 6) | SE | VE | PE) +#define EMI_D5 (FUNC(0) | PORTF(6, 5) | SE | VE | PE) +#define EMI_D5_DISABLED (FUNC(3) | PORTF(6, 5) | SE | VE | PE) +#define EMI_D4 (FUNC(0) | PORTF(6, 4) | SE | VE | PE) +#define EMI_D4_DISABLED (FUNC(3) | PORTF(6, 4) | SE | VE | PE) +#define EMI_D3 (FUNC(0) | PORTF(6, 3) | SE | VE | PE) +#define EMI_D3_DISABLED (FUNC(3) | PORTF(6, 3) | SE | VE | PE) +#define EMI_D2 (FUNC(0) | PORTF(6, 2) | SE | VE | PE) +#define EMI_D2_DISABLED (FUNC(3) | PORTF(6, 2) | SE | VE | PE) +#define EMI_D1 (FUNC(0) | PORTF(6, 1) | SE | VE | PE) +#define EMI_D1_DISABLED (FUNC(3) | PORTF(6, 1) | SE | VE | PE) +#define EMI_D0 (FUNC(0) | PORTF(6, 0) | SE | VE | PE) +#define EMI_D0_DISABLED (FUNC(3) | PORTF(6, 0) | SE | VE | PE) + +/* Bank 3, pins 16 ... 21 GPIO pins 112 ... 117 */ +#define EMI_CLKN (FUNC(0) | PORTF(7, 5) | SE | VE) +#define EMI_CLKN_DISABLED (FUNC(3) | PORTF(7, 5) | SE | VE) +#define EMI_CLK (FUNC(0) | PORTF(7, 4) | SE | VE) +#define EMI_CLK_DISABLED (FUNC(3) | PORTF(7, 4) | SE | VE) +#define EMI_DQS1 (FUNC(0) | PORTF(7, 3) | SE | VE) +#define EMI_DQS1_DISABLED (FUNC(3) | PORTF(7, 3) | SE | VE) +#define EMI_DQS0 (FUNC(0) | PORTF(7, 2) | SE | VE) +#define EMI_DQS0_DISABLED (FUNC(3) | PORTF(7, 2) | SE | VE) +#define EMI_DQM1 (FUNC(0) | PORTF(7, 1) | SE | VE | PE) +#define EMI_DQM1_DISABLED (FUNC(3) | PORTF(7, 1) | SE | VE | PE) +#define EMI_DQM0 (FUNC(0) | PORTF(7, 0) | SE | VE | PE) +#define EMI_DQM0_DISABLED (FUNC(3) | PORTF(7, 0) | SE | VE | PE) + +#endif /* __ASM_MACH_IOMUX_H */ diff --git a/arch/arm/mach-mxs/include/mach/iomux-imx28.h b/arch/arm/mach-mxs/include/mach/iomux-imx28.h new file mode 100644 index 0000000000..1e6d421c22 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/iomux-imx28.h @@ -0,0 +1,552 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* 3322222222221111111111 + * 10987654321098765432109876543210 + * ^^^^^_ Bit offset + * ^^^______ Register Number + * ^^_________ Function + * ^___________ Drive strength feature present + * ^____________ Pull up / bit keeper present + * ^^_____________ Drive strength setting + * ^_______________ Pull up / bit keeper setting + * ^________________ Voltage select present + * ^_________________ Voltage selection + * ^_____________________ direction if enabled as GPIO (1 = output) + * ^______________________ initial output value if enabled as GPIO + * and configured as output + */ +#ifndef __MACH_IOMUX_IMX28_H +#define __MACH_IOMUX_IMX28_H + +/* control pad's function */ +#define FBANK_SHIFT (5) +#define PORTF(bank,bit) (((bank) << FBANK_SHIFT) | (bit)) +#define GET_GPIO_NO(x) ((x) & 0xff) +#define FUNC_SHIFT 8 +#define FUNC(x) ((x) << FUNC_SHIFT) +#define GET_FUNC(x) (((x) >> FUNC_SHIFT) & 3) +#define IS_GPIO (3) + +/* control pad's GPIO feature if enabled */ +#define GPIO_OUT (1 << 20) +#define GPIO_VALUE(x) ((x) << 21) +#define GPIO_IN (0 << 20) +#define GET_GPIODIR(x) (!!((x) & (1 << 20))) +#define GET_GPIOVAL(x) (!!((x) & (1 << 21))) + +/* control pad's drive strength */ +#define SE (1 << 10) +#define SE_PRESENT(x) (!!((x) & SE)) +#define STRENGTH(x) ((x) << 12) +#define S4MA 0 /* used to define a 4 mA drive strength */ +#define S8MA 1 /* used to define a 8 mA drive strength */ +#define S12MA 2 /* used to define a 12 mA drive strength */ +#define S16MA 3 /* used to define a 16 mA drive strength, + not all pads can drive this current! */ +#define GET_STRENGTH(x) (((x) >> 12) & 0x3) + +/* control pad's pull up / bit keeper feature */ +#define PE (1 << 11) +#define BK (1 << 11) /* FIXME useful to distinguish? */ +#define PE_PRESENT(x) (!!((x) & PE)) +#define BK_PRESENT(x) (!!((x) & BK)) +#define PULLUP(x) ((x) << 14) +#define BITKEEPER(x) ((x) << 14) +#define GET_PULLUP(x) (!!((x) & PULLUP(1))) +#define GET_BITKEEPER(x) (!!((x) & BITKEEPER(1))) + +/* control pad's voltage feature */ +#define VE (1 << 15) +#define VE_PRESENT(x) (!!((x) & VE)) +#define VE_1_8V (0 << 16) +#define VE_3_3V (1 << 16) +#define GET_VOLTAGE(x) (!!((x) & (1 << 16))) + +/* Bank 0, GPIO pins 0 ... 31 */ +#define GPMI_RESETN (FUNC(0) | PORTF(0, 28) | SE | VE | PE) +#define GPMI_RESETN_SSP3_CMD (FUNC(1) | PORTF(0, 28) | SE | VE | PE) +#define GPMI_RESETN_GPIO (FUNC(3) | PORTF(0, 28) | SE | VE | PE) +#define GPMI_CLE (FUNC(0) | PORTF(0, 27) | SE | VE | PE) +#define GPMI_CLE_SSP3_D2 (FUNC(1) | PORTF(0, 27) | SE | VE | PE) +#define GPMI_CLE_SSP3_D5 (FUNC(2) | PORTF(0, 27) | SE | VE | PE) +#define GPMI_CLE_GPIO (FUNC(3) | PORTF(0, 27) | SE | VE | PE) +#define GPMI_ALE (FUNC(0) | PORTF(0, 26) | SE | VE | PE) +#define GPMI_ALE_SSP3_D1 (FUNC(1) | PORTF(0, 26) | SE | VE | PE) +#define GPMI_ALE_SSP3_D4 (FUNC(2) | PORTF(0, 26) | SE | VE | PE) +#define GPMI_ALE_GPIO (FUNC(3) | PORTF(0, 26) | SE | VE | PE) +#define GPMI_WRN (FUNC(0) | PORTF(0, 25) | SE | VE | BK) +#define GPMI_WRN_SSP1_SCK (FUNC(1) | PORTF(0, 25) | SE | VE | BK) +#define GPMI_WRN_GPIO (FUNC(3) | PORTF(0, 25) | SE | VE | BK) +#define GPMI_RDN (FUNC(0) | PORTF(0, 24) | SE | VE | PE) +#define GPMI_RDN_SSP3_SCK (FUNC(1) | PORTF(0, 24) | SE | VE | PE) +#define GPMI_RDN_GPIO (FUNC(3) | PORTF(0, 24) | SE | VE | PE) +#define GPMI_READY3 (FUNC(0) | PORTF(0, 23) | SE | VE | PE) +#define GPMI_READY3_CAN0_RX (FUNC(1) | PORTF(0, 23) | SE | VE | PE) +#define GPMI_READY3_HSDAC_TRIG (FUNC(2) | PORTF(0, 23) | SE | VE | PE) +#define GPMI_READY3_GPIO (FUNC(3) | PORTF(0, 23) | SE | VE | PE) +#define GPMI_READY2 (FUNC(0) | PORTF(0, 22) | SE | VE | PE) +#define GPMI_READY2_CAN0_TX (FUNC(1) | PORTF(0, 22) | SE | VE | PE) +#define GPMI_READY2_ENET0_TX_ER (FUNC(2) | PORTF(0, 22) | SE | VE | PE) +#define GPMI_READY2_GPIO (FUNC(3) | PORTF(0, 22) | SE | VE | PE) +#define GPMI_READY1 (FUNC(0) | PORTF(0, 21) | SE | VE | PE) +#define GPMI_READY1_SSP1_CMD (FUNC(1) | PORTF(0, 21) | SE | VE | PE) +#define GPMI_READY1_GPIO (FUNC(3) | PORTF(0, 21) | SE | VE | PE) +#define GPMI_READY0 (FUNC(0) | PORTF(0, 20) | SE | VE | PE) +#define GPMI_READY0_SSP1_CD (FUNC(1) | PORTF(0, 20) | SE | VE | PE) +#define GPMI_READY0_USB0_ID (FUNC(2) | PORTF(0, 20) | SE | VE | PE) +#define GPMI_READY0_GPIO (FUNC(3) | PORTF(0, 20) | SE | VE | PE) +#define GPMI_CE3N (FUNC(0) | PORTF(0, 19) | SE | VE | PE) +#define GPMI_CE3N_CAN1_RX (FUNC(1) | PORTF(0, 19) | SE | VE | PE) +#define GPMI_CE3N_SAIF1_MCLK (FUNC(2) | PORTF(0, 19) | SE | VE | PE) +#define GPMI_CE3N_GPIO (FUNC(3) | PORTF(0, 19) | SE | VE | PE) +#define GPMI_CE2N (FUNC(0) | PORTF(0, 18) | SE | VE | PE) +#define GPMI_CE2N_CAN1_TX (FUNC(1) | PORTF(0, 18) | SE | VE | PE) +#define GPMI_CE2N_ENET0_RX_ER (FUNC(2) | PORTF(0, 18) | SE | VE | PE) +#define GPMI_CE2N_GPIO (FUNC(3) | PORTF(0, 18) | SE | VE | PE) +#define GPMI_CE1N (FUNC(0) | PORTF(0, 17) | SE | VE | PE) +#define GPMI_CE1N_SSP3_D3 (FUNC(1) | PORTF(0, 17) | SE | VE | PE) +#define GPMI_CE1N_GPIO (FUNC(3) | PORTF(0, 17) | SE | VE | PE) +#define GPMI_CE0N (FUNC(0) | PORTF(0, 16) | SE | VE | PE) +#define GPMI_CE0N_SSP3_D0 (FUNC(1) | PORTF(0, 16) | SE | VE | PE) +#define GPMI_CE0N_GPIO (FUNC(3) | PORTF(0, 16) | SE | VE | PE) +#define GPMI_D7 (FUNC(0) | PORTF(0, 7) | SE | VE | PE) +#define GPMI_D7_SSP1_D7 (FUNC(1) | PORTF(0, 7) | SE | VE | PE) +#define GPMI_D7_GPIO (FUNC(3) | PORTF(0, 7) | SE | VE | PE) +#define GPMI_D6 (FUNC(0) | PORTF(0, 6) | SE | VE | PE) +#define GPMI_D6_SSP1_D6 (FUNC(1) | PORTF(0, 6) | SE | VE | PE) +#define GPMI_D6_GPIO (FUNC(3) | PORTF(0, 6) | SE | VE | PE) +#define GPMI_D5 (FUNC(0) | PORTF(0, 5) | SE | VE | PE) +#define GPMI_D5_SSP1_D5 (FUNC(1) | PORTF(0, 5) | SE | VE | PE) +#define GPMI_D5_GPIO (FUNC(3) | PORTF(0, 5) | SE | VE | PE) +#define GPMI_D4 (FUNC(0) | PORTF(0, 4) | SE | VE | PE) +#define GPMI_D4_SSP1_D4 (FUNC(1) | PORTF(0, 4) | SE | VE | PE) +#define GPMI_D4_GPIO (FUNC(3) | PORTF(0, 4) | SE | VE | PE) +#define GPMI_D3 (FUNC(0) | PORTF(0, 3) | SE | VE | PE) +#define GPMI_D3_SSP1_D3 (FUNC(1) | PORTF(0, 3) | SE | VE | PE) +#define GPMI_D3_GPIO (FUNC(3) | PORTF(0, 3) | SE | VE | PE) +#define GPMI_D2 (FUNC(0) | PORTF(0, 2) | SE | VE | PE) +#define GPMI_D2_SSP1_D2 (FUNC(1) | PORTF(0, 2) | SE | VE | PE) +#define GPMI_D2_GPIO (FUNC(3) | PORTF(0, 2) | SE | VE | PE) +#define GPMI_D1 (FUNC(0) | PORTF(0, 1) | SE | VE | PE) +#define GPMI_D1_SSP1_D1 (FUNC(1) | PORTF(0, 1) | SE | VE | PE) +#define GPMI_D1_GPIO (FUNC(3) | PORTF(0, 1) | SE | VE | PE) +#define GPMI_D0 (FUNC(0) | PORTF(0, 0) | SE | VE | PE) +#define GPMI_D0_SSP1_D0 (FUNC(1) | PORTF(0, 0) | SE | VE | PE) +#define GPMI_D0_GPIO (FUNC(3) | PORTF(0, 0) | SE | VE | PE) + +/* Bank 1, GPIO pins 32 ... 63 */ + +#define LCD_ENABLE (FUNC(0) | PORTF(1, 31) | SE | VE | BK) +#define LCD_ENABLE_GPIO (FUNC(3) | PORTF(1, 31) | SE | VE | BK) + +#define LCD_DOTCLK (FUNC(0) | PORTF(1, 30) | SE | VE | BK) + +#define LCD_HSYNC (FUNC(0) | PORTF(1, 29) | SE | VE | BK) + +#define LCD_VSYNC (FUNC(0) | PORTF(1, 28) | SE | VE | BK) + +#define LCD_CS (FUNC(0) | PORTF(1, 27) | SE | VE | BK) +#define LCD_CS_LCD_ENABLE (FUNC(1) | PORTF(1, 27) | SE | VE | BK) +#define LCD_CS_GPIO (FUNC(3) | PORTF(1, 27) | SE | VE | BK) + +#define LCD_RS (FUNC(0) | PORTF(1, 26) | SE | VE | BK) +#define LCD_RS_LCD_DOTCLK (FUNC(1) | PORTF(1, 26) | SE | VE | BK) +#define LCD_RS_GPIO (FUNC(3) | PORTF(1, 26) | SE | VE | BK) +#define LCD_WR_RWN (FUNC(0) | PORTF(1, 25) | SE | VE | BK) +#define LCD_WR_RWN_LCD_HSYNC (FUNC(1) | PORTF(1, 25) | SE | VE | BK) +#define LCD_WR_RWN_ETM_TCLK (FUNC(2) | PORTF(1, 25) | SE | VE | BK) +#define LCD_WR_RWN_GPIO (FUNC(3) | PORTF(1, 25) | SE | VE | BK) +#define LCD_RD_E (FUNC(0) | PORTF(1, 24) | SE | VE | BK) +#define LCD_RD_E_LCD_VSYNC (FUNC(1) | PORTF(1, 24) | SE | VE | BK) +#define LCD_RD_E_ETM_TCTL (FUNC(2) | PORTF(1, 24) | SE | VE | BK) +#define LCD_RD_E_GPIO (FUNC(3) | PORTF(1, 24) | SE | VE | BK) + +#define LCD_D23 (FUNC(0) | PORTF(1, 23) | SE | VE | BK) + +#define LCD_D22 (FUNC(0) | PORTF(1, 22) | SE | VE | BK) + +#define LCD_D21 (FUNC(0) | PORTF(1, 21) | SE | VE | BK) + +#define LCD_D20 (FUNC(0) | PORTF(1, 20) | SE | VE | BK) + +#define LCD_D19 (FUNC(0) | PORTF(1, 19) | SE | VE | BK) + +#define LCD_D18 (FUNC(0) | PORTF(1, 18) | SE | VE | BK) + +#define LCD_D17 (FUNC(0) | PORTF(1, 17) | SE | VE | BK) + +#define LCD_D16 (FUNC(0) | PORTF(1, 16) | SE | VE | BK) + +#define LCD_D15 (FUNC(0) | PORTF(1, 15) | SE | VE | BK) +#define LCD_D15_ETM_DA15 (FUNC(2) | PORTF(1, 15) | SE | VE | BK) +#define LCD_D15_GPIO (FUNC(3) | PORTF(1, 15) | SE | VE | BK) +#define LCD_D14 (FUNC(0) | PORTF(1, 14) | SE | VE | BK) +#define LCD_D14_ETM_DA14 (FUNC(2) | PORTF(1, 14) | SE | VE | BK) +#define LCD_D14_GPIO (FUNC(3) | PORTF(1, 14) | SE | VE | BK) +#define LCD_D13 (FUNC(0) | PORTF(1, 13) | SE | VE | BK) +#define LCD_D13_ETM_DA13 (FUNC(2) | PORTF(1, 13) | SE | VE | BK) +#define LCD_D13_GPIO (FUNC(3) | PORTF(1, 13) | SE | VE | BK) +#define LCD_D12 (FUNC(0) | PORTF(1, 12) | SE | VE | BK) +#define LCD_D12_ETM_DA12 (FUNC(2) | PORTF(1, 12) | SE | VE | BK) +#define LCD_D12_GPIO (FUNC(3) | PORTF(1, 12) | SE | VE | BK) +#define LCD_D11 (FUNC(0) | PORTF(1, 11) | SE | VE | BK) +#define LCD_D11_ETM_DA11 (FUNC(2) | PORTF(1, 11) | SE | VE | BK) +#define LCD_D11_GPIO (FUNC(3) | PORTF(1, 11) | SE | VE | BK) +#define LCD_D10 (FUNC(0) | PORTF(1, 10) | SE | VE | BK) +#define LCD_D10_ETM_DA10 (FUNC(2) | PORTF(1, 10) | SE | VE | BK) +#define LCD_D10_GPIO (FUNC(3) | PORTF(1, 10) | SE | VE | BK) +#define LCD_D9 (FUNC(0) | PORTF(1, 9) | SE | VE | BK) +#define LCD_D9_ETM_DA4 (FUNC(1) | PORTF(1, 9) | SE | VE | BK) +#define LCD_D9_ETM_DA9 (FUNC(2) | PORTF(1, 9) | SE | VE | BK) +#define LCD_D9_GPIO (FUNC(3) | PORTF(1, 9) | SE | VE | BK) +#define LCD_D8 (FUNC(0) | PORTF(1, 8) | SE | VE | BK) +#define LCD_D8_ETM_DA3 (FUNC(1) | PORTF(1, 8) | SE | VE | BK) +#define LCD_D8_ETM_DA8 (FUNC(2) | PORTF(1, 8) | SE | VE | BK) +#define LCD_D8_GPIO (FUNC(3) | PORTF(1, 8) | SE | VE | BK) +#define LCD_D7 (FUNC(0) | PORTF(1, 7) | SE | VE | BK) +#define LCD_D7_ETM_DA7 (FUNC(2) | PORTF(1, 7) | SE | VE | BK) +#define LCD_D7_GPIO (FUNC(3) | PORTF(1, 7) | SE | VE | BK) +#define LCD_D6 (FUNC(0) | PORTF(1, 6) | SE | VE | BK) +#define LCD_D6_ETM_DA6 (FUNC(2) | PORTF(1, 6) | SE | VE | BK) +#define LCD_D6_GPIO (FUNC(3) | PORTF(1, 6) | SE | VE | BK) +#define LCD_D5 (FUNC(0) | PORTF(1, 5) | SE | VE | BK) +#define LCD_D5_ETM_DA5 (FUNC(2) | PORTF(1, 5) | SE | VE | BK) +#define LCD_D5_GPIO (FUNC(3) | PORTF(1, 5) | SE | VE | BK) +#define LCD_D4 (FUNC(0) | PORTF(1, 4) | SE | VE | BK) +#define LCD_D4_ETM_DA9 (FUNC(1) | PORTF(1, 4) | SE | VE | BK) +#define LCD_D4_ETM_DA4 (FUNC(2) | PORTF(1, 4) | SE | VE | BK) +#define LCD_D4_GPIO (FUNC(3) | PORTF(1, 4) | SE | VE | BK) +#define LCD_D3 (FUNC(0) | PORTF(1, 3) | SE | VE | BK) +#define LCD_D3_ETM_DA8 (FUNC(1) | PORTF(1, 3) | SE | VE | BK) +#define LCD_D3_ETM_DA3 (FUNC(2) | PORTF(1, 3) | SE | VE | BK) +#define LCD_D3_GPIO (FUNC(3) | PORTF(1, 3) | SE | VE | BK) +#define LCD_D2 (FUNC(0) | PORTF(1, 2) | SE | VE | BK) +#define LCD_D2_ETM_DA2 (FUNC(2) | PORTF(1, 2) | SE | VE | BK) +#define LCD_D2_GPIO (FUNC(3) | PORTF(1, 2) | SE | VE | BK) +#define LCD_D1 (FUNC(0) | PORTF(1, 1) | SE | VE | BK) +#define LCD_D1_ETM_DA1 (FUNC(2) | PORTF(1, 1) | SE | VE | BK) +#define LCD_D1_GPIO (FUNC(3) | PORTF(1, 1) | SE | VE | BK) +#define LCD_D0 (FUNC(0) | PORTF(1, 0) | SE | VE | BK) +#define LCD_D0_ETM_DA0 (FUNC(2) | PORTF(1, 0) | SE | VE | BK) +#define LCD_D0_GPIO (FUNC(3) | PORTF(1, 0) | SE | VE | BK) + +/* TODO */ + +/* Bank 2, GPIO pins 64 ... 95 */ + +/* TODO */ + +#define SSP1_D3 (FUNC(0) | PORTF(2, 15) | SE | VE | PE) +#define SSP1_D3_SSP2_D7 (FUNC(1) | PORTF(2, 15) | SE | VE | PE) +#define SSP1_D3_ENET_1588_EVENT3_IN (FUNC(2) | PORTF(4, 15) | SE | VE | PE) +#define SSP1_D3_GPIO (FUNC(3) | PORTF(2, 15) | SE | VE | PE) +#define SSP1_D0 (FUNC(0) | PORTF(2, 14) | SE | VE | PE) +#define SSP1_D0_SSP2_D6 (FUNC(1) | PORTF(2, 14) | SE | VE | PE) +#define SSP1_D0_ENET_1588_EVENT3_OUT (FUNC(2) | PORTF(2, 14) | SE | VE | PE) +#define SSP1_D0_GPIO (FUNC(3) | PORTF(2, 14) | SE | VE | PE) +#define SSP1_CMD (FUNC(0) | PORTF(2, 13) | SE | VE | PE) +#define SSP1_CMD_SSP2_D2 (FUNC(1) | PORTF(2, 13) | SE | VE | PE) +#define SSP1_CMD_ENET_1588_EVENT2_IN (FUNC(2) | PORTF(2, 13) | SE | VE | PE) +#define SSP1_CMD_GPIO (FUNC(3) | PORTF(2, 13) | SE | VE | PE) +#define SSP1_SCK (FUNC(0) | PORTF(2, 12) | SE | VE | PE) +#define SSP1_SCK_SSP2_D1 (FUNC(1) | PORTF(2, 12) | SE | VE | PE) +#define SSP1_SCK_ENET_1588_EVENT2_OUT (FUNC(2) | PORTF(2, 12) | SE | VE | PE) +#define SSP1_SCK_GPIO (FUNC(3) | PORTF(2, 12) | SE | VE | PE) +#define SSP0_SCK (FUNC(0) | PORTF(2, 10) | SE | VE | BK) +#define SSP0_SCK_GPIO (FUNC(3) | PORTF(2, 10) | SE | VE | BK) +#define SSP0_CD (FUNC(0) | PORTF(2, 9) | SE | VE | PE) +#define SSP0_CD_GPIO (FUNC(3) | PORTF(2, 9) | SE | VE | PE) +#define SSP0_CMD (FUNC(0) | PORTF(2, 8) | SE | VE | PE) +#define SSP0_CMD_GPIO (FUNC(3) | PORTF(2, 8) | SE | VE | PE) +#define SSP0_D7 (FUNC(0) | PORTF(2, 7) | SE | VE | PE) +#define SSP0_D7_SSP2_SCK (FUNC(1) | PORTF(2, 7) | SE | VE | PE) +#define SSP0_D7_GPIO (FUNC(3) | PORTF(2, 7) | SE | VE | PE) +#define SSP0_D6 (FUNC(0) | PORTF(2, 6) | SE | VE | PE) +#define SSP0_D6_SSP2_CMD (FUNC(1) | PORTF(2, 6) | SE | VE | PE) +#define SSP0_D6_GPIO (FUNC(3) | PORTF(2, 6) | SE | VE | PE) +#define SSP0_D5 (FUNC(0) | PORTF(2, 5) | SE | VE | PE) +#define SSP0_D5_SSP2_D3 (FUNC(1) | PORTF(2, 5) | SE | VE | PE) +#define SSP0_D5_GPIO (FUNC(3) | PORTF(2, 5) | SE | VE | PE) +#define SSP0_D4 (FUNC(0) | PORTF(2, 4) | SE | VE | PE) +#define SSP0_D4_SSP2_D0 (FUNC(1) | PORTF(2, 4) | SE | VE | PE) +#define SSP0_D4_GPIO (FUNC(3) | PORTF(2, 4) | SE | VE | PE) +#define SSP0_D3 (FUNC(0) | PORTF(2, 3) | SE | VE | PE) +#define SSP0_D3_GPIO (FUNC(3) | PORTF(2, 3) | SE | VE | PE) +#define SSP0_D2 (FUNC(0) | PORTF(2, 2) | SE | VE | PE) +#define SSP0_D2_GPIO (FUNC(3) | PORTF(2, 2) | SE | VE | PE) +#define SSP0_D1 (FUNC(0) | PORTF(2, 1) | SE | VE | PE) +#define SSP0_D1_GPIO (FUNC(3) | PORTF(2, 1) | SE | VE | PE) +#define SSP0_D0 (FUNC(0) | PORTF(2, 0) | SE | VE | PE) +#define SSP0_D0_GPIO (FUNC(3) | PORTF(2, 0) | SE | VE | PE) + +/* Bank 3, GPIO pins 96 ... 127 */ + +#define LCD_RESET (FUNC(0) | PORTF(3, 30)) +#define LCD_RESET_LCD_VSYNC (FUNC(1) | PORTF(3, 30)) +#define LCD_RESET_GPIO (FUNC(3) | PORTF(3, 30)) +#define PWM4 (FUNC(0) | PORTF(3, 29)) +#define PWM4_GPIO (FUNC(3) | PORTF(3, 29)) +#define PWM3 (FUNC(0) | PORTF(3 28)) +#define PWM3_GPIO (FUNC(3) | PORTF(3, 28)) + +#define PWM2 (FUNC(0) | PORTF(3, 18)) + +#define PWM1 (FUNC(0) | PORTF(3, 17)) + +#define PWM0 (FUNC(0) | PORTF(3, 16)) +#define PWM0_I2C1_SCL (FUNC(1) | PORTF(3, 16)) +#define PWM0_DUART_RX (FUNC(2) | PORTF(3, 16)) +#define PWM0_GPIO (FUNC(3) | PORTF(3, 16)) +#define AUART3_RTS (FUNC(0) | PORTF(3, 15) | SE | VE | BK) +#define AUART3_RTS_CAN1_RX (FUNC(1) | PORTF(3, 15) | SE | VE | BK) +#define AUART3_RTS_ENET0_1588_EVENT1_IN (FUNC(2) | PORTF(3, 15) | SE | VE | BK) +#define AUART3_RTS_GPIO (FUNC(3) | PORTF(3, 15) | SE | VE | BK) +#define AUART3_CTS (FUNC(0) | PORTF(3, 14) | SE | VE | BK | BK) +#define AUART3_CTS_CAN1_TX (FUNC(1) | PORTF(3, 14) | SE | VE | BK) +#define AUART3_CTS_ENET0_1588_EVENT1_OUT (FUNC(2) | PORTF(3, 14) | SE | VE | BK) +#define AUART3_CTS_GPIO (FUNC(3) | PORTF(3, 14) | SE | VE | BK) +#define AUART3_TX (FUNC(0) | PORTF(3, 13) | SE | VE | BK) +#define AUART3_TX_CAN0_RX (FUNC(1) | PORTF(3, 13) | SE | VE | BK) +#define AUART3_TX_ENET0_1588_EVENT0_IN (FUNC(2) | PORTF(3, 13) | SE | VE | BK) +#define AUART3_TX_GPIO (FUNC(3) | PORTF(3, 13) | SE | VE | BK) +#define AUART3_RX (FUNC(0) | PORTF(3, 12) | SE | VE | BK) +#define AUART3_RX_CAN0_TX (FUNC(1) | PORTF(3, 12) | SE | VE | BK) +#define AUART3_RX_ENET0_1588_EVENT0_OUT (FUNC(2) | PORTF(3, 12) | SE | VE | BK) +#define AUART3_RX_GPIO (FUNC(3) | PORTF(3, 12) | SE | VE | BK) +#define AUART2_RTS (FUNC(0) | PORTF(3, 11) | SE | VE | BK) +#define AUART2_RTS_I2C1_SDA (FUNC(1) | PORTF(3, 11) | SE | VE | BK) +#define AUART2_RTS_SAIF1_IRCLK (FUNC(2) | PORTF(3, 11) | SE | VE | BK) +#define AUART2_RTS_GPIO (FUNC(3) | PORTF(3, 11) | SE | VE | BK) +#define AUART2_CTS (FUNC(0) | PORTF(3, 10) | SE | VE | BK) +#define AUART2_CTS_I2C1_SCL (FUNC(1) | PORTF(3, 10) | SE | VE | BK) +#define AUART2_CTS_SAIF1_BITCLK (FUNC(2) | PORTF(3, 10) | SE | VE | BK) +#define AUART2_CTS_GPIO (FUNC(3) | PORTF(3, 10) | SE | VE | BK) +#define AUART2_TX (FUNC(0) | PORTF(3, 9) | SE | VE | PE) +#define AUART2_TX_SSP3_D2 (FUNC(1) | PORTF(3, 9) | SE | VE | PE) +#define AUART2_TX_SSP3_D5 (FUNC(2) | PORTF(3, 9) | SE | VE | PE) +#define AUART2_TX_GPIO (FUNC(3) | PORTF(3, 9) | SE | VE | PE) +#define AUART2_RX (FUNC(0) | PORTF(3, 8) | SE | VE | PE) +#define AUART2_RX_SSP3_D1 (FUNC(1) | PORTF(3, 8) | SE | VE | PE) +#define AUART2_RX_SSP3_D4 (FUNC(2) | PORTF(3, 8) | SE | VE | PE) +#define AUART2_RX_GPIO (FUNC(3) | PORTF(3, 8) | SE | VE | PE) +#define AUART1_RTS (FUNC(0) | PORTF(3, 7) | SE | VE | PE) +#define AUART1_RTS_USB0_ID (FUNC(1) | PORTF(3, 7) | SE | VE | PE) +#define AUART1_RTS_ROTARYB (FUNC(2) | PORTF(3, 7) | SE | VE | PE) +#define AUART1_RTS_GPIO (FUNC(3) | PORTF(3, 7) | SE | VE | PE) +#define AUART1_CTS (FUNC(0) | PORTF(3, 6) | SE | VE | PE) +#define AUART1_CTS_USB0_OC (FUNC(1) | PORTF(3, 6) | SE | VE | PE) +#define AUART1_CTS_ROTARYA (FUNC(2) | PORTF(3, 6) | SE | VE | PE) +#define AUART1_CTS_GPIO (FUNC(3) | PORTF(3, 6) | SE | VE | PE) +#define AUART1_TX (FUNC(0) | PORTF(3, 5) | SE | VE | BK) +#define AUART1_TX_SSP3_CD (FUNC(1) | PORTF(3, 5) | SE | VE | BK) +#define AUART1_TX_PWM1 (FUNC(2) | PORTF(3, 5) | SE | VE | BK) +#define AUART1_TX_GPIO (FUNC(3) | PORTF(3, 5) | SE | VE | BK) +#define AUART1_RX (FUNC(0) | PORTF(3, 4) | SE | VE | BK) +#define AUART1_RX_SSP2_CD (FUNC(1) | PORTF(3, 4) | SE | VE | BK) +#define AUART1_RX_PWM0 (FUNC(2) | PORTF(3, 4) | SE | VE | BK) +#define AUART1_RX_GPIO (FUNC(3) | PORTF(3, 4) | SE | VE | BK) +#define AUART0_RTS (FUNC(0) | PORTF(3, 3) | SE | VE | BK) +#define AUART0_RTS_AUART4_TX (FUNC(1) | PORTF(3, 3) | SE | VE | BK) +#define AUART0_RTS_DUART_TX (FUNC(2) | PORTF(3, 3) | SE | VE | BK) +#define AUART0_RTS_GPIO (FUNC(3) | PORTF(3, 3) | SE | VE | BK) +#define AUART0_CTS (FUNC(0) | PORTF(3, 2) | SE | VE | BK) +#define AUART0_CTS_AUART4_RX (FUNC(1) | PORTF(3, 2) | SE | VE | BK) +#define AUART0_CTS_DUART_RX (FUNC(2) | PORTF(3, 2) | SE | VE | BK) +#define AUART0_CTS_GPIO (FUNC(3) | PORTF(3, 2) | SE | VE | BK) +#define AUART0_TX (FUNC(0) | PORTF(3, 1) | SE | VE | BK) +#define AUART0_TX_I2C0_SDA (FUNC(1) | PORTF(3, 1) | SE | VE | BK) +#define AUART0_TX_DUART_RTS (FUNC(2) | PORTF(3, 1) | SE | VE | BK) +#define AUART0_TX_GPIO (FUNC(3) | PORTF(3, 1) | SE | VE | BK) +#define AUART0_RX (FUNC(0) | PORTF(3, 0) | SE | VE | BK) +#define AUART0_RX_I2C0_SCL (FUNC(1) | PORTF(3, 0) | SE | VE | BK) +#define AUART0_RX_DUART_CTS (FUNC(2) | PORTF(3, 0) | SE | VE | BK) +#define AUART0_RX_GPIO (FUNC(3) | PORTF(3, 0) | SE | VE | BK) + +/* Bank 4, GPIO pins 128 ... 159 */ + +#define JTAG_RTCK (FUNC(0) | PORTF(4, 20) | SE | VE | BK) +#define JTAG_RTCK_GPIO (FUNC(3) | PORTF(4, 20) | SE | VE | BK) +#define ENET_CLK (FUNC(0) | PORTF(4, 16) | SE | VE | BK) +#define ENET_CLK_GPIO (FUNC(3) | PORTF(4, 16) | SE | VE | BK) + +#define ENET0_CRS (FUNC(0) | PORTF(4, 15) | SE | VE | BK) + +#define ENET0_COL (FUNC(0) | PORTF(4, 14) | SE | VE | BK) + +#define ENET0_RX_CLK (FUNC(0) | PORTF(4, 13) | SE | VE | BK) +#define ENET0_RX_CLK_RX_ER (FUNC(1) | PORTF(4, 13) | SE | VE | BK) +#define ENET0_RX_ENET0_1588_EVENT2_IN (FUNC(2) | PORTF(4, 13) | SE | VE | BK) +#define ENET0_RX_CLK_GPIO (FUNC(3) | PORTF(4, 13) | SE | VE | BK) +#define ENET0_TXD3 (FUNC(0) | PORTF(4, 12) | SE | VE | BK) +#define ENET0_TXD3_ENET1_TXD1 (FUNC(1) | PORTF(4, 12) | SE | VE | BK) +#define ENET0_TXD3_ENET0_1588_EVENT1_IN (FUNC(2) | PORTF(4, 12) | SE | VE | BK) +#define ENET0_TXD3_GPIO (FUNC(3) | PORTF(4, 12) | SE | VE | BK) + +#define ENET0_TXD2 (FUNC(0) | PORTF(4, 11) | SE | VE | BK) + +#define ENET0_TXD2_GPIO (FUNC(3) | PORTF(4, 11) | SE | VE | BK) + +#define ENET0_RXD3 (FUNC(0) | PORTF(4, 10) | SE | VE | BK) +#define ENET0_RXD3_ENET1_RXD1 (FUNC(1) | PORTF(4, 10) | SE | VE | BK) +#define ENET0_RXD3_ENET0_1588_EVENT0_IN (FUNC(2) | PORTF(4, 10) | SE | VE | BK) +#define ENET0_RXD3_GPIO (FUNC(3) | PORTF(4, 10) | SE | VE | BK) + +#define ENET0_RXD2 (FUNC(0) | PORTF(4, 9) | SE | VE | BK) + +#define ENET0_RXD2_GPIO (FUNC(3) | PORTF(4, 9) | SE | VE | BK) + +#define ENET0_TXD1 (FUNC(0) | PORTF(4, 8) | SE | VE | PE) + +#define ENET0_TXD1_GPIO (FUNC(3) | PORTF(4, 8) | SE | VE | PE) + +#define ENET0_TXD0 (FUNC(0) | PORTF(4, 7) | SE | VE | PE) + +#define ENET0_TXD0_GPIO (FUNC(3) | PORTF(4, 7) | SE | VE | PE) + +#define ENET0_TX_EN (FUNC(0) | PORTF(4, 6) | SE | VE | PE) + +#define ENET0_TX_EN_GPIO (FUNC(3) | PORTF(4, 6) | SE | VE | PE) + +#define ENET0_TX_CLK (FUNC(0) | PORTF(4, 5) | SE | VE | BK) + +#define ENET0_TX_CLK_GPIO (FUNC(3) | PORTF(4, 5) | SE | VE | BK) + +#define ENET0_RXD1 (FUNC(0) | PORTF(4, 4) | SE | VE | PE) +#define ENET0_RXD1_GPMI_READY4 (FUNC(1) | PORTF(4, 4) | SE | VE | PE) +#define ENET0_RXD1_GPIO (FUNC(3) | PORTF(4, 4) | SE | VE | PE) +#define ENET0_RXD0 (FUNC(0) | PORTF(4, 3) | SE | VE | PE) +#define ENET0_RXD0_GPMI_CE7N (FUNC(1) | PORTF(4, 3) | SE | VE | PE) +#define ENET0_RXD0_SAIF1_SDATA2 (FUNC(2) | PORTF(4, 3) | SE | VE | PE) +#define ENET0_RXD0_GPIO (FUNC(3) | PORTF(4, 3) | SE | VE | PE) +#define ENET0_RX_EN (FUNC(0) | PORTF(4, 2) | SE | VE | PE) +#define ENET0_RX_EN_GPMI_CE6N (FUNC(1) | PORTF(4, 2) | SE | VE | PE) +#define ENET0_RX_EN_SAIF1_SDATA1 (FUNC(2) | PORTF(4, 2) | SE | VE | PE) +#define ENET0_RX_EN_GPIO (FUNC(3) | PORTF(4, 2) | SE | VE | PE) +#define ENET0_MDIO (FUNC(0) | PORTF(4, 1) | SE | VE | PE) +#define ENET0_MDIO_GPMI_CE5N (FUNC(1) | PORTF(4, 1) | SE | VE | PE) +#define ENET0_MDIO_SAIF0_SDATA2 (FUNC(2) | PORTF(4, 1) | SE | VE | PE) +#define ENET0_MDIO_GPIO (FUNC(3) | PORTF(4, 1) | SE | VE | PE) +#define ENET0_MDC (FUNC(0) | PORTF(4, 0) | SE | VE | PE) +#define ENET0_MDC_GPMI_CE4N (FUNC(1) | PORTF(4, 0) | SE | VE | PE) +#define ENET0_MDC_SAIF0_SDATA1 (FUNC(2) | PORTF(4, 0) | SE | VE | PE) +#define ENET0_MDC_GPIO (FUNC(3) | PORTF(4, 0) | SE | VE | PE) + +/* + * Bank 5, GPIO pins 160 ... 191 + * Note: These pins are disabled instead of being GPIOs + */ +#define EMI_DDR_OPEN (FUNC(0) | PORTF(5, 26) | BK) +#define EMI_DDR_OPEN_OFF (FUNC(3) | PORTF(5, 26) | BK) +#define EMI_DSQ1 (FUNC(0) | PORTF(5, 23) | BK) +#define EMI_DSQ1_OFF (FUNC(3) | PORTF(5, 23) | BK) +#define EMI_DSQ0 (FUNC(0) | PORTF(5, 22) | BK) +#define EMI_DSQ0_OFF (FUNC(3) | PORTF(5, 22) | BK) +#define EMI_CLK (FUNC(0) | PORTF(5, 21) | BK) +#define EMI_CLK_OFF (FUNC(3) | PORTF(5, 21) | BK) +#define EMI_DDR_OPEN_FB (FUNC(0) | PORTF(5, 20) | BK) +#define EMI_DDR_OPEN_FB_OFF (FUNC(3) | PORTF(5, 20) | BK) +#define EMI_DQM1 (FUNC(0) | PORTF(5, 19) | BK) +#define EMI_DQM1_OFF (FUNC(3) | PORTF(5, 19) | BK) +#define EMI_ODT1 (FUNC(0) | PORTF(5, 18) | BK) +#define EMI_ODT1_OFF (FUNC(3) | PORTF(5, 18) | BK) +#define EMI_DQM0 (FUNC(0) | PORTF(5, 17) | BK) +#define EMI_DQM0_OFF (FUNC(3) | PORTF(5, 17) | BK) +#define EMI_ODT0 (FUNC(0) | PORTF(5, 16) | BK) +#define EMI_ODT0_OFF (FUNC(3) | PORTF(5, 16) | BK) +#define EMI_DATA15 (FUNC(0) | PORTF(5, 15) | BK) +#define EMI_DATA15_OFF (FUNC(3) | PORTF(5, 15) | BK) +#define EMI_DATA14 (FUNC(0) | PORTF(5, 14) | BK) +#define EMI_DATA14_OFF (FUNC(3) | PORTF(5, 14) | BK) +#define EMI_DATA13 (FUNC(0) | PORTF(5, 13) | BK) +#define EMI_DATA13_OFF (FUNC(3) | PORTF(5, 13) | BK) +#define EMI_DATA12 (FUNC(0) | PORTF(5, 12) | BK) +#define EMI_DATA12_OFF (FUNC(3) | PORTF(5, 12) | BK) +#define EMI_DATA11 (FUNC(0) | PORTF(5, 11) | BK) +#define EMI_DATA10_OFF (FUNC(3) | PORTF(5, 10) | BK) +#define EMI_DATA10 (FUNC(0) | PORTF(5, 10) | BK) +#define EMI_DATA10_OFF (FUNC(3) | PORTF(5, 10) | BK) +#define EMI_DATA9 (FUNC(0) | PORTF(5, 9) | BK) +#define EMI_DATA9_OFF (FUNC(3) | PORTF(5, 9) | BK) +#define EMI_DATA8 (FUNC(0) | PORTF(5, 8) | BK) +#define EMI_DATA8_OFF (FUNC(3) | PORTF(5, 8) | BK) +#define EMI_DATA7 (FUNC(0) | PORTF(5, 7) | BK) +#define EMI_DATA7_OFF (FUNC(3) | PORTF(5, 7) | BK) +#define EMI_DATA6 (FUNC(0) | PORTF(5, 6) | BK) +#define EMI_DATA6_OFF (FUNC(3) | PORTF(5, 6) | BK) +#define EMI_DATA5 (FUNC(0) | PORTF(5, 5) | BK) +#define EMI_DATA5_OFF (FUNC(3) | PORTF(5, 5) | BK) +#define EMI_DATA4 (FUNC(0) | PORTF(5, 4) | BK) +#define EMI_DATA4_OFF (FUNC(3) | PORTF(5, 4) | BK) +#define EMI_DATA3 (FUNC(0) | PORTF(5, 3) | BK) +#define EMI_DATA3_OFF (FUNC(3) | PORTF(5, 3) | BK) +#define EMI_DATA2 (FUNC(0) | PORTF(5, 2) | BK) +#define EMI_DATA2_OFF (FUNC(3) | PORTF(5, 2) | BK) +#define EMI_DATA1 (FUNC(0) | PORTF(5, 1) | BK) +#define EMI_DATA1_OFF (FUNC(3) | PORTF(5, 1) | BK) +#define EMI_DATA0 (FUNC(0) | PORTF(5, 0) | BK) +#define EMI_DATA0_OFF (FUNC(3) | PORTF(5, 0) | BK) + +/* + * Bank 6, GPIO pins 192 ... 223 + * Note: This pins are disabled instead of being GPIOs + */ +#define EMI_CKE (FUNC(0) | PORTF(6, 24) | BK) +#define EMI_CKE_OFF (FUNC(3) | PORTF(6, 24) | BK) +#define EMI_CE1N (FUNC(0) | PORTF(6, 23) | BK) +#define EMI_CE1N_OFF (FUNC(3) | PORTF(6, 23) | BK) +#define EMI_CE0N (FUNC(0) | PORTF(6, 22) | BK) +#define EMI_CE0N_OFF (FUNC(3) | PORTF(6, 22) | BK) +#define EMI_WEN (FUNC(0) | PORTF(6, 21) | BK) +#define EMI_WEN_OFF (FUNC(3) | PORTF(6, 21) | BK) +#define EMI_RASN (FUNC(0) | PORTF(6, 20) | BK) +#define EMI_RASN_OFF (FUNC(3) | PORTF(6, 20) | BK) +#define EMI_CASN (FUNC(0) | PORTF(6, 19) | BK) +#define EMI_CASN_OFF (FUNC(3) | PORTF(6, 19) | BK) +#define EMI_BA2 (FUNC(0) | PORTF(6, 18) | BK) +#define EMI_BA2_OFF (FUNC(3) | PORTF(6, 18) | BK) +#define EMI_BA1 (FUNC(0) | PORTF(6, 17) | BK) +#define EMI_BA1_OFF (FUNC(3) | PORTF(6, 17) | BK) +#define EMI_BA0 (FUNC(0) | PORTF(6, 16) | BK) +#define EMI_BA0_OFF (FUNC(3) | PORTF(6, 16) | BK) +#define EMI_A14 (FUNC(0) | PORTF(6, 14) | BK) +#define EMI_A14_OFF (FUNC(3) | PORTF(6, 14) | BK) +#define EMI_A13 (FUNC(0) | PORTF(6, 13) | BK) +#define EMI_A13_OFF (FUNC(3) | PORTF(6, 13) | BK) +#define EMI_A12 (FUNC(0) | PORTF(6, 12) | BK) +#define EMI_A12_OFF (FUNC(3) | PORTF(6, 12) | BK) +#define EMI_A11 (FUNC(0) | PORTF(6, 11) | BK) +#define EMI_A11_OFF (FUNC(3) | PORTF(6, 11) | BK) +#define EMI_A10 (FUNC(0) | PORTF(6, 10) | BK) +#define EMI_A10_OFF (FUNC(3) | PORTF(6, 10) | BK) +#define EMI_A9 (FUNC(0) | PORTF(6, 9) | BK) +#define EMI_A9_OFF (FUNC(3) | PORTF(6, 9) | BK) +#define EMI_A8 (FUNC(0) | PORTF(6, 8) | BK) +#define EMI_A8_OFF (FUNC(3) | PORTF(6, 8) | BK) +#define EMI_A7 (FUNC(0) | PORTF(6, 7) | BK) +#define EMI_A7_OFF (FUNC(3) | PORTF(6, 7) | BK) +#define EMI_A6 (FUNC(0) | PORTF(6, 6) | BK) +#define EMI_A6_OFF (FUNC(3) | PORTF(6, 6) | BK) +#define EMI_A5 (FUNC(0) | PORTF(6, 5) | BK) +#define EMI_A5_OFF (FUNC(3) | PORTF(6, 5) | BK) +#define EMI_A4 (FUNC(0) | PORTF(6, 4) | BK) +#define EMI_A4_OFF (FUNC(3) | PORTF(6, 4) | BK) +#define EMI_A3 (FUNC(0) | PORTF(6, 3) | BK) +#define EMI_A3_OFF (FUNC(3) | PORTF(6, 3) | BK) +#define EMI_A2 (FUNC(0) | PORTF(6, 2) | BK) +#define EMI_A2_OFF (FUNC(3) | PORTF(6, 2) | BK) +#define EMI_A1 (FUNC(0) | PORTF(6, 1) | BK) +#define EMI_A1_OFF (FUNC(3) | PORTF(6, 1) | BK) +#define EMI_A0 (FUNC(0) | PORTF(6, 0) | BK) +#define EMI_A0_OFF (FUNC(3) | PORTF(6, 0) | BK) + +#endif /* __MACH_IOMUX_IMX28_H */ diff --git a/arch/arm/mach-mxs/include/mach/mci.h b/arch/arm/mach-mxs/include/mach/mci.h new file mode 100644 index 0000000000..b9249085ae --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/mci.h @@ -0,0 +1,32 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MACH_MMC_H +#define __MACH_MMC_H + +struct stm_mci_platform_data { + unsigned caps; /**< supported operating modes (MMC_MODE_*) */ + unsigned voltages; /**< supported voltage range (MMC_VDD_*) */ + unsigned f_min; /**< min operating frequency in Hz (0 -> no limit) */ + unsigned f_max; /**< max operating frequency in Hz (0 -> no limit) */ + /* TODO */ + /* function to modify the voltage */ + /* function to switch the voltage */ + /* function to detect the presence of a SD card in the socket */ +}; + +#endif /* __MACH_MMC_H */ diff --git a/arch/arm/mach-mxs/include/mach/usb.h b/arch/arm/mach-mxs/include/mach/usb.h new file mode 100644 index 0000000000..af7d885cb3 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/usb.h @@ -0,0 +1,6 @@ +#ifndef __MACH_USB_H +#define __MACH_USB_H + +int imx_usb_phy_enable(void); + +#endif /* __MACH_USB_H */ diff --git a/arch/arm/mach-mxs/iomux-imx.c b/arch/arm/mach-mxs/iomux-imx.c new file mode 100644 index 0000000000..bf6165f8d2 --- /dev/null +++ b/arch/arm/mach-mxs/iomux-imx.c @@ -0,0 +1,201 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <init.h> +#include <gpio.h> +#include <errno.h> +#include <asm/io.h> +#include <mach/imx-regs.h> + +#define HW_PINCTRL_CTRL 0x000 +#define HW_PINCTRL_MUXSEL0 0x100 + +#ifdef CONFIG_ARCH_IMX23 +#define HW_PINCTRL_DRIVE0 0x200 +#define HW_PINCTRL_PULL0 0x400 +#define HW_PINCTRL_DOUT0 0x500 +#define HW_PINCTRL_DIN0 0x600 +#define HW_PINCTRL_DOE0 0x700 + +#define MAX_GPIO_NO 95 +#endif + +#ifdef CONFIG_ARCH_IMX28 +#define HW_PINCTRL_DRIVE0 0x300 +#define HW_PINCTRL_PULL0 0x600 +#define HW_PINCTRL_DOUT0 0x700 +#define HW_PINCTRL_DIN0 0x900 +#define HW_PINCTRL_DOE0 0xb00 + +#define MAX_GPIO_NO 159 +#endif + +static unsigned calc_mux_reg(unsigned no) +{ + /* each register controls 16 pads */ + return ((no >> 4) << 4) + HW_PINCTRL_MUXSEL0; +} + +static unsigned calc_strength_reg(unsigned no) +{ + /* each register controls 8 pads */ + return ((no >> 3) << 4) + HW_PINCTRL_DRIVE0; +} + +static unsigned calc_pullup_reg(unsigned no) +{ + /* each register controls 32 pads */ + return ((no >> 5) << 4) + HW_PINCTRL_PULL0; +} + +static unsigned calc_output_enable_reg(unsigned no) +{ + /* each register controls 32 pads */ + return ((no >> 5) << 4) + HW_PINCTRL_DOE0; +} + +static unsigned calc_output_reg(unsigned no) +{ + /* each register controls 32 pads */ + return ((no >> 5) << 4) + HW_PINCTRL_DOUT0; +} + +static unsigned calc_input_reg(unsigned no) +{ + /* each register controls 32 pads */ + return ((no >> 5) << 4) + HW_PINCTRL_DIN0; +} + +/** + * @param[in] m One pin define per call from iomux-mx23.h/iomux-mx28.h + */ +void imx_gpio_mode(uint32_t m) +{ + uint32_t reg; + unsigned gpio_pin, reg_offset; + + gpio_pin = GET_GPIO_NO(m); + + /* configure the pad to its function (always) */ + reg_offset = calc_mux_reg(gpio_pin); + reg = readl(IMX_IOMUXC_BASE + reg_offset) & ~(0x3 << ((gpio_pin % 16) << 1)); + reg |= GET_FUNC(m) << ((gpio_pin % 16) << 1); + writel(reg, IMX_IOMUXC_BASE + reg_offset); + + /* some pins are disabled when configured for GPIO */ + if ((gpio_pin > MAX_GPIO_NO) && (GET_FUNC(m) == IS_GPIO)) { + printf("Cannot configure pad %d to GPIO\n", gpio_pin); + return; + } + + if (SE_PRESENT(m)) { + reg_offset = calc_strength_reg(gpio_pin); + reg = readl(IMX_IOMUXC_BASE + reg_offset) & ~(0x3 << ((gpio_pin % 8) << 2)); + reg |= GET_STRENGTH(m) << ((gpio_pin % 8) << 2); + writel(reg, IMX_IOMUXC_BASE + reg_offset); + } + + if (VE_PRESENT(m)) { + reg_offset = calc_strength_reg(gpio_pin); + if (GET_VOLTAGE(m) == 1) + writel(0x1 << (((gpio_pin % 8) << 2) + 2), + IMX_IOMUXC_BASE + reg_offset + BIT_SET); + else + writel(0x1 << (((gpio_pin % 8) << 2) + 2), + IMX_IOMUXC_BASE + reg_offset + BIT_CLR); + } + + if (PE_PRESENT(m)) { + reg_offset = calc_pullup_reg(gpio_pin); + writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + + (GET_PULLUP(m) == 1 ? BIT_SET : BIT_CLR)); + } + + if (GET_FUNC(m) == IS_GPIO) { + if (GET_GPIODIR(m) == 1) { + /* first set the output value */ + reg_offset = calc_output_reg(gpio_pin); + writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + + reg_offset + (GET_GPIOVAL(m) == 1 ? BIT_SET : BIT_CLR)); + /* then the direction */ + reg_offset = calc_output_enable_reg(gpio_pin); + writel(0x1 << (gpio_pin % 32), + IMX_IOMUXC_BASE + reg_offset + BIT_SET); + } else { + /* then the direction */ + reg_offset = calc_output_enable_reg(gpio_pin); + writel(0x1 << (gpio_pin % 32), + IMX_IOMUXC_BASE + reg_offset + BIT_CLR); + } + } +} + +int gpio_direction_input(unsigned gpio) +{ + unsigned reg_offset; + + if (gpio > MAX_GPIO_NO) + return -EINVAL; + + reg_offset = calc_output_enable_reg(gpio); + writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + BIT_CLR); + + return 0; +} + +int gpio_direction_output(unsigned gpio, int val) +{ + unsigned reg_offset; + + if (gpio > MAX_GPIO_NO) + return -EINVAL; + + /* first set the output value... */ + reg_offset = calc_output_reg(gpio); + writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + + reg_offset + (val != 0 ? BIT_SET : BIT_CLR)); + /* ...then the direction */ + reg_offset = calc_output_enable_reg(gpio); + writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + BIT_SET); + + return 0; +} + +void gpio_set_value(unsigned gpio, int val) +{ + unsigned reg_offset; + + reg_offset = calc_output_reg(gpio); + writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + + reg_offset + (val != 0 ? BIT_SET : BIT_CLR)); +} + +int gpio_get_value(unsigned gpio) +{ + uint32_t reg; + unsigned reg_offset; + + reg_offset = calc_input_reg(gpio); + reg = readl(IMX_IOMUXC_BASE + reg_offset); + if (reg & (0x1 << (gpio % 32))) + return 1; + + return 0; +} diff --git a/arch/arm/mach-mxs/reset-imx.c b/arch/arm/mach-mxs/reset-imx.c new file mode 100644 index 0000000000..b35f796b40 --- /dev/null +++ b/arch/arm/mach-mxs/reset-imx.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <init.h> +#include <notifier.h> +#include <mach/imx-regs.h> +#include <asm/io.h> + +#define HW_RTC_CTRL 0x000 +# define BM_RTC_CTRL_WATCHDOGEN (1 << 4) +#define HW_RTC_CTRL_SET 0x004 +#define HW_RTC_CTRL_CLR 0x008 +#define HW_RTC_CTRL_TOG 0x00C + +#define HW_RTC_WATCHDOG 0x050 +#define HW_RTC_WATCHDOG_SET 0x054 +#define HW_RTC_WATCHDOG_CLR 0x058 +#define HW_RTC_WATCHDOG_TOG 0x05C + +#define WDOG_COUNTER_RATE 1000 /* 1 kHz clock */ + +#define HW_RTC_PERSISTENT1 0x070 +# define BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER 0x80000000 +#define HW_RTC_PERSISTENT1_SET 0x074 +#define HW_RTC_PERSISTENT1_CLR 0x078 +#define HW_RTC_PERSISTENT1_TOG 0x07C + +/* + * Reset the cpu by setting up the watchdog timer and let it time out + * + * TODO There is a much easier way to reset the CPU: Refer bit 2 in + * the HW_CLKCTRL_RESET register, data sheet page 106/4-30 + */ +void __noreturn reset_cpu (unsigned long addr) +{ + writel(WDOG_COUNTER_RATE, IMX_WDT_BASE + HW_RTC_WATCHDOG); + writel(BM_RTC_CTRL_WATCHDOGEN, IMX_WDT_BASE + HW_RTC_CTRL_SET); + writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER, IMX_WDT_BASE + HW_RTC_PERSISTENT1); + + while (1) + ; + /*NOTREACHED*/ +} +EXPORT_SYMBOL(reset_cpu); diff --git a/arch/arm/mach-mxs/speed-imx23.c b/arch/arm/mach-mxs/speed-imx23.c new file mode 100644 index 0000000000..a31139d7a7 --- /dev/null +++ b/arch/arm/mach-mxs/speed-imx23.c @@ -0,0 +1,278 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix + * + * This code is based partially on code of: + * + * (c) 2008 Embedded Alley Solutions, Inc. + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <init.h> +#include <asm/io.h> +#include <mach/imx-regs.h> +#include <mach/generic.h> +#include <mach/clock.h> + +#define HW_CLKCTRL_PLLCTRL0 0x000 +#define HW_CLKCTRL_PLLCTRL1 0x010 +#define HW_CLKCTRL_CPU 0x20 +# define GET_CPU_XTAL_DIV(x) (((x) >> 16) & 0x3ff) +# define GET_CPU_PLL_DIV(x) ((x) & 0x3f) +#define HW_CLKCTRL_HBUS 0x30 +#define HW_CLKCTRL_XBUS 0x40 +#define HW_CLKCTRL_XTAL 0x050 +#define HW_CLKCTRL_PIX 0x060 +/* note: no set/clear register! */ +#define HW_CLKCTRL_SSP 0x070 +/* note: no set/clear register! */ +# define CLKCTRL_SSP_CLKGATE (1 << 31) +# define CLKCTRL_SSP_BUSY (1 << 29) +# define CLKCTRL_SSP_DIV_MASK 0x1ff +# define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) +# define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) +#define HW_CLKCTRL_GPMI 0x080 +/* note: no set/clear register! */ +#define HW_CLKCTRL_SPDIF 0x090 +/* note: no set/clear register! */ +#define HW_CLKCTRL_EMI 0xa0 +/* note: no set/clear register! */ +# define CLKCTRL_EMI_CLKGATE (1 << 31) +# define GET_EMI_XTAL_DIV(x) (((x) >> 8) & 0xf) +# define GET_EMI_PLL_DIV(x) ((x) & 0x3f) +#define HW_CLKCTRL_SAIF 0x0c0 +#define HW_CLKCTRL_TV 0x0d0 +#define HW_CLKCTRL_ETM 0x0e0 +#define HW_CLKCTRL_FRAC 0xf0 +# define CLKCTRL_FRAC_CLKGATEIO (1 << 31) +# define GET_IOFRAC(x) (((x) >> 24) & 0x3f) +# define SET_IOFRAC(x) (((x) & 0x3f) << 24) +# define CLKCTRL_FRAC_CLKGATEPIX (1 << 23) +# define GET_PIXFRAC(x) (((x) >> 16) & 0x3f) +# define CLKCTRL_FRAC_CLKGATEEMI (1 << 15) +# define GET_EMIFRAC(x) (((x) >> 8) & 0x3f) +# define CLKCTRL_FRAC_CLKGATECPU (1 << 7) +# define GET_CPUFRAC(x) ((x) & 0x3f) +#define HW_CLKCTRL_FRAC1 0x100 +#define HW_CLKCTRL_CLKSEQ 0x110 +# define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) +# define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7) +# define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6) +# define CLKCTRL_CLKSEQ_BYPASS_SSP (1 << 5) +# define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4) +#define HW_CLKCTRL_RESET 0x120 +#define HW_CLKCTRL_STATUS 0x130 +#define HW_CLKCTRL_VERSION 0x140 + +unsigned imx_get_mpllclk(void) +{ + /* the main PLL runs at 480 MHz */ + return 480000000; +} + +unsigned imx_get_xtalclk(void) +{ + /* the external reference runs at 24 MHz */ + return 24000000; +} + +/* used for the SDRAM controller */ +unsigned imx_get_emiclk(void) +{ + uint32_t reg; + unsigned rate; + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_EMI) & CLKCTRL_EMI_CLKGATE) + return 0U; /* clock is off */ + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_EMI) + return imx_get_xtalclk() / GET_EMI_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI)); + + rate = imx_get_mpllclk() / 1000; + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC); + if (!(reg & CLKCTRL_FRAC_CLKGATEEMI)) { + rate *= 18U; + rate /= GET_EMIFRAC(reg); + } + + return (rate / GET_EMI_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI))) + * 1000; +} + +/* + * Source of ssp, gpmi, ir + */ +unsigned imx_get_ioclk(void) +{ + uint32_t reg; + unsigned rate = imx_get_mpllclk() / 1000; + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC); + if (reg & CLKCTRL_FRAC_CLKGATEIO) + return 0U; /* clock is off */ + + rate *= 18U; + rate /= GET_IOFRAC(reg); + return rate * 1000; +} + +/** + * Setup a new frequency to the IOCLK domain. + * @param nc New frequency in [Hz] + * + * The FRAC divider for the IOCLK must be between 18 (* 18/18) and 35 (* 18/35) + */ +unsigned imx_set_ioclk(unsigned nc) +{ + uint32_t reg; + unsigned div; + + nc /= 1000; + div = (imx_get_mpllclk() / 1000) * 18; + div = DIV_ROUND_CLOSEST(div, nc); + if (div > 0x3f) + div = 0x3f; + /* mask the current settings */ + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC) & ~(SET_IOFRAC(0x3f)); + writel(reg | SET_IOFRAC(div), IMX_CCM_BASE + HW_CLKCTRL_FRAC); + /* enable the IO clock at its new frequency */ + writel(CLKCTRL_FRAC_CLKGATEIO, IMX_CCM_BASE + HW_CLKCTRL_FRAC + 8); + + return imx_get_ioclk(); +} + +/* this is CPU core clock */ +unsigned imx_get_armclk(void) +{ + uint32_t reg; + unsigned rate; + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_CPU) + return imx_get_xtalclk() / GET_CPU_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU)); + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC); + if (reg & CLKCTRL_FRAC_CLKGATECPU) + return 0U; /* should not possible, shouldn't it? */ + + rate = imx_get_mpllclk() / 1000; + rate *= 18U; + rate /= GET_CPUFRAC(reg); + + return (rate / GET_CPU_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU))) + * 1000; +} + +/* this is the AHB and APBH bus clock */ +unsigned imx_get_hclk(void) +{ + unsigned rate = imx_get_armclk() / 1000; + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x20) { + rate *= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; + rate >>= 5U; /* / 32 */ + } else + rate /= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; + return rate * 1000; +} + +/* + * Source of UART, debug UART, audio, PWM, dri, timer, digctl + */ +unsigned imx_get_xclk(void) +{ + unsigned rate = imx_get_xtalclk(); /* runs from the 24 MHz crystal reference */ + + return rate / (readl(IMX_CCM_BASE + HW_CLKCTRL_XBUS) & 0x3ff); +} + +/* 'index' gets ignored on i.MX23 */ +unsigned imx_get_sspclk(unsigned index) +{ + unsigned rate; + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_CLKGATE) + return 0U; /* clock is off */ + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_SSP) + rate = imx_get_xtalclk(); + else + rate = imx_get_ioclk(); + + return rate / GET_SSP_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_SSP)); +} + +/** + * @param index Unit index (ignored on i.MX23) + * @param nc New frequency in [Hz] + * @param high != 0 if ioclk should be the source + * @return The new possible frequency in [kHz] + */ +unsigned imx_set_sspclk(unsigned index, unsigned nc, int high) +{ + uint32_t reg; + unsigned ssp_div; + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & ~CLKCTRL_SSP_CLKGATE; + /* Datasheet says: Do not change the DIV setting if the clock is off */ + writel(reg, IMX_CCM_BASE + HW_CLKCTRL_SSP); + /* Wait while clock is gated */ + while (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_CLKGATE) + ; + + if (high) + ssp_div = imx_get_ioclk(); + else + ssp_div = imx_get_xtalclk(); + + if (nc > ssp_div) { + printf("Cannot setup SSP unit clock to %u Hz, base clock is only %u Hz\n", nc, ssp_div); + ssp_div = 1U; + } else { + ssp_div = DIV_ROUND_UP(ssp_div, nc); + if (ssp_div > CLKCTRL_SSP_DIV_MASK) + ssp_div = CLKCTRL_SSP_DIV_MASK; + } + + /* Set new divider value */ + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & ~CLKCTRL_SSP_DIV_MASK; + writel(reg | SET_SSP_DIV(ssp_div), IMX_CCM_BASE + HW_CLKCTRL_SSP); + + /* Wait until new divider value is set */ + while (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_BUSY) + ; + + if (high) + /* switch to ioclock */ + writel(CLKCTRL_CLKSEQ_BYPASS_SSP, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 8); + else + /* switch to 24 MHz crystal */ + writel(CLKCTRL_CLKSEQ_BYPASS_SSP, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 4); + + return imx_get_sspclk(index); +} + +void imx_dump_clocks(void) +{ + printf("mpll: %10u kHz\n", imx_get_mpllclk() / 1000); + printf("arm: %10u kHz\n", imx_get_armclk() / 1000); + printf("ioclk: %10u kHz\n", imx_get_ioclk() / 1000); + printf("emiclk: %10u kHz\n", imx_get_emiclk() / 1000); + printf("hclk: %10u kHz\n", imx_get_hclk() / 1000); + printf("xclk: %10u kHz\n", imx_get_xclk() / 1000); + printf("ssp: %10u kHz\n", imx_get_sspclk(0) / 1000); +} diff --git a/arch/arm/mach-mxs/speed-imx28.c b/arch/arm/mach-mxs/speed-imx28.c new file mode 100644 index 0000000000..63c6b0754b --- /dev/null +++ b/arch/arm/mach-mxs/speed-imx28.c @@ -0,0 +1,392 @@ +/* + * (C) Copyright 2010 Juergen Beisert - Pengutronix <kernel@pengutronix.de> + * + * This code is based partially on code that has: + * + * (c) 2008 Embedded Alley Solutions, Inc. + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <common.h> +#include <init.h> +#include <asm/io.h> +#include <mach/imx-regs.h> +#include <mach/generic.h> +#include <mach/clock.h> + +#define HW_CLKCTRL_PLL0CTRL0 0x000 +#define HW_CLKCTRL_PLL0CTRL1 0x010 +#define HW_CLKCTRL_PLL1CTRL0 0x020 +#define HW_CLKCTRL_PLL1CTRL1 0x030 +#define HW_CLKCTRL_PLL2CTRL0 0x040 +# define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) +# define CLKCTRL_PLL2CTRL0_POWER (1 << 23) +#define HW_CLKCTRL_CPU 0x50 +# define GET_CPU_XTAL_DIV(x) (((x) >> 16) & 0x3ff) +# define GET_CPU_PLL_DIV(x) ((x) & 0x3f) +#define HW_CLKCTRL_HBUS 0x60 +#define HW_CLKCTRL_XBUS 0x70 +#define HW_CLKCTRL_XTAL 0x080 +#define HW_CLKCTRL_SSP0 0x090 +#define HW_CLKCTRL_SSP1 0x0a0 +#define HW_CLKCTRL_SSP2 0x0b0 +#define HW_CLKCTRL_SSP3 0x0c0 +/* note: no set/clear register! */ +# define CLKCTRL_SSP_CLKGATE (1 << 31) +# define CLKCTRL_SSP_BUSY (1 << 29) +# define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) +# define CLKCTRL_SSP_DIV_MASK 0x1ff +# define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) +# define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) +#define HW_CLKCTRL_GPMI 0x0d0 +/* note: no set/clear register! */ +#define HW_CLKCTRL_SPDIF 0x0e0 +/* note: no set/clear register! */ +#define HW_CLKCTRL_EMI 0xf0 +/* note: no set/clear register! */ +# define CLKCTRL_EMI_CLKGATE (1 << 31) +# define GET_EMI_XTAL_DIV(x) (((x) >> 8) & 0xf) +# define GET_EMI_PLL_DIV(x) ((x) & 0x3f) +#define HW_CLKCTRL_SAIF0 0x100 +#define HW_CLKCTRL_SAIF1 0x110 +#define HW_CLKCTRL_DIS_LCDIF 0x120 +# define CLKCTRL_DIS_LCDIF_GATE (1 << 31) +# define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) +# define SET_DIS_LCDIF_DIV(x) ((x) & 0x1fff) +# define GET_DIS_LCDIF_DIV(x) ((x) & 0x1fff) +#define HW_CLKCTRL_ETM 0x130 +#define HW_CLKCTRL_ENET 0x140 +# define SET_CLKCTRL_ENET_DIV(x) (((x) & 0x3f) << 21) +# define SET_CLKCTRL_ENET_SEL(x) (((x) & 0x3) << 19) +# define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) +#define HW_CLKCTRL_HSADC 0x150 +#define HW_CLKCTRL_FLEXCAN 0x160 +#define HW_CLKCTRL_FRAC0 0x1b0 +# define CLKCTRL_FRAC_CLKGATEIO0 (1 << 31) +# define GET_IO0FRAC(x) (((x) >> 24) & 0x3f) +# define SET_IO0FRAC(x) (((x) & 0x3f) << 24) +# define CLKCTRL_FRAC_CLKGATEIO1 (1 << 23) +# define GET_IO1FRAC(x) (((x) >> 16) & 0x3f) +# define SET_IO1FRAC(x) (((x) & 0x3f) << 16) +# define CLKCTRL_FRAC_CLKGATEEMI (1 << 15) +# define GET_EMIFRAC(x) (((x) >> 8) & 0x3f) +# define CLKCTRL_FRAC_CLKGATECPU (1 << 7) +# define GET_CPUFRAC(x) ((x) & 0x3f) +#define HW_CLKCTRL_FRAC1 0x1c0 +# define CLKCTRL_FRAC_CLKGATEGPMI (1 << 23) +# define GET_GPMIFRAC(x) (((x) >> 16) & 0x3f) +# define CLKCTRL_FRAC_CLKGATEHSADC (1 << 15) +# define GET_HSADCFRAC(x) (((x) >> 8) & 0x3f) +# define CLKCTRL_FRAC_CLKGATEPIX (1 << 7) +# define GET_PIXFRAC(x) ((x) & 0x3f) +# define SET_PIXFRAC(x) ((x) & 0x3f) +#define HW_CLKCTRL_CLKSEQ 0x1d0 +# define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) +# define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) +# define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) +# define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) +# define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) +# define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) +# define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) +# define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) +# define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) +# define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) +# define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) +#define HW_CLKCTRL_RESET 0x1e0 +#define HW_CLKCTRL_STATUS 0x1f0 +#define HW_CLKCTRL_VERSION 0x200 + +unsigned imx_get_mpllclk(void) +{ + /* the main PLL runs at 480 MHz */ + return 480000000; +} + +unsigned imx_get_xtalclk(void) +{ + /* the external reference runs at 24 MHz */ + return 24000000; +} + +unsigned imx_get_fecclk(void) +{ + /* this PLL always runs at 50 MHz */ + return 50000000; +} + + +/* used for the SDRAM controller */ +unsigned imx_get_emiclk(void) +{ + uint32_t reg; + unsigned rate; + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_EMI) & CLKCTRL_EMI_CLKGATE) + return 0; /* clock is off */ + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_EMI) + return imx_get_xtalclk() / + GET_EMI_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI)); + + rate = imx_get_mpllclk() / 1000; + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0); + if (!(reg & CLKCTRL_FRAC_CLKGATEEMI)) { + rate *= 18; + rate /= GET_EMIFRAC(reg); + } + + return (rate / GET_EMI_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI))) + * 1000; +} + +/* + * Source of ssp, gpmi, ir + * @param index 0 or 1 for ioclk0 or ioclock1 + */ +unsigned imx_get_ioclk(unsigned index) +{ + uint32_t reg; + unsigned rate = imx_get_mpllclk() / 1000; + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0); + switch (index) { + case 0: + if (reg & CLKCTRL_FRAC_CLKGATEIO0) + return 0; /* clock is off */ + + rate *= 18; + rate /= GET_IO0FRAC(reg); + break; + case 1: + if (reg & CLKCTRL_FRAC_CLKGATEIO1) + return 0; /* clock is off */ + + rate *= 18; + rate /= GET_IO1FRAC(reg); + break; + } + + return rate * 1000; +} + +/** + * Setup a new frequency to the IOCLK domain. + * @param index 0 or 1 for ioclk0 or ioclock1 + * @param nc New frequency in [Hz] + * + * The FRAC divider for the IOCLK must be between 18 (* 18/18) and 35 (* 18/35) + * + * ioclock0 is the shared clock source of SSP0/SSP1, ioclock1 the shared clock + * source of SSP2/SSP3 + */ +unsigned imx_set_ioclk(unsigned index, unsigned nc) +{ + uint32_t reg; + unsigned div; + + nc /= 1000; + div = (imx_get_mpllclk() / 1000) * 18; + div = DIV_ROUND_CLOSEST(div, nc); + if (div > 0x3f) + div = 0x3f; + + switch (index) { + case 0: + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0) & + ~(SET_IO0FRAC(0x3f)); + /* mask the current settings */ + writel(reg | SET_IO0FRAC(div), IMX_CCM_BASE + HW_CLKCTRL_FRAC0); + /* enable the IO clock at its new frequency */ + writel(CLKCTRL_FRAC_CLKGATEIO0, + IMX_CCM_BASE + HW_CLKCTRL_FRAC0 + BIT_CLR); + break; + case 1: + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0) & + ~(SET_IO1FRAC(0x3f)); + /* mask the current settings */ + writel(reg | SET_IO1FRAC(div), IMX_CCM_BASE + HW_CLKCTRL_FRAC0); + /* enable the IO clock at its new frequency */ + writel(CLKCTRL_FRAC_CLKGATEIO1, + IMX_CCM_BASE + HW_CLKCTRL_FRAC0 + BIT_CLR); + break; + } + + return imx_get_ioclk(index); +} + +/* this is CPU core clock */ +unsigned imx_get_armclk(void) +{ + uint32_t reg; + unsigned rate; + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_CPU) + return imx_get_xtalclk() / + GET_CPU_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU)); + + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0); + if (reg & CLKCTRL_FRAC_CLKGATECPU) + return 0; /* should not possible, shouldn't it? */ + + rate = (imx_get_mpllclk() / 1000) * 18; + rate /= GET_CPUFRAC(reg); + + return (rate / GET_CPU_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU))) + * 1000; +} + +/* this is the AHB and APBH bus clock */ +unsigned imx_get_hclk(void) +{ + unsigned rate = imx_get_armclk() / 1000; + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x20) { + rate *= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; + rate /= 32; + } else + rate /= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; + return rate * 1000; +} + +/* + * Source of UART, debug UART, audio, PWM, dri, timer, digctl + */ +unsigned imx_get_xclk(void) +{ + /* runs from the 24 MHz crystal reference */ + unsigned rate = imx_get_xtalclk(); + + return rate / (readl(IMX_CCM_BASE + HW_CLKCTRL_XBUS) & 0x3ff); +} + +/** + * @param index The SSP unit (0...3) + */ +unsigned imx_get_sspclk(unsigned index) +{ + unsigned rate, offset, shift, ioclk_index; + + if (index > 3) { + pr_debug("Unknown SSP unit: %u\n", index); + return 0; + } + + ioclk_index = index >> 1; + + offset = HW_CLKCTRL_SSP0 + (0x10 * index); + shift = CLKCTRL_CLKSEQ_BYPASS_SSP0 << index; + + if (readl(IMX_CCM_BASE + offset) & CLKCTRL_SSP_CLKGATE) + return 0; /* clock is off */ + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & shift) + rate = imx_get_xtalclk(); + else + rate = imx_get_ioclk(ioclk_index); + + return rate / GET_SSP_DIV(readl(IMX_CCM_BASE + offset)); +} + +/** + * @param index The SSP unit (0...3) + * @param nc New frequency in [Hz] + * @param high != 0 if ioclk should be the source + * @return The new possible frequency + */ +unsigned imx_set_sspclk(unsigned index, unsigned nc, int high) +{ + uint32_t reg; + unsigned ssp_div, offset, shift, ioclk_index; + + if (index > 3) { + pr_debug("Unknown SSP unit: %u\n", index); + return 0; + } + + ioclk_index = index >> 1; + + offset = HW_CLKCTRL_SSP0 + (0x10 * index); + shift = CLKCTRL_CLKSEQ_BYPASS_SSP0 << index; + + reg = readl(IMX_CCM_BASE + offset) & ~CLKCTRL_SSP_CLKGATE; + /* Datasheet says: Do not change the DIV setting if the clock is off */ + writel(reg, IMX_CCM_BASE + offset); + /* Wait while clock is gated */ + while (readl(IMX_CCM_BASE + offset) & CLKCTRL_SSP_CLKGATE) + ; + + if (high) + ssp_div = imx_get_ioclk(ioclk_index); + else + ssp_div = imx_get_xtalclk(); + + if (nc > ssp_div) { + printf("Cannot setup SSP unit clock to %u kHz, base clock is " + "only %u kHz\n", nc, ssp_div); + ssp_div = 1; + } else { + ssp_div = DIV_ROUND_UP(ssp_div, nc); + if (ssp_div > CLKCTRL_SSP_DIV_MASK) + ssp_div = CLKCTRL_SSP_DIV_MASK; + } + + /* Set new divider value */ + reg = readl(IMX_CCM_BASE + offset) & ~CLKCTRL_SSP_DIV_MASK; + writel(reg | SET_SSP_DIV(ssp_div), IMX_CCM_BASE + offset); + + /* Wait until new divider value is set */ + while (readl(IMX_CCM_BASE + offset) & CLKCTRL_SSP_BUSY) + ; + + if (high) + /* switch to ioclock */ + writel(shift, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + BIT_CLR); + else + /* switch to 24 MHz crystal */ + writel(shift, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + BIT_SET); + + return imx_get_sspclk(index); +} + +void imx_enable_enetclk(void) +{ + uint32_t reg; + + /* wake up main enet PLL */ + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_PLL2CTRL0); + if (!(reg & CLKCTRL_PLL2CTRL0_POWER)) { + reg |= CLKCTRL_PLL2CTRL0_POWER; + writel(reg, IMX_CCM_BASE + HW_CLKCTRL_PLL2CTRL0); + udelay(50); /* wait until this PLL locks */ + } + reg &= ~CLKCTRL_PLL2CTRL0_CLKGATE; + writel(reg, IMX_CCM_BASE + HW_CLKCTRL_PLL2CTRL0); + + writel(SET_CLKCTRL_ENET_DIV(1) | SET_CLKCTRL_ENET_SEL(0) | + CLKCTRL_ENET_CLK_OUT_EN, /* FIXME may be platform specific */ + IMX_CCM_BASE + HW_CLKCTRL_ENET); +} + +void imx_dump_clocks(void) +{ + printf("mpll: %10u kHz\n", imx_get_mpllclk() / 1000); + printf("arm: %10u kHz\n", imx_get_armclk() / 1000); + printf("ioclk0: %10u kHz\n", imx_get_ioclk(0) / 1000); + printf("ioclk1: %10u kHz\n", imx_get_ioclk(1) / 1000); + printf("emiclk: %10u kHz\n", imx_get_emiclk() / 1000); + printf("hclk: %10u kHz\n", imx_get_hclk() / 1000); + printf("xclk: %10u kHz\n", imx_get_xclk() / 1000); + printf("ssp0: %10u kHz\n", imx_get_sspclk(0) / 1000); + printf("ssp1: %10u kHz\n", imx_get_sspclk(1) / 1000); + printf("ssp2: %10u kHz\n", imx_get_sspclk(2) / 1000); + printf("ssp3: %10u kHz\n", imx_get_sspclk(3) / 1000); +} diff --git a/arch/arm/mach-mxs/usb.c b/arch/arm/mach-mxs/usb.c new file mode 100644 index 0000000000..d232bb6075 --- /dev/null +++ b/arch/arm/mach-mxs/usb.c @@ -0,0 +1,92 @@ +/* + * i.MX23/28 USBPHY setup + * + * Copyright 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <mach/imx-regs.h> + +#define POWER_CTRL (IMX_POWER_BASE + 0x0) +#define POWER_CTRL_CLKGATE 0x40000000 + +#define POWER_STS (IMX_POWER_BASE + 0xc0) +#define POWER_STS_VBUSVALID 0x00000002 +#define POWER_STS_BVALID 0x00000004 +#define POWER_STS_AVALID 0x00000008 + +#define POWER_DEBUG (IMX_POWER_BASE + 0x110) +#define POWER_DEBUG_BVALIDPIOLOCK 0x00000002 +#define POWER_DEBUG_AVALIDPIOLOCK 0x00000004 +#define POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 + +#define USBPHY_PWD (IMX_USBPHY_BASE + 0x0) + +#define USBPHY_CTRL (IMX_USBPHY_BASE + 0x30) +#define USBPHY_CTRL_SFTRST 0x80000000 +#define USBPHY_CTRL_CLKGATE 0x40000000 + +#define CLK_PLLCTRL0 (IMX_CCM_BASE + 0x0) +#define PLLCTRL0_EN_USB_CLKS 0x00040000 + +#define DIGCTRL_CTRL (IMX_DIGCTL_BASE + 0x0) +#define DIGCTL_CTRL_USB_CLKGATE 0x00000004 + +#define SET 0x4 +#define CLR 0x8 + +int imx_usb_phy_enable(void) +{ + u32 reg; + + /* + * Set these bits so that we can force the OTG bits high + * so the ARC core operates properly + */ + writel(POWER_CTRL_CLKGATE, POWER_CTRL + CLR); + + writel(POWER_DEBUG_VBUSVALIDPIOLOCK | + POWER_DEBUG_AVALIDPIOLOCK | + POWER_DEBUG_BVALIDPIOLOCK, POWER_DEBUG + SET); + + reg = readl(POWER_STS); + reg |= POWER_STS_BVALID | POWER_STS_AVALID | POWER_STS_VBUSVALID; + writel(reg, POWER_STS); + + /* Reset USBPHY module */ + writel(USBPHY_CTRL_SFTRST, USBPHY_CTRL + SET); + udelay(10); + + /* Remove CLKGATE and SFTRST */ + writel(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST, USBPHY_CTRL + CLR); + + /* Turn on the USB clocks */ + writel(PLLCTRL0_EN_USB_CLKS, CLK_PLLCTRL0 + SET); + writel(DIGCTL_CTRL_USB_CLKGATE, DIGCTRL_CTRL + CLR); + + /* Power up the PHY */ + writel(0, USBPHY_PWD); + + /* + * Set precharge bit to cure overshoot problems at the + * start of packets + */ + writel(1, USBPHY_CTRL + SET); + + return 0; +} + |