diff options
Diffstat (limited to 'arch/arm/mach-pxa/include/mach')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/clock.h | 16 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/devices.h | 26 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/gpio.h | 132 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/hardware.h | 31 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/mfp-pxa27x.h | 438 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h | 133 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/mfp.h | 21 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/pxa-regs.h | 33 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/pxa27x-regs.h | 6 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/pxa2xx-regs.h | 267 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/regs-intc.h | 34 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/regs-ost.h | 34 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/udc_pxa2xx.h | 26 |
13 files changed, 1197 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/clock.h b/arch/arm/mach-pxa/include/mach/clock.h new file mode 100644 index 0000000000..cd0ab8ea3f --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/clock.h @@ -0,0 +1,16 @@ + +/* + * clock.h - definitions of the PXA clock functions + * + * Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#ifndef __MACH_CLOCK_H +#define __MACH_CLOCK_H + +unsigned long pxa_get_uartclk(void); + +#endif /* !__MACH_CLOCK_H */ diff --git a/arch/arm/mach-pxa/include/mach/devices.h b/arch/arm/mach-pxa/include/mach/devices.h new file mode 100644 index 0000000000..e205b7c7f2 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/devices.h @@ -0,0 +1,26 @@ +/* + * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <i2c/i2c.h> +#include <mach/pxafb.h> + +struct device_d *pxa_add_i2c(void *base, int id, + struct i2c_platform_data *pdata); +struct device_d *pxa_add_uart(void *base, int id); +struct device_d *pxa_add_fb(void *base, struct pxafb_platform_data *pdata); +struct device_d *pxa_add_mmc(void *base, int id, void *pdata); + diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h new file mode 100644 index 0000000000..e6724e1caf --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/gpio.h @@ -0,0 +1,132 @@ +/* + * arch/arm/mach-pxa/include/mach/gpio.h + * + * PXA GPIO wrappers for arch-neutral GPIO calls + * + * Written by Philipp Zabel <philipp.zabel@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_PXA_GPIO_H +#define __ASM_ARCH_PXA_GPIO_H + +#include <mach/hardware.h> + +#define GPIO_REGS_VIRT (0x40E00000) + +#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) +#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x))) + +/* GPIO Pin Level Registers */ +#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00) +#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00) +#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00) +#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00) + +/* GPIO Pin Direction Registers */ +#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c) +#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c) +#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c) +#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c) + +/* GPIO Pin Output Set Registers */ +#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18) +#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18) +#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18) +#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18) + +/* GPIO Pin Output Clear Registers */ +#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24) +#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24) +#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24) +#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24) + +/* GPIO Rising Edge Detect Registers */ +#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30) +#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30) +#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30) +#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30) + +/* GPIO Falling Edge Detect Registers */ +#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c) +#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c) +#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c) +#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c) + +/* GPIO Edge Detect Status Registers */ +#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48) +#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48) +#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48) +#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48) + +/* GPIO Alternate Function Select Registers */ +#define GAFR0_L GPIO_REG(0x0054) +#define GAFR0_U GPIO_REG(0x0058) +#define GAFR1_L GPIO_REG(0x005C) +#define GAFR1_U GPIO_REG(0x0060) +#define GAFR2_L GPIO_REG(0x0064) +#define GAFR2_U GPIO_REG(0x0068) +#define GAFR3_L GPIO_REG(0x006C) +#define GAFR3_U GPIO_REG(0x0070) + +/* More handy macros. The argument is a literal GPIO number. */ + +#define GPIO_bit(x) (1 << ((x) & 0x1f)) + +#define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00) +#define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c) +#define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18) +#define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24) +#define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30) +#define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c) +#define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48) +#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) + + +#define NR_BUILTIN_GPIO 128 + +#define gpio_to_bank(gpio) ((gpio) >> 5) + +#ifdef CONFIG_CPU_PXA26x +/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, + * as well as their Alternate Function value being '1' for GPIO in GAFRx. + */ +static inline int __gpio_is_inverted(unsigned gpio) +{ + return cpu_is_pxa25x() && gpio > 85; +} +#else +static inline int __gpio_is_inverted(unsigned gpio) { return 0; } +#endif + +/* + * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate + * function of a GPIO, and GPDRx cannot be altered once configured. It + * is attributed as "occupied" here (I know this terminology isn't + * accurate, you are welcome to propose a better one :-) + */ +static inline int __gpio_is_occupied(unsigned gpio) +{ + if (cpu_is_pxa27x() || cpu_is_pxa25x()) { + int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; + int dir = GPDR(gpio) & GPIO_bit(gpio); + + if (__gpio_is_inverted(gpio)) + return af != 1 || dir == 0; + else + return af != 0 || dir != 0; + } else + return GPDR(gpio) & GPIO_bit(gpio); +} +#include <plat/gpio.h> +#endif diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h new file mode 100644 index 0000000000..e53085cdde --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -0,0 +1,31 @@ +/* + * (c) 2010 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H + +#ifdef CONFIG_ARCH_PXA2XX +#define cpu_is_pxa2xx() (1) +#else +#define cpi_is_pxa2xx() (0) +#endif + +#ifdef CONFIG_ARCH_PXA25X +#define cpu_is_pxa25x() (1) +#else +#define cpu_is_pxa25x() (0) +#endif + +#ifdef CONFIG_ARCH_PXA27X +#define cpu_is_pxa27x() (1) +#else +#define cpu_is_pxa27x() (0) +#endif + +#endif /* !__MACH_HARDWARE_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h new file mode 100644 index 0000000000..6543c05f47 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h @@ -0,0 +1,438 @@ +#ifndef __ASM_ARCH_MFP_PXA27X_H +#define __ASM_ARCH_MFP_PXA27X_H + +/* + * NOTE: for those special-function bidirectional GPIOs, as described + * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input + * alternative is preserved, the direction is actually selected by the + * specific controller, and this should work in most cases. + */ + +#include <mach/mfp-pxa2xx.h> + +/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN + * bit is set, regardless of the GPIO configuration + */ +#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) + +/* GPIO */ +#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) +#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF0) +#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF0) +#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF0) +#define GPIO90_GPIO MFP_CFG_IN(GPIO90, AF0) +#define GPIO91_GPIO MFP_CFG_IN(GPIO91, AF0) +#define GPIO92_GPIO MFP_CFG_IN(GPIO92, AF0) +#define GPIO93_GPIO MFP_CFG_IN(GPIO93, AF0) +#define GPIO94_GPIO MFP_CFG_IN(GPIO94, AF0) +#define GPIO95_GPIO MFP_CFG_IN(GPIO95, AF0) +#define GPIO96_GPIO MFP_CFG_IN(GPIO96, AF0) +#define GPIO97_GPIO MFP_CFG_IN(GPIO97, AF0) +#define GPIO98_GPIO MFP_CFG_IN(GPIO98, AF0) +#define GPIO99_GPIO MFP_CFG_IN(GPIO99, AF0) +#define GPIO100_GPIO MFP_CFG_IN(GPIO100, AF0) +#define GPIO101_GPIO MFP_CFG_IN(GPIO101, AF0) +#define GPIO102_GPIO MFP_CFG_IN(GPIO102, AF0) +#define GPIO103_GPIO MFP_CFG_IN(GPIO103, AF0) +#define GPIO104_GPIO MFP_CFG_IN(GPIO104, AF0) +#define GPIO105_GPIO MFP_CFG_IN(GPIO105, AF0) +#define GPIO106_GPIO MFP_CFG_IN(GPIO106, AF0) +#define GPIO107_GPIO MFP_CFG_IN(GPIO107, AF0) +#define GPIO108_GPIO MFP_CFG_IN(GPIO108, AF0) +#define GPIO109_GPIO MFP_CFG_IN(GPIO109, AF0) +#define GPIO110_GPIO MFP_CFG_IN(GPIO110, AF0) +#define GPIO111_GPIO MFP_CFG_IN(GPIO111, AF0) +#define GPIO112_GPIO MFP_CFG_IN(GPIO112, AF0) +#define GPIO113_GPIO MFP_CFG_IN(GPIO113, AF0) +#define GPIO114_GPIO MFP_CFG_IN(GPIO114, AF0) +#define GPIO115_GPIO MFP_CFG_IN(GPIO115, AF0) +#define GPIO116_GPIO MFP_CFG_IN(GPIO116, AF0) +#define GPIO117_GPIO MFP_CFG_IN(GPIO117, AF0) +#define GPIO118_GPIO MFP_CFG_IN(GPIO118, AF0) +#define GPIO119_GPIO MFP_CFG_IN(GPIO119, AF0) +#define GPIO120_GPIO MFP_CFG_IN(GPIO120, AF0) + +/* Crystal and Clock Signals */ +#define GPIO9_HZ_CLK MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) +#define GPIO10_HZ_CLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) +#define GPIO11_48_MHz MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW) +#define GPIO12_48_MHz MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW) +#define GPIO13_CLK_EXT MFP_CFG_IN(GPIO13, AF1) + +/* OS Timer Signals */ +#define GPIO11_EXT_SYNC_0 MFP_CFG_IN(GPIO11, AF1) +#define GPIO12_EXT_SYNC_1 MFP_CFG_IN(GPIO12, AF1) +#define GPIO9_CHOUT_0 MFP_CFG_OUT(GPIO9, AF3, DRIVE_LOW) +#define GPIO10_CHOUT_1 MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW) +#define GPIO11_CHOUT_0 MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) +#define GPIO12_CHOUT_1 MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) + +/* SDRAM and Static Memory I/O Signals */ +#define GPIO20_nSDCS_2 MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH) +#define GPIO21_nSDCS_3 MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH) +#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) +#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) +#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) +#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) +#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) + +/* Miscellaneous I/O and DMA Signals */ +#define GPIO21_DVAL_0 MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH) +#define GPIO116_DVAL_0 MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH) +#define GPIO33_DVAL_1 MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH) +#define GPIO96_DVAL_1 MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH) +#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) +#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) +#define GPIO115_DREQ_0 MFP_CFG_IN(GPIO115, AF1) +#define GPIO80_DREQ_1 MFP_CFG_IN(GPIO80, AF1) +#define GPIO97_DREQ_1 MFP_CFG_IN(GPIO97, AF2) +#define GPIO85_DREQ_2 MFP_CFG_IN(GPIO85, AF2) +#define GPIO100_DREQ_2 MFP_CFG_IN(GPIO100, AF2) + +/* Alternate Bus Master Mode I/O Signals */ +#define GPIO20_MBREQ MFP_CFG_IN(GPIO20, AF2) +#define GPIO80_MBREQ MFP_CFG_IN(GPIO80, AF2) +#define GPIO96_MBREQ MFP_CFG_IN(GPIO96, AF2) +#define GPIO115_MBREQ MFP_CFG_IN(GPIO115, AF3) +#define GPIO21_MBGNT MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW) +#define GPIO33_MBGNT MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW) +#define GPIO97_MBGNT MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW) +#define GPIO116_MBGNT MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW) + +/* PC CARD */ +#define GPIO15_nPCE_1 MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH) +#define GPIO85_nPCE_1 MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH) +#define GPIO86_nPCE_1 MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH) +#define GPIO102_nPCE_1 MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH) +#define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) +#define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH) +#define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1) +#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) +#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) +#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) +#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) +#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) +#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) +#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) +#define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH) +#define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH) + +/* I2C */ +#define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1) +#define GPIO118_I2C_SDA MFP_CFG_IN(GPIO118, AF1) + +/* FFUART */ +#define GPIO9_FFUART_CTS MFP_CFG_IN(GPIO9, AF3) +#define GPIO26_FFUART_CTS MFP_CFG_IN(GPIO26, AF3) +#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) +#define GPIO100_FFUART_CTS MFP_CFG_IN(GPIO100, AF3) +#define GPIO10_FFUART_DCD MFP_CFG_IN(GPIO10, AF1) +#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) +#define GPIO33_FFUART_DSR MFP_CFG_IN(GPIO33, AF2) +#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) +#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) +#define GPIO89_FFUART_RI MFP_CFG_IN(GPIO89, AF3) +#define GPIO19_FFUART_RXD MFP_CFG_IN(GPIO19, AF3) +#define GPIO33_FFUART_RXD MFP_CFG_IN(GPIO33, AF1) +#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) +#define GPIO41_FFUART_RXD MFP_CFG_IN(GPIO41, AF1) +#define GPIO53_FFUART_RXD MFP_CFG_IN(GPIO53, AF1) +#define GPIO85_FFUART_RXD MFP_CFG_IN(GPIO85, AF1) +#define GPIO96_FFUART_RXD MFP_CFG_IN(GPIO96, AF3) +#define GPIO102_FFUART_RXD MFP_CFG_IN(GPIO102, AF3) +#define GPIO16_FFUART_TXD MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH) +#define GPIO37_FFUART_TXD MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH) +#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) +#define GPIO83_FFUART_TXD MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH) +#define GPIO99_FFUART_TXD MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH) +#define GPIO27_FFUART_RTS MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH) +#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) +#define GPIO83_FFUART_RTS MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH) +#define GPIO98_FFUART_RTS MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH) +#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) +#define GPIO82_FFUART_DTR MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH) + +/* BTUART */ +#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) +#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) +#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) +#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) + +/* STUART */ +#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) +#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) + +/* FICP */ +#define GPIO42_FICP_RXD MFP_CFG_IN(GPIO42, AF2) +#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) +#define GPIO43_FICP_TXD MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH) +#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) + +/* PWM 0/1/2/3 */ +#define GPIO11_PWM2_OUT MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW) +#define GPIO12_PWM3_OUT MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW) +#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) +#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) +#define GPIO38_PWM1_OUT MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW) +#define GPIO46_PWM2_OUT MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW) +#define GPIO47_PWM3_OUT MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW) +#define GPIO79_PWM2_OUT MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW) +#define GPIO80_PWM3_OUT MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW) +#define GPIO115_PWM1_OUT MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW) + +/* AC97 */ +#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) +#define GPIO94_AC97_SYNC MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW) +#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) +#define GPIO93_AC97_SDATA_OUT MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW) +#define GPIO45_AC97_SYSCLK MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW) +#define GPIO89_AC97_SYSCLK MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW) +#define GPIO98_AC97_SYSCLK MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW) +#define GPIO95_AC97_nRESET MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW) +#define GPIO113_AC97_nRESET MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW) +#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) +#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) +#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2) +#define GPIO99_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO99, AF2) + +/* I2S */ +#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) +#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) +#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) +#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) +#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) +#define GPIO113_I2S_SYSCLK MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW) + +/* SSP 1 */ +#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) +#define GPIO29_SSP1_SCLK MFP_CFG_IN(GPIO29, AF3) +#define GPIO27_SSP1_SYSCLK MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW) +#define GPIO53_SSP1_SYSCLK MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW) +#define GPIO24_SSP1_SFRM MFP_CFG_IN(GPIO24, AF2) +#define GPIO28_SSP1_SFRM MFP_CFG_IN(GPIO28, AF3) +#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) +#define GPIO57_SSP1_TXD MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW) +#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) +#define GPIO27_SSP1_SCLKEN MFP_CFG_IN(GPIO27, AF2) + +/* SSP 2 */ +#define GPIO19_SSP2_SCLK MFP_CFG_IN(GPIO19, AF1) +#define GPIO22_SSP2_SCLK MFP_CFG_IN(GPIO22, AF3) +#define GPIO29_SSP2_SCLK MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW) +#define GPIO36_SSP2_SCLK MFP_CFG_IN(GPIO36, AF2) +#define GPIO50_SSP2_SCLK MFP_CFG_IN(GPIO50, AF3) +#define GPIO22_SSP2_SYSCLK MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW) +#define GPIO14_SSP2_SFRM MFP_CFG_IN(GPIO14, AF2) +#define GPIO37_SSP2_SFRM MFP_CFG_IN(GPIO37, AF2) +#define GPIO87_SSP2_SFRM MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW) +#define GPIO88_SSP2_SFRM MFP_CFG_IN(GPIO88, AF3) +#define GPIO13_SSP2_TXD MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW) +#define GPIO38_SSP2_TXD MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW) +#define GPIO87_SSP2_TXD MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW) +#define GPIO89_SSP2_TXD MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW) +#define GPIO11_SSP2_RXD MFP_CFG_IN(GPIO11, AF2) +#define GPIO29_SSP2_RXD MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW) +#define GPIO40_SSP2_RXD MFP_CFG_IN(GPIO40, AF1) +#define GPIO86_SSP2_RXD MFP_CFG_IN(GPIO86, AF1) +#define GPIO88_SSP2_RXD MFP_CFG_IN(GPIO88, AF2) +#define GPIO22_SSP2_EXTCLK MFP_CFG_IN(GPIO22, AF1) +#define GPIO27_SSP2_EXTCLK MFP_CFG_IN(GPIO27, AF1) +#define GPIO22_SSP2_SCLKEN MFP_CFG_IN(GPIO22, AF2) +#define GPIO23_SSP2_SCLKEN MFP_CFG_IN(GPIO23, AF2) + +/* SSP 3 */ +#define GPIO34_SSP3_SCLK MFP_CFG_IN(GPIO34, AF3) +#define GPIO40_SSP3_SCLK MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW) +#define GPIO52_SSP3_SCLK MFP_CFG_IN(GPIO52, AF2) +#define GPIO84_SSP3_SCLK MFP_CFG_IN(GPIO84, AF1) +#define GPIO45_SSP3_SYSCLK MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW) +#define GPIO35_SSP3_SFRM MFP_CFG_IN(GPIO35, AF3) +#define GPIO39_SSP3_SFRM MFP_CFG_IN(GPIO39, AF3) +#define GPIO83_SSP3_SFRM MFP_CFG_IN(GPIO83, AF1) +#define GPIO35_SSP3_TXD MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW) +#define GPIO38_SSP3_TXD MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW) +#define GPIO81_SSP3_TXD MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) +#define GPIO41_SSP3_RXD MFP_CFG_IN(GPIO41, AF3) +#define GPIO82_SSP3_RXD MFP_CFG_IN(GPIO82, AF1) +#define GPIO89_SSP3_RXD MFP_CFG_IN(GPIO89, AF1) + +/* MMC */ +#define GPIO32_MMC_CLK MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW) +#define GPIO92_MMC_DAT_0 MFP_CFG_IN(GPIO92, AF1) +#define GPIO109_MMC_DAT_1 MFP_CFG_IN(GPIO109, AF1) +#define GPIO110_MMC_DAT_2 MFP_CFG_IN(GPIO110, AF1) +#define GPIO111_MMC_DAT_3 MFP_CFG_IN(GPIO111, AF1) +#define GPIO112_MMC_CMD MFP_CFG_IN(GPIO112, AF1) + +/* LCD */ +#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) +#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) +#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) +#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) +#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) +#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) +#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) +#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) +#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) +#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) +#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) +#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) +#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) +#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) +#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) +#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) +#define GPIO86_LCD_LDD_16 MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW) +#define GPIO87_LCD_LDD_17 MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW) +#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) +#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) +#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) +#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) +#define GPIO14_LCD_VSYNC MFP_CFG_IN(GPIO14, AF1) +#define GPIO19_LCD_CS MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW) + +/* Keypad */ +#define GPIO93_KP_DKIN_0 MFP_CFG_IN(GPIO93, AF1) +#define GPIO94_KP_DKIN_1 MFP_CFG_IN(GPIO94, AF1) +#define GPIO95_KP_DKIN_2 MFP_CFG_IN(GPIO95, AF1) +#define GPIO96_KP_DKIN_3 MFP_CFG_IN(GPIO96, AF1) +#define GPIO97_KP_DKIN_4 MFP_CFG_IN(GPIO97, AF1) +#define GPIO98_KP_DKIN_5 MFP_CFG_IN(GPIO98, AF1) +#define GPIO99_KP_DKIN_6 MFP_CFG_IN(GPIO99, AF1) +#define GPIO13_KP_KDIN_7 MFP_CFG_IN(GPIO13, AF2) +#define GPIO100_KP_MKIN_0 MFP_CFG_IN(GPIO100, AF1) +#define GPIO101_KP_MKIN_1 MFP_CFG_IN(GPIO101, AF1) +#define GPIO102_KP_MKIN_2 MFP_CFG_IN(GPIO102, AF1) +#define GPIO34_KP_MKIN_3 MFP_CFG_IN(GPIO34, AF2) +#define GPIO37_KP_MKIN_3 MFP_CFG_IN(GPIO37, AF3) +#define GPIO97_KP_MKIN_3 MFP_CFG_IN(GPIO97, AF3) +#define GPIO98_KP_MKIN_4 MFP_CFG_IN(GPIO98, AF3) +#define GPIO38_KP_MKIN_4 MFP_CFG_IN(GPIO38, AF2) +#define GPIO39_KP_MKIN_4 MFP_CFG_IN(GPIO39, AF1) +#define GPIO16_KP_MKIN_5 MFP_CFG_IN(GPIO16, AF1) +#define GPIO90_KP_MKIN_5 MFP_CFG_IN(GPIO90, AF1) +#define GPIO99_KP_MKIN_5 MFP_CFG_IN(GPIO99, AF3) +#define GPIO17_KP_MKIN_6 MFP_CFG_IN(GPIO17, AF1) +#define GPIO91_KP_MKIN_6 MFP_CFG_IN(GPIO91, AF1) +#define GPIO95_KP_MKIN_6 MFP_CFG_IN(GPIO95, AF3) +#define GPIO13_KP_MKIN_7 MFP_CFG_IN(GPIO13, AF3) +#define GPIO36_KP_MKIN_7 MFP_CFG_IN(GPIO36, AF3) +#define GPIO103_KP_MKOUT_0 MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH) +#define GPIO104_KP_MKOUT_1 MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH) +#define GPIO105_KP_MKOUT_2 MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH) +#define GPIO106_KP_MKOUT_3 MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH) +#define GPIO107_KP_MKOUT_4 MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH) +#define GPIO108_KP_MKOUT_5 MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH) +#define GPIO35_KP_MKOUT_6 MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH) +#define GPIO22_KP_MKOUT_7 MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH) +#define GPIO40_KP_MKOUT_6 MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH) +#define GPIO41_KP_MKOUT_7 MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH) +#define GPIO96_KP_MKOUT_6 MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH) + +/* USB P3 */ +#define GPIO10_USB_P3_5 MFP_CFG_IN(GPIO10, AF3) +#define GPIO11_USB_P3_1 MFP_CFG_IN(GPIO11, AF3) +#define GPIO30_USB_P3_2 MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) +#define GPIO31_USB_P3_6 MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) +#define GPIO56_USB_P3_4 MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) +#define GPIO86_USB_P3_5 MFP_CFG_IN(GPIO86, AF3) +#define GPIO87_USB_P3_1 MFP_CFG_IN(GPIO87, AF3) +#define GPIO90_USB_P3_5 MFP_CFG_IN(GPIO90, AF2) +#define GPIO91_USB_P3_1 MFP_CFG_IN(GPIO91, AF2) +#define GPIO113_USB_P3_3 MFP_CFG_IN(GPIO113, AF3) + +/* USB P2 */ +#define GPIO34_USB_P2_2 MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW) +#define GPIO35_USB_P2_1 MFP_CFG_IN(GPIO35, AF2) +#define GPIO36_USB_P2_4 MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW) +#define GPIO37_USB_P2_8 MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW) +#define GPIO38_USB_P2_3 MFP_CFG_IN(GPIO38, AF3) +#define GPIO39_USB_P2_6 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) +#define GPIO40_USB_P2_5 MFP_CFG_IN(GPIO40, AF3) +#define GPIO41_USB_P2_7 MFP_CFG_IN(GPIO41, AF2) +#define GPIO53_USB_P2_3 MFP_CFG_IN(GPIO53, AF2) + +/* USB Host Port 1/2 */ +#define GPIO88_USBH1_PWR MFP_CFG_IN(GPIO88, AF1) +#define GPIO89_USBH1_PEN MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW) +#define GPIO119_USBH2_PWR MFP_CFG_IN(GPIO119, AF1) +#define GPIO120_USBH2_PEN MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW) + +/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */ +#define GPIO115_CIF_DD_3 MFP_CFG_IN(GPIO115, AF2) +#define GPIO116_CIF_DD_2 MFP_CFG_IN(GPIO116, AF1) +#define GPIO12_CIF_DD_7 MFP_CFG_IN(GPIO12, AF2) +#define GPIO17_CIF_DD_6 MFP_CFG_IN(GPIO17, AF2) +#define GPIO23_CIF_MCLK MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW) +#define GPIO24_CIF_FV MFP_CFG_IN(GPIO24, AF1) +#define GPIO25_CIF_LV MFP_CFG_IN(GPIO25, AF1) +#define GPIO26_CIF_PCLK MFP_CFG_IN(GPIO26, AF2) +#define GPIO27_CIF_DD_0 MFP_CFG_IN(GPIO27, AF3) +#define GPIO42_CIF_MCLK MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW) +#define GPIO43_CIF_FV MFP_CFG_IN(GPIO43, AF3) +#define GPIO44_CIF_LV MFP_CFG_IN(GPIO44, AF3) +#define GPIO45_CIF_PCLK MFP_CFG_IN(GPIO45, AF3) +#define GPIO47_CIF_DD_0 MFP_CFG_IN(GPIO47, AF1) +#define GPIO48_CIF_DD_5 MFP_CFG_IN(GPIO48, AF1) +#define GPIO50_CIF_DD_3 MFP_CFG_IN(GPIO50, AF1) +#define GPIO51_CIF_DD_2 MFP_CFG_IN(GPIO51, AF1) +#define GPIO52_CIF_DD_4 MFP_CFG_IN(GPIO52, AF1) +#define GPIO53_CIF_MCLK MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW) +#define GPIO54_CIF_PCLK MFP_CFG_IN(GPIO54, AF3) +#define GPIO55_CIF_DD_1 MFP_CFG_IN(GPIO55, AF1) +#define GPIO81_CIF_DD_0 MFP_CFG_IN(GPIO81, AF2) +#define GPIO82_CIF_DD_5 MFP_CFG_IN(GPIO82, AF3) +#define GPIO83_CIF_DD_4 MFP_CFG_IN(GPIO83, AF3) +#define GPIO84_CIF_FV MFP_CFG_IN(GPIO84, AF3) +#define GPIO85_CIF_LV MFP_CFG_IN(GPIO85, AF3) +#define GPIO90_CIF_DD_4 MFP_CFG_IN(GPIO90, AF3) +#define GPIO91_CIF_DD_5 MFP_CFG_IN(GPIO91, AF3) +#define GPIO93_CIF_DD_6 MFP_CFG_IN(GPIO93, AF2) +#define GPIO94_CIF_DD_5 MFP_CFG_IN(GPIO94, AF2) +#define GPIO95_CIF_DD_4 MFP_CFG_IN(GPIO95, AF2) +#define GPIO98_CIF_DD_0 MFP_CFG_IN(GPIO98, AF2) +#define GPIO103_CIF_DD_3 MFP_CFG_IN(GPIO103, AF1) +#define GPIO104_CIF_DD_2 MFP_CFG_IN(GPIO104, AF1) +#define GPIO105_CIF_DD_1 MFP_CFG_IN(GPIO105, AF1) +#define GPIO106_CIF_DD_9 MFP_CFG_IN(GPIO106, AF1) +#define GPIO107_CIF_DD_8 MFP_CFG_IN(GPIO107, AF1) +#define GPIO108_CIF_DD_7 MFP_CFG_IN(GPIO108, AF1) +#define GPIO114_CIF_DD_1 MFP_CFG_IN(GPIO114, AF1) + +/* Universal Subscriber ID Interface */ +#define GPIO114_UVS0 MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW) +#define GPIO115_nUVS1 MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW) +#define GPIO116_nUVS2 MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW) +#define GPIO14_UCLK MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW) +#define GPIO91_UCLK MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW) +#define GPIO19_nURST MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW) +#define GPIO90_nURST MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW) +#define GPIO116_UDET MFP_CFG_IN(GPIO116, AF3) +#define GPIO114_UEN MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW) +#define GPIO115_UEN MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW) + +/* Mobile Scalable Link (MSL) Interface */ +#define GPIO81_BB_OB_DAT_0 MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW) +#define GPIO48_BB_OB_DAT_1 MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW) +#define GPIO50_BB_OB_DAT_2 MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW) +#define GPIO51_BB_OB_DAT_3 MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW) +#define GPIO52_BB_OB_CLK MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW) +#define GPIO53_BB_OB_STB MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) +#define GPIO54_BB_OB_WAIT MFP_CFG_IN(GPIO54, AF2) +#define GPIO82_BB_IB_DAT_0 MFP_CFG_IN(GPIO82, AF2) +#define GPIO55_BB_IB_DAT_1 MFP_CFG_IN(GPIO55, AF2) +#define GPIO56_BB_IB_DAT_2 MFP_CFG_IN(GPIO56, AF2) +#define GPIO57_BB_IB_DAT_3 MFP_CFG_IN(GPIO57, AF2) +#define GPIO83_BB_IB_CLK MFP_CFG_IN(GPIO83, AF2) +#define GPIO84_BB_IB_STB MFP_CFG_IN(GPIO84, AF2) +#define GPIO85_BB_IB_WAIT MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW) + +/* Memory Stick Host Controller */ +#define GPIO92_MSBS MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW) +#define GPIO109_MSSDIO MFP_CFG_IN(GPIO109, AF2) +#define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2) +#define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) + +extern int keypad_set_wake(unsigned int on); +#endif /* __ASM_ARCH_MFP_PXA27X_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h new file mode 100644 index 0000000000..658b28ed12 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h @@ -0,0 +1,133 @@ +#ifndef __ASM_ARCH_MFP_PXA2XX_H +#define __ASM_ARCH_MFP_PXA2XX_H + +#include <plat/mfp.h> + +/* + * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: + * + * MFP_PIN(x) + * MFP_AFx + * MFP_LPM_DRIVE_{LOW, HIGH} + * MFP_LPM_EDGE_x + * + * other MFP_x bit definitions will be ignored + * + * and adds the below two bits specifically for pxa2xx: + * + * bit 23 - Input/Output (PXA2xx specific) + * bit 24 - Wakeup Enable(PXA2xx specific) + */ + +#define MFP_DIR_IN (0x0 << 23) +#define MFP_DIR_OUT (0x1 << 23) +#define MFP_DIR_MASK (0x1 << 23) +#define MFP_DIR(x) (((x) >> 23) & 0x1) + +#define MFP_LPM_CAN_WAKEUP (0x1 << 24) +#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) +#define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL) +#define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH) + +/* specifically for enabling wakeup on keypad GPIOs */ +#define WAKEUP_ON_LEVEL_HIGH (MFP_LPM_CAN_WAKEUP) + +#define MFP_CFG_IN(pin, af) \ + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\ + (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN)) + +/* NOTE: pins configured as output _must_ provide a low power state, + * and this state should help to minimize the power dissipation. + */ +#define MFP_CFG_OUT(pin, af, state) \ + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\ + (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) + +/* Common configurations for pxa25x and pxa27x + * + * Note: pins configured as GPIO are always initialized to input + * so not to cause any side effect + */ +#define GPIO0_GPIO MFP_CFG_IN(GPIO0, AF0) +#define GPIO1_GPIO MFP_CFG_IN(GPIO1, AF0) +#define GPIO9_GPIO MFP_CFG_IN(GPIO9, AF0) +#define GPIO10_GPIO MFP_CFG_IN(GPIO10, AF0) +#define GPIO11_GPIO MFP_CFG_IN(GPIO11, AF0) +#define GPIO12_GPIO MFP_CFG_IN(GPIO12, AF0) +#define GPIO13_GPIO MFP_CFG_IN(GPIO13, AF0) +#define GPIO14_GPIO MFP_CFG_IN(GPIO14, AF0) +#define GPIO15_GPIO MFP_CFG_IN(GPIO15, AF0) +#define GPIO16_GPIO MFP_CFG_IN(GPIO16, AF0) +#define GPIO17_GPIO MFP_CFG_IN(GPIO17, AF0) +#define GPIO18_GPIO MFP_CFG_IN(GPIO18, AF0) +#define GPIO19_GPIO MFP_CFG_IN(GPIO19, AF0) +#define GPIO20_GPIO MFP_CFG_IN(GPIO20, AF0) +#define GPIO21_GPIO MFP_CFG_IN(GPIO21, AF0) +#define GPIO22_GPIO MFP_CFG_IN(GPIO22, AF0) +#define GPIO23_GPIO MFP_CFG_IN(GPIO23, AF0) +#define GPIO24_GPIO MFP_CFG_IN(GPIO24, AF0) +#define GPIO25_GPIO MFP_CFG_IN(GPIO25, AF0) +#define GPIO26_GPIO MFP_CFG_IN(GPIO26, AF0) +#define GPIO27_GPIO MFP_CFG_IN(GPIO27, AF0) +#define GPIO28_GPIO MFP_CFG_IN(GPIO28, AF0) +#define GPIO29_GPIO MFP_CFG_IN(GPIO29, AF0) +#define GPIO30_GPIO MFP_CFG_IN(GPIO30, AF0) +#define GPIO31_GPIO MFP_CFG_IN(GPIO31, AF0) +#define GPIO32_GPIO MFP_CFG_IN(GPIO32, AF0) +#define GPIO33_GPIO MFP_CFG_IN(GPIO33, AF0) +#define GPIO34_GPIO MFP_CFG_IN(GPIO34, AF0) +#define GPIO35_GPIO MFP_CFG_IN(GPIO35, AF0) +#define GPIO36_GPIO MFP_CFG_IN(GPIO36, AF0) +#define GPIO37_GPIO MFP_CFG_IN(GPIO37, AF0) +#define GPIO38_GPIO MFP_CFG_IN(GPIO38, AF0) +#define GPIO39_GPIO MFP_CFG_IN(GPIO39, AF0) +#define GPIO40_GPIO MFP_CFG_IN(GPIO40, AF0) +#define GPIO41_GPIO MFP_CFG_IN(GPIO41, AF0) +#define GPIO42_GPIO MFP_CFG_IN(GPIO42, AF0) +#define GPIO43_GPIO MFP_CFG_IN(GPIO43, AF0) +#define GPIO44_GPIO MFP_CFG_IN(GPIO44, AF0) +#define GPIO45_GPIO MFP_CFG_IN(GPIO45, AF0) +#define GPIO46_GPIO MFP_CFG_IN(GPIO46, AF0) +#define GPIO47_GPIO MFP_CFG_IN(GPIO47, AF0) +#define GPIO48_GPIO MFP_CFG_IN(GPIO48, AF0) +#define GPIO49_GPIO MFP_CFG_IN(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG_IN(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG_IN(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG_IN(GPIO52, AF0) +#define GPIO53_GPIO MFP_CFG_IN(GPIO53, AF0) +#define GPIO54_GPIO MFP_CFG_IN(GPIO54, AF0) +#define GPIO55_GPIO MFP_CFG_IN(GPIO55, AF0) +#define GPIO56_GPIO MFP_CFG_IN(GPIO56, AF0) +#define GPIO57_GPIO MFP_CFG_IN(GPIO57, AF0) +#define GPIO58_GPIO MFP_CFG_IN(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG_IN(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG_IN(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG_IN(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG_IN(GPIO62, AF0) +#define GPIO63_GPIO MFP_CFG_IN(GPIO63, AF0) +#define GPIO64_GPIO MFP_CFG_IN(GPIO64, AF0) +#define GPIO65_GPIO MFP_CFG_IN(GPIO65, AF0) +#define GPIO66_GPIO MFP_CFG_IN(GPIO66, AF0) +#define GPIO67_GPIO MFP_CFG_IN(GPIO67, AF0) +#define GPIO68_GPIO MFP_CFG_IN(GPIO68, AF0) +#define GPIO69_GPIO MFP_CFG_IN(GPIO69, AF0) +#define GPIO70_GPIO MFP_CFG_IN(GPIO70, AF0) +#define GPIO71_GPIO MFP_CFG_IN(GPIO71, AF0) +#define GPIO72_GPIO MFP_CFG_IN(GPIO72, AF0) +#define GPIO73_GPIO MFP_CFG_IN(GPIO73, AF0) +#define GPIO74_GPIO MFP_CFG_IN(GPIO74, AF0) +#define GPIO75_GPIO MFP_CFG_IN(GPIO75, AF0) +#define GPIO76_GPIO MFP_CFG_IN(GPIO76, AF0) +#define GPIO77_GPIO MFP_CFG_IN(GPIO77, AF0) +#define GPIO78_GPIO MFP_CFG_IN(GPIO78, AF0) +#define GPIO79_GPIO MFP_CFG_IN(GPIO79, AF0) +#define GPIO80_GPIO MFP_CFG_IN(GPIO80, AF0) +#define GPIO81_GPIO MFP_CFG_IN(GPIO81, AF0) +#define GPIO82_GPIO MFP_CFG_IN(GPIO82, AF0) +#define GPIO83_GPIO MFP_CFG_IN(GPIO83, AF0) +#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0) + +extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num); +extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm); +extern int gpio_set_wake(unsigned int gpio, unsigned int on); +#endif /* __ASM_ARCH_MFP_PXA2XX_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/include/mach/mfp.h new file mode 100644 index 0000000000..271e249ae3 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/mfp.h @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-pxa/include/mach/mfp.h + * + * Multi-Function Pin Definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * + * 2007-8-21: eric miao <eric.miao@marvell.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_H +#define __ASM_ARCH_MFP_H + +#include <plat/mfp.h> + +#endif /* __ASM_ARCH_MFP_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h new file mode 100644 index 0000000000..c32d2ae704 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h @@ -0,0 +1,33 @@ +/* + * (c) 2010 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de> + * + * This file is released under the GPLv2 + * + */ + +#ifndef __MACH_PXA_REGS_H +#define __MACH_PXA_REGS_H + +#ifndef __ASSEMBLY__ +# define __REG(x) (*((volatile u32 *)(x))) +# define __REG16(x) (*(volatile u16 *)(x)) +# define __REG2(x, y) (*(volatile u32 *)((u32)&__REG(x) + (y))) +#else +# define __REG(x) (x) +# define __REG16(x) (x) +# define __REG2(x, y) ((x) + (y)) +#endif + +#ifdef CONFIG_ARCH_PXA2XX +# include <mach/pxa2xx-regs.h> +#endif + +#ifdef CONFIG_ARCH_PXA27X +# include <mach/pxa27x-regs.h> +#else +# error "unknown PXA soc type" +#endif + +#endif /* !__MACH_PXA_REGS_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa27x-regs.h b/arch/arm/mach-pxa/include/mach/pxa27x-regs.h new file mode 100644 index 0000000000..f4d88d47ab --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa27x-regs.h @@ -0,0 +1,6 @@ +#ifndef __MACH_PXA27X_REGS +#define __MACH_PXA27X_REGS + +/* this file intentionally left blank */ + +#endif /* !__MACH_PXA27X_REGS */ diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h new file mode 100644 index 0000000000..4762d8a71e --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -0,0 +1,267 @@ +/* + * arch/arm/mach-pxa/include/mach/pxa2xx-regs.h + * + * Taken from pxa-regs.h by Russell King + * + * Author: Nicolas Pitre + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PXA2XX_REGS_H +#define __PXA2XX_REGS_H + +#include <mach/hardware.h> + +/* + * PXA Chip selects + */ +#define PXA_CS0_PHYS 0x00000000 +#define PXA_CS1_PHYS 0x04000000 +#define PXA_CS2_PHYS 0x08000000 +#define PXA_CS3_PHYS 0x0C000000 +#define PXA_CS4_PHYS 0x10000000 +#define PXA_CS5_PHYS 0x14000000 + +/* + * Memory controller + */ +#define MDCNFG_OFFSET 0x00000000 +#define MDREFR_OFFSET 0x00000004 +#define MSC0_OFFSET 0x00000008 +#define MSC1_OFFSET 0x0000000C +#define MSC2_OFFSET 0x00000010 +#define MECR_OFFSET 0x00000014 +#define SXCNFG_OFFSET 0x0000001C +#define FLYCNFG_OFFSET 0x00000020 +#define MCMEM0_OFFSET 0x00000028 +#define MCMEM1_OFFSET 0x0000002C +#define MCATT0_OFFSET 0x00000030 +#define MCATT1_OFFSET 0x00000034 +#define MCIO0_OFFSET 0x00000038 +#define MCIO1_OFFSET 0x0000003C +#define MDMRS_OFFSET 0x00000040 + +#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ +#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ +#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ +#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ +#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ +#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ +#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ +#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ +#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ +#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ +#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ +#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ +#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ +#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ + +/* + * More handy macros for PCMCIA + * + * Arg is socket number + */ +#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */ +#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */ +#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */ + +/* MECR register defines */ +#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ +#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ + +#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ +#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ +#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ +#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ + +#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ +#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ +#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ +#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ +#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ +#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ +#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ +#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ +#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ +#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ +#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ +#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ +#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ +#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ + +/* + * Power Manager + */ + +#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ +#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ +#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ +#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ +#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ +#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ +#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ +#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ +#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ +#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ +#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ +#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ +#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ + +#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ +#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ +#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ +#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ +#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ +#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ +#define PCMD(x) __REG2(0x40F00080, (x)<<2) +#define PCMD0 __REG(0x40F00080 + 0 * 4) +#define PCMD1 __REG(0x40F00080 + 1 * 4) +#define PCMD2 __REG(0x40F00080 + 2 * 4) +#define PCMD3 __REG(0x40F00080 + 3 * 4) +#define PCMD4 __REG(0x40F00080 + 4 * 4) +#define PCMD5 __REG(0x40F00080 + 5 * 4) +#define PCMD6 __REG(0x40F00080 + 6 * 4) +#define PCMD7 __REG(0x40F00080 + 7 * 4) +#define PCMD8 __REG(0x40F00080 + 8 * 4) +#define PCMD9 __REG(0x40F00080 + 9 * 4) +#define PCMD10 __REG(0x40F00080 + 10 * 4) +#define PCMD11 __REG(0x40F00080 + 11 * 4) +#define PCMD12 __REG(0x40F00080 + 12 * 4) +#define PCMD13 __REG(0x40F00080 + 13 * 4) +#define PCMD14 __REG(0x40F00080 + 14 * 4) +#define PCMD15 __REG(0x40F00080 + 15 * 4) +#define PCMD16 __REG(0x40F00080 + 16 * 4) +#define PCMD17 __REG(0x40F00080 + 17 * 4) +#define PCMD18 __REG(0x40F00080 + 18 * 4) +#define PCMD19 __REG(0x40F00080 + 19 * 4) +#define PCMD20 __REG(0x40F00080 + 20 * 4) +#define PCMD21 __REG(0x40F00080 + 21 * 4) +#define PCMD22 __REG(0x40F00080 + 22 * 4) +#define PCMD23 __REG(0x40F00080 + 23 * 4) +#define PCMD24 __REG(0x40F00080 + 24 * 4) +#define PCMD25 __REG(0x40F00080 + 25 * 4) +#define PCMD26 __REG(0x40F00080 + 26 * 4) +#define PCMD27 __REG(0x40F00080 + 27 * 4) +#define PCMD28 __REG(0x40F00080 + 28 * 4) +#define PCMD29 __REG(0x40F00080 + 29 * 4) +#define PCMD30 __REG(0x40F00080 + 30 * 4) +#define PCMD31 __REG(0x40F00080 + 31 * 4) + +#define PCMD_MBC (1<<12) +#define PCMD_DCE (1<<11) +#define PCMD_LC (1<<10) +/* FIXME: PCMD_SQC need be checked. */ +#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, + bit 9 should be 0 all day. */ +#define PVCR_VCSA (0x1<<14) +#define PVCR_CommandDelay (0xf80) +#define PCFR_PI2C_EN (0x1 << 6) + +#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ +#define PSSR_RDH (1 << 5) /* Read Disable Hold */ +#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ +#define PSSR_STS (1 << 3) /* Standby Mode Status */ +#define PSSR_VFS (1 << 2) /* VDD Fault Status */ +#define PSSR_BFS (1 << 1) /* Battery Fault Status */ +#define PSSR_SSS (1 << 0) /* Software Sleep Status */ + +#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ + +#define PCFR_RO (1 << 15) /* RDH Override */ +#define PCFR_PO (1 << 14) /* PH Override */ +#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ +#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ +#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ +#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ +#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ +#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ +#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ +#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ +#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ +#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ + +#define RCSR_GPR (1 << 3) /* GPIO Reset */ +#define RCSR_SMR (1 << 2) /* Sleep Mode */ +#define RCSR_WDR (1 << 1) /* Watchdog Reset */ +#define RCSR_HWR (1 << 0) /* Hardware Reset */ + +#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ +#define PWER_GPIO0 PWER_GPIO(0) /* GPIO [0] wake-up enable */ +#define PWER_GPIO1 PWER_GPIO(1) /* GPIO [1] wake-up enable */ +#define PWER_GPIO2 PWER_GPIO(2) /* GPIO [2] wake-up enable */ +#define PWER_GPIO3 PWER_GPIO(3) /* GPIO [3] wake-up enable */ +#define PWER_GPIO4 PWER_GPIO(4) /* GPIO [4] wake-up enable */ +#define PWER_GPIO5 PWER_GPIO(5) /* GPIO [5] wake-up enable */ +#define PWER_GPIO6 PWER_GPIO(6) /* GPIO [6] wake-up enable */ +#define PWER_GPIO7 PWER_GPIO(7) /* GPIO [7] wake-up enable */ +#define PWER_GPIO8 PWER_GPIO(8) /* GPIO [8] wake-up enable */ +#define PWER_GPIO9 PWER_GPIO(9) /* GPIO [9] wake-up enable */ +#define PWER_GPIO10 PWER_GPIO(10) /* GPIO [10] wake-up enable */ +#define PWER_GPIO11 PWER_GPIO(11) /* GPIO [11] wake-up enable */ +#define PWER_GPIO12 PWER_GPIO(12) /* GPIO [12] wake-up enable */ +#define PWER_GPIO13 PWER_GPIO(13) /* GPIO [13] wake-up enable */ +#define PWER_GPIO14 PWER_GPIO(14) /* GPIO [14] wake-up enable */ +#define PWER_GPIO15 PWER_GPIO(15) /* GPIO [15] wake-up enable */ +#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ + +/* + * PXA2xx specific Core clock definitions + */ +#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ +#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ +#define CKEN __REG(0x41300004) /* Clock Enable Register */ +#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ + +#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ +#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ +#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ + +#define CKEN_AC97CONF (1 << 31) /* AC97 Controller Configuration */ +#define CKEN_CAMERA (1 << 24) /* Camera Interface Clock Enable */ +#define CKEN_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ +#define CKEN_MEMC (1 << 22) /* Memory Controller Clock Enable */ +#define CKEN_MEMSTK (1 << 21) /* Memory Stick Host Controller */ +#define CKEN_IM (1 << 20) /* Internal Memory Clock Enable */ +#define CKEN_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ +#define CKEN_USIM (1 << 18) /* USIM Unit Clock Enable */ +#define CKEN_MSL (1 << 17) /* MSL Unit Clock Enable */ +#define CKEN_LCD (1 << 16) /* LCD Unit Clock Enable */ +#define CKEN_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ +#define CKEN_I2C (1 << 14) /* I2C Unit Clock Enable */ +#define CKEN_FICP (1 << 13) /* FICP Unit Clock Enable */ +#define CKEN_MMC (1 << 12) /* MMC Unit Clock Enable */ +#define CKEN_USB (1 << 11) /* USB Unit Clock Enable */ +#define CKEN_ASSP (1 << 10) /* ASSP (1 << SSP3) Clock Enable */ +#define CKEN_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ +#define CKEN_OSTIMER (1 << 9) /* OS Timer Unit Clock Enable */ +#define CKEN_NSSP (1 << 9) /* NSSP (1 << SSP2) Clock Enable */ +#define CKEN_I2S (1 << 8) /* I2S Unit Clock Enable */ +#define CKEN_BTUART (1 << 7) /* BTUART Unit Clock Enable */ +#define CKEN_FFUART (1 << 6) /* FFUART Unit Clock Enable */ +#define CKEN_STUART (1 << 5) /* STUART Unit Clock Enable */ +#define CKEN_HWUART (1 << 4) /* HWUART Unit Clock Enable */ +#define CKEN_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ +#define CKEN_SSP (1 << 3) /* SSP Unit Clock Enable */ +#define CKEN_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */ +#define CKEN_AC97 (1 << 2) /* AC97 Unit Clock Enable */ +#define CKEN_PWM1 (1 << 1) /* PWM1 Clock Enable */ +#define CKEN_PWM0 (1 << 0) /* PWM0 Clock Enable */ + +#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ +#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ + +/* PWRMODE register M field values */ + +#define PWRMODE_IDLE 0x1 +#define PWRMODE_STANDBY 0x2 +#define PWRMODE_SLEEP 0x3 +#define PWRMODE_DEEPSLEEP 0x7 + +#endif diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h new file mode 100644 index 0000000000..68464ce1c1 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-intc.h @@ -0,0 +1,34 @@ +#ifndef __ASM_MACH_REGS_INTC_H +#define __ASM_MACH_REGS_INTC_H + +#include <mach/hardware.h> + +/* + * Interrupt Controller + */ + +#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ +#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ +#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ +#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ +#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ +#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ +#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ + +#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ +#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ +#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ +#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ +#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ + +#define ICIP3 __REG(0x40D00130) /* Interrupt Controller IRQ Pending Register 3 */ +#define ICMR3 __REG(0x40D00134) /* Interrupt Controller Mask Register 3 */ +#define ICLR3 __REG(0x40D00138) /* Interrupt Controller Level Register 3 */ +#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */ +#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */ + +#define IPR(x) __REG(0x40D0001C + (x < 32 ? (x << 2) \ + : (x < 64 ? (0x94 + ((x - 32) << 2)) \ + : (0x128 + ((x - 64) << 2))))) + +#endif /* __ASM_MACH_REGS_INTC_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h new file mode 100644 index 0000000000..a3e5f86ef6 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ost.h @@ -0,0 +1,34 @@ +#ifndef __ASM_MACH_REGS_OST_H +#define __ASM_MACH_REGS_OST_H + +#include <mach/hardware.h> + +/* + * OS Timer & Match Registers + */ + +#define OSMR0 __REG(0x40A00000) /* */ +#define OSMR1 __REG(0x40A00004) /* */ +#define OSMR2 __REG(0x40A00008) /* */ +#define OSMR3 __REG(0x40A0000C) /* */ +#define OSMR4 __REG(0x40A00080) /* */ +#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ +#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ +#define OMCR4 __REG(0x40A000C0) /* */ +#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ +#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ +#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ + +#define OSSR_M3 (1 << 3) /* Match status channel 3 */ +#define OSSR_M2 (1 << 2) /* Match status channel 2 */ +#define OSSR_M1 (1 << 1) /* Match status channel 1 */ +#define OSSR_M0 (1 << 0) /* Match status channel 0 */ + +#define OWER_WME (1 << 0) /* Watchdog Match Enable */ + +#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ +#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ +#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ +#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ + +#endif /* __ASM_MACH_REGS_OST_H */ diff --git a/arch/arm/mach-pxa/include/mach/udc_pxa2xx.h b/arch/arm/mach-pxa/include/mach/udc_pxa2xx.h new file mode 100644 index 0000000000..dcdd36a3b4 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/udc_pxa2xx.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-pxa/include/mach/udc_pxa2xx.h + * + * This supports machine-specific differences in how the PXA2xx + * USB Device Controller (UDC) is wired. + * + * It is set in linux/arch/arm/mach-pxa/<machine>.c or in + * linux/arch/mach-ixp4xx/<machine>.c and used in + * the probe routine of linux/drivers/usb/gadget/pxa2xx_udc.c + */ + +struct pxa2xx_udc_mach_info { + int (*udc_is_connected)(void); /* do we see host? */ + void (*udc_command)(int cmd); +#define PXA2XX_UDC_CMD_CONNECT 0 /* let host see us */ +#define PXA2XX_UDC_CMD_DISCONNECT 1 /* so host won't see us */ + + /* Boards following the design guidelines in the developer's manual, + * with on-chip GPIOs not Lubbock's weird hardware, can have a sane + * VBUS IRQ and omit the methods above. Store the GPIO number + * here. Note that sometimes the signals go through inverters... + */ + bool gpio_pullup_inverted; + int gpio_pullup; /* high == pullup activated */ +}; + |