diff options
Diffstat (limited to 'arch/arm/mach-stm32mp')
-rw-r--r-- | arch/arm/mach-stm32mp/Kconfig | 23 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/Makefile | 4 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/bbu.c | 197 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/bl33-generic.c | 24 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/ddrctrl.c | 64 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/include/mach/bbu.h | 14 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/include/mach/bootsource.h | 21 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/include/mach/bsec.h | 41 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/include/mach/ddr_regs.h | 368 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/include/mach/debug_ll.h | 28 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/include/mach/entry.h | 19 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/include/mach/revision.h | 99 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/include/mach/smc.h | 28 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/include/mach/stm32.h | 37 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/init.c | 139 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/stm32image.c | 8 |
16 files changed, 333 insertions, 781 deletions
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 8328eb899a..524d282a1d 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -1,18 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-only + if ARCH_STM32MP config ARCH_NR_GPIO int default 416 +config ARCH_STM32MP13 + select ARM_PSCI_CLIENT + bool + config ARCH_STM32MP157 select ARM_PSCI_CLIENT bool +config MACH_STM32MP13XX_DK + select ARCH_STM32MP13 + bool "STM32MP135F DK board" + config MACH_STM32MP15XX_DKX select ARCH_STM32MP157 bool "STM32MP157 DK1 and DK2 boards" help - builds a single barebox-stm32mp15xx-dkx.img that can be deployed + builds a single barebox-stm32mp15xx-dkx.stm32 that can be deployed as SSBL on both the stm32mp157a-dk1 and stm32mp157c-dk2 config MACH_LXA_MC1 @@ -27,7 +37,7 @@ config MACH_STM32MP15X_EV1 select ARCH_STM32MP157 bool "STM32MP15X-EV1 board" help - builds a single barebox-stm32mp15x-ev1.img that can be deployed + builds a single barebox-stm32mp15x-ev1.stm32 that can be deployed as SSBL on any STM32MP15X-EVAL platform, like the STM32MP157C-EV1 @@ -35,7 +45,14 @@ config MACH_PROTONIC_STM32MP1 select ARCH_STM32MP157 bool "Protonic PRTT1L family of boards" help - Builds all barebox-prtt1*.img that can be deployed as SSBL + Builds all barebox-prtt1*.stm32 that can be deployed as SSBL on the respective PRTT1L family board +config MACH_PHYTEC_PHYCORE_STM32MP1 + select ARCH_STM32MP157 + bool "phyCORE-STM32MP1" + help + builds an additional barebox-phytec-phycore.stm32 + that can be deployed as SSBL on the phyCORE-STM32MP1 + endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index 8e14b22535..837449150c 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -1,3 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y := init.o obj-pbl-y := ddrctrl.o +pbl-y := bl33-generic.o obj-$(CONFIG_BOOTM) += stm32image.o +obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o diff --git a/arch/arm/mach-stm32mp/bbu.c b/arch/arm/mach-stm32mp/bbu.c new file mode 100644 index 0000000000..5d6d61db7d --- /dev/null +++ b/arch/arm/mach-stm32mp/bbu.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#define pr_fmt(fmt) "stm32mp-bbu: " fmt +#include <common.h> +#include <malloc.h> +#include <bbu.h> +#include <filetype.h> +#include <errno.h> +#include <fs.h> +#include <fcntl.h> +#include <linux/sizes.h> +#include <linux/stat.h> +#include <ioctl.h> +#include <mach/stm32mp/bbu.h> +#include <libfile.h> +#include <linux/bitfield.h> + +#define STM32MP_BBU_IMAGE_HAVE_FSBL BIT(0) +#define STM32MP_BBU_IMAGE_HAVE_FIP BIT(1) + +struct stm32mp_bbu_handler { + struct bbu_handler handler; + loff_t offset; +}; + +#define to_stm32mp_bbu_handler(h) container_of(h, struct stm32mp_bbu_handler, h) + +static int stm32mp_bbu_gpt_part_update(struct bbu_handler *handler, + const struct bbu_data *data, + const char *part, bool optional) +{ + struct bbu_data gpt_data = *data; + struct stat st; + int ret; + + gpt_data.devicefile = basprintf("%s.%s", gpt_data.devicefile, part); + if (!gpt_data.devicefile) + return -ENOMEM; + + pr_debug("Attempting %s update\n", gpt_data.devicefile); + + ret = stat(gpt_data.devicefile, &st); + if (ret == -ENOENT) { + if (optional) + return 0; + pr_err("Partition %s does not exist\n", gpt_data.devicefile); + } + if (ret) + goto out; + + ret = bbu_std_file_handler(handler, &gpt_data); +out: + kfree_const(gpt_data.devicefile); + return ret; +} + +static int stm32mp_bbu_mmc_update(struct bbu_handler *handler, + struct bbu_data *data) +{ + struct stm32mp_bbu_handler *priv = to_stm32mp_bbu_handler(handler); + int fd, ret; + size_t image_len = data->len; + const void *buf = data->image; + struct stat st; + + pr_debug("Attempting eMMC boot partition update\n"); + + ret = bbu_confirm(data); + if (ret) + return ret; + + fd = open(data->devicefile, O_RDWR); + if (fd < 0) + return fd; + + ret = fstat(fd, &st); + if (ret) + goto close; + + if (st.st_size < priv->offset || image_len > st.st_size - priv->offset) { + ret = -ENOSPC; + goto close; + } + + ret = pwrite_full(fd, buf, image_len, priv->offset); + if (ret < 0) + pr_err("writing to %s failed with %pe\n", data->devicefile, ERR_PTR(ret)); + +close: + close(fd); + + return ret < 0 ? ret : 0; +} + +/* + * TF-A compiled with STM32_EMMC_BOOT will first check for FIP image + * at offset SZ_256K and then in GPT partition of that name. + */ +static int stm32mp_bbu_mmc_fip_handler(struct bbu_handler *handler, + struct bbu_data *data) +{ + struct stm32mp_bbu_handler *priv = to_stm32mp_bbu_handler(handler); + enum filetype filetype; + int image_flags = 0, ret; + bool is_emmc = true; + + filetype = file_detect_type(data->image, data->len); + + switch (filetype) { + case filetype_stm32_image_fsbl_v1: + priv->offset = 0; + image_flags |= STM32MP_BBU_IMAGE_HAVE_FSBL; + if (data->len > SZ_256K) + image_flags |= STM32MP_BBU_IMAGE_HAVE_FIP; + break; + default: + if (!bbu_force(data, "incorrect image type. Expected: %s, got %s", + file_type_to_string(filetype_fip), + file_type_to_string(filetype))) + return -EINVAL; + /* If forced assume it's a SSBL */ + filetype = filetype_fip; + fallthrough; + case filetype_fip: + priv->offset = SZ_256K; + image_flags |= STM32MP_BBU_IMAGE_HAVE_FIP; + break; + } + + pr_debug("Handling %s\n", file_type_to_string(filetype)); + + handler->flags |= BBU_HANDLER_FLAG_MMC_BOOT_ACK; + + ret = bbu_mmcboot_handler(handler, data, stm32mp_bbu_mmc_update); + if (ret == -ENOENT) { + pr_debug("Not an eMMC, falling back to GPT fsbl1 partition\n"); + is_emmc = false; + ret = 0; + } + if (ret < 0) { + pr_debug("eMMC boot update failed: %pe\n", ERR_PTR(ret)); + return ret; + } + + if (!is_emmc && (image_flags & STM32MP_BBU_IMAGE_HAVE_FSBL)) { + struct bbu_data fsbl1_data = *data; + + fsbl1_data.len = min_t(size_t, fsbl1_data.len, SZ_256K); + + /* + * BootROM tells TF-A which fsbl slot was booted in r0, but TF-A + * doesn't yet propagate this to us, so for now always flash + * fsbl1 + */ + ret = stm32mp_bbu_gpt_part_update(handler, &fsbl1_data, "fsbl1", false); + } + + if (ret == 0 && (image_flags & STM32MP_BBU_IMAGE_HAVE_FIP)) { + struct bbu_data fip_data = *data; + + if (image_flags & STM32MP_BBU_IMAGE_HAVE_FSBL) { + fip_data.image += SZ_256K; + fip_data.len -= SZ_256K; + } + + /* No fip GPT partition in eMMC user area is usually ok, as + * that means TF-A is configured to load FIP from eMMC boot part + */ + ret = stm32mp_bbu_gpt_part_update(handler, &fip_data, "fip", is_emmc); + } + + if (ret < 0) + pr_debug("eMMC user area update failed: %pe\n", ERR_PTR(ret)); + + return ret; +} + +int stm32mp_bbu_mmc_fip_register(const char *name, + const char *devicefile, + unsigned long flags) +{ + struct stm32mp_bbu_handler *priv; + int ret; + + priv = xzalloc(sizeof(*priv)); + + priv->handler.flags = flags; + priv->handler.devicefile = devicefile; + priv->handler.name = name; + priv->handler.handler = stm32mp_bbu_mmc_fip_handler; + + ret = bbu_register_handler(&priv->handler); + if (ret) + free(priv); + + return ret; +} diff --git a/arch/arm/mach-stm32mp/bl33-generic.c b/arch/arm/mach-stm32mp/bl33-generic.c new file mode 100644 index 0000000000..dda0135a07 --- /dev/null +++ b/arch/arm/mach-stm32mp/bl33-generic.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <mach/stm32mp/entry.h> +#include <debug_ll.h> + +/* + * barebox-dt-2nd.img expects being loaded at an offset, so the + * stack can grow down from entry point. The STM32MP TF-A default + * is to not have an offset. This stm32mp specific entry points + * avoids this issue by setting up a 64 byte stack after end of + * barebox and by asking the memory controller about RAM size + * instead of parsing it out of the DT. + * + * When using OP-TEE, ensure CONFIG_OPTEE_SIZE is appopriately set. + */ + +ENTRY_FUNCTION(start_stm32mp_bl33, r0, r1, r2) +{ + stm32mp_cpu_lowlevel_init(); + + putc_ll('>'); + + stm32mp1_barebox_entry((void *)r2); +} diff --git a/arch/arm/mach-stm32mp/ddrctrl.c b/arch/arm/mach-stm32mp/ddrctrl.c index 7f2013c22d..f198ee196c 100644 --- a/arch/arm/mach-stm32mp/ddrctrl.c +++ b/arch/arm/mach-stm32mp/ddrctrl.c @@ -5,10 +5,10 @@ #include <common.h> #include <init.h> -#include <mach/stm32.h> -#include <mach/ddr_regs.h> -#include <mach/entry.h> -#include <mach/stm32.h> +#include <mach/stm32mp/ddr_regs.h> +#include <mach/stm32mp/entry.h> +#include <mach/stm32mp/stm32.h> +#include <mach/stm32mp/revision.h> #include <asm/barebox-arm.h> #include <asm/memory.h> #include <pbl.h> @@ -24,12 +24,12 @@ #define ADDRMAP2_COL_B5 GENMASK(27, 24) #define ADDRMAP3_COL_B6 GENMASK( 3, 0) -#define ADDRMAP3_COL_B7 GENMASK(12, 8) -#define ADDRMAP3_COL_B8 GENMASK(20, 16) -#define ADDRMAP3_COL_B9 GENMASK(28, 24) +#define ADDRMAP3_COL_B7 GENMASK(11, 8) +#define ADDRMAP3_COL_B8 GENMASK(19, 16) +#define ADDRMAP3_COL_B9 GENMASK(27, 24) -#define ADDRMAP4_COL_B10 GENMASK( 4, 0) -#define ADDRMAP4_COL_B11 GENMASK(12, 8) +#define ADDRMAP4_COL_B10 GENMASK( 3, 0) +#define ADDRMAP4_COL_B11 GENMASK(11, 8) #define ADDRMAP5_ROW_B0 GENMASK( 3, 0) #define ADDRMAP5_ROW_B1 GENMASK(11, 8) @@ -62,7 +62,8 @@ enum ddrctrl_buswidth { }; static unsigned long ddrctrl_addrmap_ramsize(struct stm32mp1_ddrctl __iomem *d, - enum ddrctrl_buswidth buswidth) + enum ddrctrl_buswidth buswidth, + unsigned nb_bytes) { unsigned banks = 3, cols = 12, rows = 16; u32 reg; @@ -99,61 +100,62 @@ static unsigned long ddrctrl_addrmap_ramsize(struct stm32mp1_ddrctl __iomem *d, if (LINE_UNUSED(reg, ADDRMAP6_ROW_B13)) rows--; if (LINE_UNUSED(reg, ADDRMAP6_ROW_B12)) rows--; - return memory_sdram_size(cols, rows, BIT(banks), 4 / BIT(buswidth)); + return memory_sdram_size(cols, rows, BIT(banks), + DIV_ROUND_UP(nb_bytes, BIT(buswidth))); } -static inline unsigned ddrctrl_ramsize(void __iomem *base) +static inline unsigned ddrctrl_ramsize(void __iomem *base, unsigned nb_bytes) { struct stm32mp1_ddrctl __iomem *ddrctl = base; unsigned buswidth = readl(&ddrctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK; buswidth >>= DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT; - return ddrctrl_addrmap_ramsize(ddrctl, buswidth); + return ddrctrl_addrmap_ramsize(ddrctl, buswidth, nb_bytes); } static inline unsigned stm32mp1_ddrctrl_ramsize(void) { - return ddrctrl_ramsize(IOMEM(STM32_DDRCTL_BASE)); + u32 nb_bytes = 4; + + if (cpu_stm32_is_stm32mp13()) + nb_bytes /= 2; + + return ddrctrl_ramsize(IOMEM(STM32_DDRCTL_BASE), nb_bytes); } -void __noreturn stm32mp1_barebox_entry(void *boarddata) +void __noreturn __prereloc stm32mp1_barebox_entry(void *boarddata) { barebox_arm_entry(STM32_DDR_BASE, stm32mp1_ddrctrl_ramsize(), boarddata); } -static int stm32mp1_ddr_probe(struct device_d *dev) +static int stm32mp1_ddr_probe(struct device *dev) { struct resource *iores; void __iomem *base; + unsigned long nb_bytes; iores = dev_request_mem_resource(dev, 0); if (IS_ERR(iores)) return PTR_ERR(iores); base = IOMEM(iores->start); - return arm_add_mem_device("ram0", STM32_DDR_BASE, ddrctrl_ramsize(base)); + nb_bytes = (unsigned long)device_get_match_data(dev); + + return arm_add_mem_device("ram0", STM32_DDR_BASE, + ddrctrl_ramsize(base, nb_bytes)); } static __maybe_unused struct of_device_id stm32mp1_ddr_dt_ids[] = { - { .compatible = "st,stm32mp1-ddr" }, + { .compatible = "st,stm32mp1-ddr", .data = (void *)4 }, + { .compatible = "st,stm32mp13-ddr", .data = (void *)2 }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, stm32mp1_ddr_dt_ids); -static struct driver_d stm32mp1_ddr_driver = { +static struct driver stm32mp1_ddr_driver = { .name = "stm32mp1-ddr", .probe = stm32mp1_ddr_probe, .of_compatible = DRV_OF_COMPAT(stm32mp1_ddr_dt_ids), }; - -static int stm32mp1_ddr_init(void) -{ - int ret; - - ret = platform_driver_register(&stm32mp1_ddr_driver); - if (ret) - return ret; - - return of_devices_ensure_probed_by_dev_id(stm32mp1_ddr_dt_ids); -} -mem_initcall(stm32mp1_ddr_init); +mem_platform_driver(stm32mp1_ddr_driver); diff --git a/arch/arm/mach-stm32mp/include/mach/bbu.h b/arch/arm/mach-stm32mp/include/mach/bbu.h deleted file mode 100644 index 8b9504400e..0000000000 --- a/arch/arm/mach-stm32mp/include/mach/bbu.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef MACH_STM32MP_BBU_H_ -#define MACH_STM32MP_BBU_H_ - -#include <bbu.h> - -static inline int stm32mp_bbu_mmc_register_handler(const char *name, - const char *devicefile, - unsigned long flags) -{ - return bbu_register_std_file_update(name, flags, devicefile, - filetype_stm32_image_v1); -} - -#endif /* MACH_STM32MP_BBU_H_ */ diff --git a/arch/arm/mach-stm32mp/include/mach/bootsource.h b/arch/arm/mach-stm32mp/include/mach/bootsource.h deleted file mode 100644 index 5750dc1448..0000000000 --- a/arch/arm/mach-stm32mp/include/mach/bootsource.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - */ - -#ifndef __MACH_STM32_BOOTSOURCE_H__ -#define __MACH_STM32_BOOTSOURCE_H__ - -enum stm32mp_boot_device { - STM32MP_BOOT_FLASH_SD = 0x10, /* .. 0x13 */ - STM32MP_BOOT_FLASH_EMMC = 0x20, /* .. 0x23 */ - STM32MP_BOOT_FLASH_NAND = 0x30, - STM32MP_BOOT_FLASH_NAND_FMC = 0x31, - STM32MP_BOOT_FLASH_NOR = 0x40, - STM32MP_BOOT_FLASH_NOR_QSPI = 0x41, - STM32MP_BOOT_SERIAL_UART = 0x50, /* .. 0x58 */ - STM32MP_BOOT_SERIAL_USB = 0x60, - STM32MP_BOOT_SERIAL_USB_OTG = 0x62, -}; - -#endif diff --git a/arch/arm/mach-stm32mp/include/mach/bsec.h b/arch/arm/mach-stm32mp/include/mach/bsec.h deleted file mode 100644 index d3cb91b1fd..0000000000 --- a/arch/arm/mach-stm32mp/include/mach/bsec.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef __MACH_STM32_BSEC_H__ -#define __MACH_STM32_BSEC_H__ - -#include <mach/smc.h> - -/* Return status */ -enum bsec_smc { - BSEC_SMC_OK = 0, - BSEC_SMC_ERROR = -1, - BSEC_SMC_DISTURBED = -2, - BSEC_SMC_INVALID_PARAM = -3, - BSEC_SMC_PROG_FAIL = -4, - BSEC_SMC_LOCK_FAIL = -5, - BSEC_SMC_WRITE_FAIL = -6, - BSEC_SMC_SHADOW_FAIL = -7, - BSEC_SMC_TIMEOUT = -8, -}; - -/* Service for BSEC */ -enum bsec_op { - BSEC_SMC_READ_SHADOW = 1, - BSEC_SMC_PROG_OTP = 2, - BSEC_SMC_WRITE_SHADOW = 3, - BSEC_SMC_READ_OTP = 4, - BSEC_SMC_READ_ALL = 5, - BSEC_SMC_WRITE_ALL = 6, -}; - -static inline enum bsec_smc bsec_read_field(unsigned field, unsigned *val) -{ - return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_READ_SHADOW, - field, 0, val); -} - -static inline enum bsec_smc bsec_write_field(unsigned field, unsigned val) -{ - return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_WRITE_SHADOW, - field, val, NULL); -} - -#endif diff --git a/arch/arm/mach-stm32mp/include/mach/ddr_regs.h b/arch/arm/mach-stm32mp/include/mach/ddr_regs.h deleted file mode 100644 index 7d6a5b8be4..0000000000 --- a/arch/arm/mach-stm32mp/include/mach/ddr_regs.h +++ /dev/null @@ -1,368 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - */ - -#ifndef _STM32MP1_DDR_REGS_H -#define _STM32MP1_DDR_REGS_H - -/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */ -struct stm32mp1_ddrctl { - u32 mstr ; /* 0x0 Master*/ - u32 stat; /* 0x4 Operating Mode Status*/ - u8 reserved008[0x10 - 0x8]; - u32 mrctrl0; /* 0x10 Control 0.*/ - u32 mrctrl1; /* 0x14 Control 1*/ - u32 mrstat; /* 0x18 Status*/ - u32 reserved01c; /* 0x1c */ - u32 derateen; /* 0x20 Temperature Derate Enable*/ - u32 derateint; /* 0x24 Temperature Derate Interval*/ - u8 reserved028[0x30 - 0x28]; - u32 pwrctl; /* 0x30 Low Power Control*/ - u32 pwrtmg; /* 0x34 Low Power Timing*/ - u32 hwlpctl; /* 0x38 Hardware Low Power Control*/ - u8 reserved03c[0x50 - 0x3C]; - u32 rfshctl0; /* 0x50 Refresh Control 0*/ - u32 reserved054; /* 0x54 Refresh Control 1*/ - u32 reserved058; /* 0x58 Refresh Control 2*/ - u32 reserved05C; - u32 rfshctl3; /* 0x60 Refresh Control 0*/ - u32 rfshtmg; /* 0x64 Refresh Timing*/ - u8 reserved068[0xc0 - 0x68]; - u32 crcparctl0; /* 0xc0 CRC Parity Control0*/ - u32 reserved0c4; /* 0xc4 CRC Parity Control1*/ - u32 reserved0c8; /* 0xc8 CRC Parity Control2*/ - u32 crcparstat; /* 0xcc CRC Parity Status*/ - u32 init0; /* 0xd0 SDRAM Initialization 0*/ - u32 init1; /* 0xd4 SDRAM Initialization 1*/ - u32 init2; /* 0xd8 SDRAM Initialization 2*/ - u32 init3; /* 0xdc SDRAM Initialization 3*/ - u32 init4; /* 0xe0 SDRAM Initialization 4*/ - u32 init5; /* 0xe4 SDRAM Initialization 5*/ - u32 reserved0e8; - u32 reserved0ec; - u32 dimmctl; /* 0xf0 DIMM Control*/ - u8 reserved0f4[0x100 - 0xf4]; - u32 dramtmg0; /* 0x100 SDRAM Timing 0*/ - u32 dramtmg1; /* 0x104 SDRAM Timing 1*/ - u32 dramtmg2; /* 0x108 SDRAM Timing 2*/ - u32 dramtmg3; /* 0x10c SDRAM Timing 3*/ - u32 dramtmg4; /* 0x110 SDRAM Timing 4*/ - u32 dramtmg5; /* 0x114 SDRAM Timing 5*/ - u32 dramtmg6; /* 0x118 SDRAM Timing 6*/ - u32 dramtmg7; /* 0x11c SDRAM Timing 7*/ - u32 dramtmg8; /* 0x120 SDRAM Timing 8*/ - u8 reserved124[0x138 - 0x124]; - u32 dramtmg14; /* 0x138 SDRAM Timing 14*/ - u32 dramtmg15; /* 0x13C SDRAM Timing 15*/ - u8 reserved140[0x180 - 0x140]; - u32 zqctl0; /* 0x180 ZQ Control 0*/ - u32 zqctl1; /* 0x184 ZQ Control 1*/ - u32 zqctl2; /* 0x188 ZQ Control 2*/ - u32 zqstat; /* 0x18c ZQ Status*/ - u32 dfitmg0; /* 0x190 DFI Timing 0*/ - u32 dfitmg1; /* 0x194 DFI Timing 1*/ - u32 dfilpcfg0; /* 0x198 DFI Low Power Configuration 0*/ - u32 reserved19c; - u32 dfiupd0; /* 0x1a0 DFI Update 0*/ - u32 dfiupd1; /* 0x1a4 DFI Update 1*/ - u32 dfiupd2; /* 0x1a8 DFI Update 2*/ - u32 reserved1ac; - u32 dfimisc; /* 0x1b0 DFI Miscellaneous Control*/ - u8 reserved1b4[0x1bc - 0x1b4]; - u32 dfistat; /* 0x1bc DFI Miscellaneous Control*/ - u8 reserved1c0[0x1c4 - 0x1c0]; - u32 dfiphymstr; /* 0x1c4 DFI PHY Master interface*/ - u8 reserved1c8[0x204 - 0x1c8]; - u32 addrmap1; /* 0x204 Address Map 1*/ - u32 addrmap2; /* 0x208 Address Map 2*/ - u32 addrmap3; /* 0x20c Address Map 3*/ - u32 addrmap4; /* 0x210 Address Map 4*/ - u32 addrmap5; /* 0x214 Address Map 5*/ - u32 addrmap6; /* 0x218 Address Map 6*/ - u8 reserved21c[0x224 - 0x21c]; - u32 addrmap9; /* 0x224 Address Map 9*/ - u32 addrmap10; /* 0x228 Address Map 10*/ - u32 addrmap11; /* 0x22C Address Map 11*/ - u8 reserved230[0x240 - 0x230]; - u32 odtcfg; /* 0x240 ODT Configuration*/ - u32 odtmap; /* 0x244 ODT/Rank Map*/ - u8 reserved248[0x250 - 0x248]; - u32 sched; /* 0x250 Scheduler Control*/ - u32 sched1; /* 0x254 Scheduler Control 1*/ - u32 reserved258; - u32 perfhpr1; /* 0x25c High Priority Read CAM 1*/ - u32 reserved260; - u32 perflpr1; /* 0x264 Low Priority Read CAM 1*/ - u32 reserved268; - u32 perfwr1; /* 0x26c Write CAM 1*/ - u8 reserved27c[0x300 - 0x270]; - u32 dbg0; /* 0x300 Debug 0*/ - u32 dbg1; /* 0x304 Debug 1*/ - u32 dbgcam; /* 0x308 CAM Debug*/ - u32 dbgcmd; /* 0x30c Command Debug*/ - u32 dbgstat; /* 0x310 Status Debug*/ - u8 reserved314[0x320 - 0x314]; - u32 swctl; /* 0x320 Software Programming Control Enable*/ - u32 swstat; /* 0x324 Software Programming Control Status*/ - u8 reserved328[0x36c - 0x328]; - u32 poisoncfg; /* 0x36c AXI Poison Configuration Register*/ - u32 poisonstat; /* 0x370 AXI Poison Status Register*/ - u8 reserved374[0x3fc - 0x374]; - - /* Multi Port registers */ - u32 pstat; /* 0x3fc Port Status*/ - u32 pccfg; /* 0x400 Port Common Configuration*/ - - /* PORT 0 */ - u32 pcfgr_0; /* 0x404 Configuration Read*/ - u32 pcfgw_0; /* 0x408 Configuration Write*/ - u8 reserved40c[0x490 - 0x40c]; - u32 pctrl_0; /* 0x490 Port Control Register */ - u32 pcfgqos0_0; /* 0x494 Read QoS Configuration 0*/ - u32 pcfgqos1_0; /* 0x498 Read QoS Configuration 1*/ - u32 pcfgwqos0_0; /* 0x49c Write QoS Configuration 0*/ - u32 pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1*/ - u8 reserved4a4[0x4b4 - 0x4a4]; - - /* PORT 1 */ - u32 pcfgr_1; /* 0x4b4 Configuration Read*/ - u32 pcfgw_1; /* 0x4b8 Configuration Write*/ - u8 reserved4bc[0x540 - 0x4bc]; - u32 pctrl_1; /* 0x540 Port 2 Control Register */ - u32 pcfgqos0_1; /* 0x544 Read QoS Configuration 0*/ - u32 pcfgqos1_1; /* 0x548 Read QoS Configuration 1*/ - u32 pcfgwqos0_1; /* 0x54c Write QoS Configuration 0*/ - u32 pcfgwqos1_1; /* 0x550 Write QoS Configuration 1*/ -}; - -/* DDR Physical Interface Control (DDRPHYC) registers*/ -struct stm32mp1_ddrphy { - u32 ridr; /* 0x00 R Revision Identification*/ - u32 pir; /* 0x04 R/W PHY Initialization*/ - u32 pgcr; /* 0x08 R/W PHY General Configuration*/ - u32 pgsr; /* 0x0C PHY General Status*/ - u32 dllgcr; /* 0x10 R/W DLL General Control*/ - u32 acdllcr; /* 0x14 R/W AC DLL Control*/ - u32 ptr0; /* 0x18 R/W PHY Timing 0*/ - u32 ptr1; /* 0x1C R/W PHY Timing 1*/ - u32 ptr2; /* 0x20 R/W PHY Timing 2*/ - u32 aciocr; /* 0x24 AC I/O Configuration*/ - u32 dxccr; /* 0x28 DATX8 Common Configuration*/ - u32 dsgcr; /* 0x2C DDR System General Configuration*/ - u32 dcr; /* 0x30 DRAM Configuration*/ - u32 dtpr0; /* 0x34 DRAM Timing Parameters0*/ - u32 dtpr1; /* 0x38 DRAM Timing Parameters1*/ - u32 dtpr2; /* 0x3C DRAM Timing Parameters2*/ - u32 mr0; /* 0x40 Mode 0*/ - u32 mr1; /* 0x44 Mode 1*/ - u32 mr2; /* 0x48 Mode 2*/ - u32 mr3; /* 0x4C Mode 3*/ - u32 odtcr; /* 0x50 ODT Configuration*/ - u32 dtar; /* 0x54 data training address*/ - u32 dtdr0; /* 0x58 */ - u32 dtdr1; /* 0x5c */ - u8 res1[0x0c0 - 0x060]; /* 0x60 */ - u32 dcuar; /* 0xc0 Address*/ - u32 dcudr; /* 0xc4 DCU Data*/ - u32 dcurr; /* 0xc8 DCU Run*/ - u32 dculr; /* 0xcc DCU Loop*/ - u32 dcugcr; /* 0xd0 DCU General Configuration*/ - u32 dcutpr; /* 0xd4 DCU Timing Parameters */ - u32 dcusr0; /* 0xd8 DCU Status 0*/ - u32 dcusr1; /* 0xdc DCU Status 1*/ - u8 res2[0x100 - 0xe0]; /* 0xe0 */ - u32 bistrr; /* 0x100 BIST Run*/ - u32 bistmskr0; /* 0x104 BIST Mask 0*/ - u32 bistmskr1; /* 0x108 BIST Mask 0*/ - u32 bistwcr; /* 0x10c BIST Word Count*/ - u32 bistlsr; /* 0x110 BIST LFSR Seed*/ - u32 bistar0; /* 0x114 BIST Address 0*/ - u32 bistar1; /* 0x118 BIST Address 1*/ - u32 bistar2; /* 0x11c BIST Address 2*/ - u32 bistupdr; /* 0x120 BIST User Data Pattern*/ - u32 bistgsr; /* 0x124 BIST General Status*/ - u32 bistwer; /* 0x128 BIST Word Error*/ - u32 bistber0; /* 0x12c BIST Bit Error 0*/ - u32 bistber1; /* 0x130 BIST Bit Error 1*/ - u32 bistber2; /* 0x134 BIST Bit Error 2*/ - u32 bistwcsr; /* 0x138 BIST Word Count Status*/ - u32 bistfwr0; /* 0x13c BIST Fail Word 0*/ - u32 bistfwr1; /* 0x140 BIST Fail Word 1*/ - u8 res3[0x178 - 0x144]; /* 0x144 */ - u32 gpr0; /* 0x178 General Purpose 0 (GPR0)*/ - u32 gpr1; /* 0x17C General Purpose 1 (GPR1)*/ - u32 zq0cr0; /* 0x180 zq 0 control 0 */ - u32 zq0cr1; /* 0x184 zq 0 control 1 */ - u32 zq0sr0; /* 0x188 zq 0 status 0 */ - u32 zq0sr1; /* 0x18C zq 0 status 1 */ - u8 res4[0x1C0 - 0x190]; /* 0x190 */ - u32 dx0gcr; /* 0x1c0 Byte lane 0 General Configuration*/ - u32 dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0*/ - u32 dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1*/ - u32 dx0dllcr; /* 0x1cc Byte lane 0 DLL Control*/ - u32 dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing*/ - u32 dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing*/ - u8 res5[0x200 - 0x1d8]; /* 0x1d8 */ - u32 dx1gcr; /* 0x200 Byte lane 1 General Configuration*/ - u32 dx1gsr0; /* 0x204 Byte lane 1 General Status 0*/ - u32 dx1gsr1; /* 0x208 Byte lane 1 General Status 1*/ - u32 dx1dllcr; /* 0x20c Byte lane 1 DLL Control*/ - u32 dx1dqtr; /* 0x210 Byte lane 1 DQ Timing*/ - u32 dx1dqstr; /* 0x214 Byte lane 1 QS Timing*/ - u8 res6[0x240 - 0x218]; /* 0x218 */ - u32 dx2gcr; /* 0x240 Byte lane 2 General Configuration*/ - u32 dx2gsr0; /* 0x244 Byte lane 2 General Status 0*/ - u32 dx2gsr1; /* 0x248 Byte lane 2 General Status 1*/ - u32 dx2dllcr; /* 0x24c Byte lane 2 DLL Control*/ - u32 dx2dqtr; /* 0x250 Byte lane 2 DQ Timing*/ - u32 dx2dqstr; /* 0x254 Byte lane 2 QS Timing*/ - u8 res7[0x280 - 0x258]; /* 0x258 */ - u32 dx3gcr; /* 0x280 Byte lane 3 General Configuration*/ - u32 dx3gsr0; /* 0x284 Byte lane 3 General Status 0*/ - u32 dx3gsr1; /* 0x288 Byte lane 3 General Status 1*/ - u32 dx3dllcr; /* 0x28c Byte lane 3 DLL Control*/ - u32 dx3dqtr; /* 0x290 Byte lane 3 DQ Timing*/ - u32 dx3dqstr; /* 0x294 Byte lane 3 QS Timing*/ -}; - -#define DXN(phy, offset, byte) ((u32)(phy) + (offset) + ((u32)(byte) * 0x40)) -#define DXNGCR(phy, byte) DXN(phy, 0x1c0, byte) -#define DXNDLLCR(phy, byte) DXN(phy, 0x1cc, byte) -#define DXNDQTR(phy, byte) DXN(phy, 0x1d0, byte) -#define DXNDQSTR(phy, byte) DXN(phy, 0x1d4, byte) - -/* DDRCTRL REGISTERS */ -#define DDRCTRL_MSTR_DDR3 BIT(0) -#define DDRCTRL_MSTR_LPDDR2 BIT(2) -#define DDRCTRL_MSTR_LPDDR3 BIT(3) -#define DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT 12 -#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12) -#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12) -#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12) -#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER (2 << 12) -#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15) - -#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0) -#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 1 -#define DDRCTRL_STAT_OPERATING_MODE_SR 3 -#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4) -#define DDRCTRL_STAT_SELFREF_TYPE_ASR (3 << 4) -#define DDRCTRL_STAT_SELFREF_TYPE_SR (2 << 4) - -#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE 0 -/* only one rank supported */ -#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4 -#define DDRCTRL_MRCTRL0_MR_RANK_ALL \ - (0x1 << DDRCTRL_MRCTRL0_MR_RANK_SHIFT) -#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12 -#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12) -#define DDRCTRL_MRCTRL0_MR_WR BIT(31) - -#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0) - -#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) -#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) - -#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) - -#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16) -#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16 - -#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK (0xC0000000) -#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL (BIT(30)) - -#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) - -#define DDRCTRL_DBG1_DIS_HIF BIT(1) - -#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29) -#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28) -#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26) -#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8) -#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0) -#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \ - (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \ - DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY) -#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \ - (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \ - DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \ - DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH) - -#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0) - -#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0) - -#define DDRCTRL_SWCTL_SW_DONE BIT(0) - -#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0) - -#define DDRCTRL_PCTRL_N_PORT_EN BIT(0) - -/* DDRPHYC registers */ -#define DDRPHYC_PIR_INIT BIT(0) -#define DDRPHYC_PIR_DLLSRST BIT(1) -#define DDRPHYC_PIR_DLLLOCK BIT(2) -#define DDRPHYC_PIR_ZCAL BIT(3) -#define DDRPHYC_PIR_ITMSRST BIT(4) -#define DDRPHYC_PIR_DRAMRST BIT(5) -#define DDRPHYC_PIR_DRAMINIT BIT(6) -#define DDRPHYC_PIR_QSTRN BIT(7) -#define DDRPHYC_PIR_ICPC BIT(16) -#define DDRPHYC_PIR_ZCALBYP BIT(30) -#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7) - -#define DDRPHYC_PGCR_DFTCMP BIT(2) -#define DDRPHYC_PGCR_PDDISDX BIT(24) -#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25) - -#define DDRPHYC_PGSR_IDONE BIT(0) -#define DDRPHYC_PGSR_DTERR BIT(5) -#define DDRPHYC_PGSR_DTIERR BIT(6) -#define DDRPHYC_PGSR_DFTERR BIT(7) -#define DDRPHYC_PGSR_RVERR BIT(8) -#define DDRPHYC_PGSR_RVEIRR BIT(9) - -#define DDRPHYC_DLLGCR_BPS200 BIT(23) - -#define DDRPHYC_ACDLLCR_DLLDIS BIT(31) - -#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0) -#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0 -#define DDRPHYC_ZQ0CRN_ZDEN BIT(28) - -#define DDRPHYC_DXNGCR_DXEN BIT(0) - -#define DDRPHYC_DXNDLLCR_DLLSRST BIT(30) -#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31) -#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14) -#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14 - -#define DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit) (4 * (bit)) -#define DDRPHYC_DXNDQTR_DQDLY_MASK GENMASK(3, 0) -#define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK GENMASK(1, 0) -#define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK GENMASK(3, 2) - -#define DDRPHYC_DXNDQSTR_DQSDLY_MASK GENMASK(22, 20) -#define DDRPHYC_DXNDQSTR_DQSDLY_SHIFT 20 -#define DDRPHYC_DXNDQSTR_DQSNDLY_MASK GENMASK(25, 23) -#define DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT 23 -#define DDRPHYC_DXNDQSTR_R0DGSL_MASK GENMASK(2, 0) -#define DDRPHYC_DXNDQSTR_R0DGSL_SHIFT 0 -#define DDRPHYC_DXNDQSTR_R0DGPS_MASK GENMASK(13, 12) -#define DDRPHYC_DXNDQSTR_R0DGPS_SHIFT 12 - -#define DDRPHYC_BISTRR_BDXSEL_MASK GENMASK(22, 19) -#define DDRPHYC_BISTRR_BDXSEL_SHIFT 19 - -#define DDRPHYC_BISTGSR_BDDONE BIT(0) -#define DDRPHYC_BISTGSR_BDXERR BIT(2) - -#define DDRPHYC_BISTWCSR_DXWCNT_SHIFT 16 - -/* PWR registers */ -#define PWR_CR3 0x00C -#define PWR_CR3_DDRSRDIS BIT(11) -#define PWR_CR3_DDRRETEN BIT(12) - -#endif diff --git a/arch/arm/mach-stm32mp/include/mach/debug_ll.h b/arch/arm/mach-stm32mp/include/mach/debug_ll.h deleted file mode 100644 index 99fedb91fe..0000000000 --- a/arch/arm/mach-stm32mp/include/mach/debug_ll.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef __MACH_STM32MP1_DEBUG_LL_H -#define __MACH_STM32MP1_DEBUG_LL_H - -#include <io.h> -#include <mach/stm32.h> - -#define DEBUG_LL_UART_ADDR STM32_UART4_BASE - -#define CR1_OFFSET 0x00 -#define CR3_OFFSET 0x08 -#define BRR_OFFSET 0x0c -#define ISR_OFFSET 0x1c -#define ICR_OFFSET 0x20 -#define RDR_OFFSET 0x24 -#define TDR_OFFSET 0x28 - -#define USART_ISR_TXE BIT(7) - -static inline void PUTC_LL(int c) -{ - void __iomem *base = IOMEM(DEBUG_LL_UART_ADDR); - - writel(c, base + TDR_OFFSET); - - while ((readl(base + ISR_OFFSET) & USART_ISR_TXE) == 0); -} - -#endif /* __MACH_STM32MP1_DEBUG_LL_H */ diff --git a/arch/arm/mach-stm32mp/include/mach/entry.h b/arch/arm/mach-stm32mp/include/mach/entry.h deleted file mode 100644 index 92e15b5cf4..0000000000 --- a/arch/arm/mach-stm32mp/include/mach/entry.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _STM32MP_MACH_ENTRY_H_ -#define _STM32MP_MACH_ENTRY_H_ - -#include <linux/kernel.h> -#include <asm/barebox-arm.h> - -static __always_inline void stm32mp_cpu_lowlevel_init(void) -{ - unsigned long stack_top; - arm_cpu_lowlevel_init(); - - stack_top = (unsigned long)__image_end + get_runtime_offset() + 64; - stack_top = ALIGN(stack_top, 16); - arm_setup_stack(stack_top); -} - -void __noreturn stm32mp1_barebox_entry(void *boarddata); - -#endif diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h deleted file mode 100644 index 2ef8ef30c3..0000000000 --- a/arch/arm/mach-stm32mp/include/mach/revision.h +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved - */ - -#ifndef __MACH_CPUTYPE_H__ -#define __MACH_CPUTYPE_H__ - -#include <mach/bsec.h> -#include <asm/io.h> -#include <mach/stm32.h> - -/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) - * 157X: 2x Cortex-A7, Cortex-M4, CAN FD, GPU, DSI - * 153X: 2x Cortex-A7, Cortex-M4, CAN FD - * 151X: 1x Cortex-A7, Cortex-M4 - * XXXA: Cortex-A7 @ 650 MHz - * XXXC: Cortex-A7 @ 650 MHz + Secure Boot + HW Crypto - * XXXD: Cortex-A7 @ 800 MHz - * XXXF: Cortex-A7 @ 800 MHz + Secure Boot + HW Crypto - */ -#define CPU_STM32MP157Cxx 0x05000000 -#define CPU_STM32MP157Axx 0x05000001 -#define CPU_STM32MP153Cxx 0x05000024 -#define CPU_STM32MP153Axx 0x05000025 -#define CPU_STM32MP151Cxx 0x0500002E -#define CPU_STM32MP151Axx 0x0500002F -#define CPU_STM32MP157Fxx 0x05000080 -#define CPU_STM32MP157Dxx 0x05000081 -#define CPU_STM32MP153Fxx 0x050000A4 -#define CPU_STM32MP153Dxx 0x050000A5 -#define CPU_STM32MP151Fxx 0x050000AE -#define CPU_STM32MP151Dxx 0x050000AF - -/* silicon revisions */ -#define CPU_REV_A 0x1000 -#define CPU_REV_B 0x2000 -#define CPU_REV_Z 0x2001 - -int stm32mp_silicon_revision(void); -int stm32mp_cputype(void); -int stm32mp_package(void); - -#define cpu_is_stm32mp157c() (stm32mp_cputype() == CPU_STM32MP157Cxx) -#define cpu_is_stm32mp157a() (stm32mp_cputype() == CPU_STM32MP157Axx) -#define cpu_is_stm32mp153c() (stm32mp_cputype() == CPU_STM32MP153Cxx) -#define cpu_is_stm32mp153a() (stm32mp_cputype() == CPU_STM32MP153Axx) -#define cpu_is_stm32mp151c() (stm32mp_cputype() == CPU_STM32MP151Cxx) -#define cpu_is_stm32mp151a() (stm32mp_cputype() == CPU_STM32MP151Axx) - -/* DBGMCU register */ -#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) -#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) -#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) -#define DBGMCU_IDC_DEV_ID_SHIFT 0 -#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) -#define DBGMCU_IDC_REV_ID_SHIFT 16 - -#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) -#define RCC_DBGCFGR_DBGCKEN BIT(8) - -/* BSEC OTP index */ -#define BSEC_OTP_RPN 1 -#define BSEC_OTP_PKG 16 - -/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ -#define RPN_SHIFT 0 -#define RPN_MASK GENMASK(7, 0) - -static inline u32 stm32mp_read_idc(void) -{ - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - return readl(IOMEM(DBGMCU_IDC)); -} - -/* Get Device Part Number (RPN) from OTP */ -static inline int __stm32mp_get_cpu_rpn(u32 *rpn) -{ - int ret = bsec_read_field(BSEC_OTP_RPN, rpn); - if (ret) - return ret; - - *rpn = (*rpn >> RPN_SHIFT) & RPN_MASK; - return 0; -} - -static inline int __stm32mp_get_cpu_type(u32 *type) -{ - u32 id; - int ret = __stm32mp_get_cpu_rpn(type); - if (ret) - return ret; - - id = (stm32mp_read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; - *type |= id << 16; - return 0; -} - -#endif /* __MACH_CPUTYPE_H__ */ diff --git a/arch/arm/mach-stm32mp/include/mach/smc.h b/arch/arm/mach-stm32mp/include/mach/smc.h deleted file mode 100644 index 6b8e62bd53..0000000000 --- a/arch/arm/mach-stm32mp/include/mach/smc.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef __MACH_STM32_SMC_H__ -#define __MACH_STM32_SMC_H__ - -#include <linux/arm-smccc.h> - -/* Secure Service access from Non-secure */ -#define STM32_SMC_RCC 0x82001000 -#define STM32_SMC_PWR 0x82001001 -#define STM32_SMC_RTC 0x82001002 -#define STM32_SMC_BSEC 0x82001003 - -/* Register access service use for RCC/RTC/PWR */ -#define STM32_SMC_REG_WRITE 0x1 -#define STM32_SMC_REG_SET 0x2 -#define STM32_SMC_REG_CLEAR 0x3 - -static inline int stm32mp_smc(u32 svc, u8 op, u32 data1, u32 data2, u32 *val) -{ - struct arm_smccc_res res; - - arm_smccc_smc(svc, op, data1, data2, 0, 0, 0, 0, &res); - if (val) - *val = res.a1; - - return (int)res.a0; -} - -#endif diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h deleted file mode 100644 index adb898fa26..0000000000 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - */ - -#ifndef _MACH_STM32_H_ -#define _MACH_STM32_H_ - -/* - * Peripheral memory map - */ -#define STM32_RCC_BASE 0x50000000 -#define STM32_PWR_BASE 0x50001000 -#define STM32_DBGMCU_BASE 0x50081000 -#define STM32_DDRCTL_BASE 0x5A003000 -#define STM32_DDRPHY_BASE 0x5A004000 -#define STM32_BSEC_BASE 0x5C005000 -#define STM32_TZC_BASE 0x5C006000 -#define STM32_ETZPC_BASE 0x5C007000 -#define STM32_TAMP_BASE 0x5C00A000 - -#define STM32_USART1_BASE 0x5C000000 -#define STM32_USART2_BASE 0x4000E000 -#define STM32_USART3_BASE 0x4000F000 -#define STM32_UART4_BASE 0x40010000 -#define STM32_UART5_BASE 0x40011000 -#define STM32_USART6_BASE 0x44003000 -#define STM32_UART7_BASE 0x40018000 -#define STM32_UART8_BASE 0x40019000 - -#define STM32_SYSRAM_BASE 0x2FFC0000 -#define STM32_SYSRAM_SIZE SZ_256K - -#define STM32_DDR_BASE 0xC0000000 -#define STM32_DDR_SIZE SZ_1G - -#endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c index 01961ae456..2eb8b6beec 100644 --- a/arch/arm/mach-stm32mp/init.c +++ b/arch/arm/mach-stm32mp/init.c @@ -8,10 +8,10 @@ #include <common.h> #include <init.h> -#include <mach/stm32.h> -#include <mach/bsec.h> -#include <mach/revision.h> -#include <mach/bootsource.h> +#include <mach/stm32mp/stm32.h> +#include <mach/stm32mp/bsec.h> +#include <mach/stm32mp/revision.h> +#include <mach/stm32mp/bootsource.h> #include <bootsource.h> #include <dt-bindings/pinctrl/stm32-pinfunc.h> @@ -42,12 +42,9 @@ /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) -/* secure access */ -#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) -#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) /* non secure access */ -#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) -#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) +#define STM32MP13_TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) +#define STM32MP15_TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) #define TAMP_BOOT_MODE_SHIFT 8 @@ -60,9 +57,8 @@ #define FIXUP_CPU_NUM(mask) ((mask) >> 16) #define FIXUP_CPU_HZ(mask) (((mask) & GENMASK(15, 0)) * 1000UL * 1000UL) -static void setup_boot_mode(void) +static void setup_boot_mode(u32 boot_ctx) { - u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); u32 boot_mode = (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; @@ -98,31 +94,7 @@ static void setup_boot_mode(void) pr_debug("[boot_ctx=0x%x] => mode=0x%x, instance=%d\n", boot_ctx, boot_mode, instance); - bootsource_set(src); - bootsource_set_instance(instance); -} - -static int __stm32mp_cputype; -int stm32mp_cputype(void) -{ - return __stm32mp_cputype; -} - -static int __stm32mp_silicon_revision; -int stm32mp_silicon_revision(void) -{ - return __stm32mp_silicon_revision; -} - -static int __stm32mp_package; -int stm32mp_package(void) -{ - return __stm32mp_package; -} - -static u32 get_cpu_revision(void) -{ - return (stm32mp_read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; + bootsource_set_raw(src, instance); } static int get_cpu_package(u32 *pkg) @@ -140,7 +112,7 @@ static int stm32mp15_fixup_cpus(struct device_node *root, void *_ctx) unsigned long ctx = (unsigned long)_ctx; struct device_node *cpus_node, *np, *tmp; - cpus_node = of_find_node_by_name(root, "cpus"); + cpus_node = of_find_node_by_name_address(root, "cpus"); if (!cpus_node) return 0; @@ -182,127 +154,112 @@ static int stm32mp15_fixup_pkg(struct device_node *root, void *_pkg) return fixup_pinctrl(root, "st,stm32mp157-z-pinctrl", pkg); } -static int setup_cpu_type(void) +static int stm32mp15_setup_cpu_type(void) { - const char *cputypestr, *cpupkgstr, *cpurevstr; unsigned long cpufixupctx = 0, pkgfixupctx = 0; - u32 pkg; - int ret; + int cputype, package; - __stm32mp_get_cpu_type(&__stm32mp_cputype); - switch (__stm32mp_cputype) { + __stm32mp15_get_cpu_type(&cputype); + switch (cputype) { case CPU_STM32MP157Fxx: - cputypestr = "157F"; cpufixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP157Dxx: - cputypestr = "157D"; cpufixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP157Cxx: - cputypestr = "157C"; cpufixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP157Axx: - cputypestr = "157A"; cpufixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP153Fxx: - cputypestr = "153F"; cpufixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP153Dxx: - cputypestr = "153D"; cpufixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP153Cxx: - cputypestr = "153C"; cpufixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP153Axx: - cputypestr = "153A"; cpufixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP151Cxx: - cputypestr = "151C"; cpufixupctx = FIXUP_CPU_MASK(1, 650); break; case CPU_STM32MP151Axx: - cputypestr = "151A"; cpufixupctx = FIXUP_CPU_MASK(1, 650); break; case CPU_STM32MP151Fxx: - cputypestr = "151F"; cpufixupctx = FIXUP_CPU_MASK(1, 800); break; case CPU_STM32MP151Dxx: - cputypestr = "151D"; cpufixupctx = FIXUP_CPU_MASK(1, 800); break; default: - cputypestr = "????"; break; } - get_cpu_package(&__stm32mp_package ); - switch (__stm32mp_package) { + get_cpu_package(&package); + switch (package) { case PKG_AA_LBGA448: - cpupkgstr = "AA"; pkgfixupctx = STM32MP_PKG_AA; break; case PKG_AB_LBGA354: - cpupkgstr = "AB"; pkgfixupctx = STM32MP_PKG_AB; break; case PKG_AC_TFBGA361: - cpupkgstr = "AC"; pkgfixupctx = STM32MP_PKG_AC; break; case PKG_AD_TFBGA257: - cpupkgstr = "AD"; pkgfixupctx = STM32MP_PKG_AD; break; default: - cpupkgstr = "??"; break; } - __stm32mp_silicon_revision = get_cpu_revision(); - switch (__stm32mp_silicon_revision) { - case CPU_REV_A: - cpurevstr = "A"; - break; - case CPU_REV_B: - cpurevstr = "B"; - break; - case CPU_REV_Z: - cpurevstr = "Z"; - break; - default: - cpurevstr = "?"; - } - - pr_debug("cputype = 0x%x, package = 0x%x, revision = 0x%x\n", - __stm32mp_cputype, pkg, __stm32mp_silicon_revision); - pr_info("detected STM32MP%s%s Rev.%s\n", cputypestr, cpupkgstr, cpurevstr); - - if (cpufixupctx) { - ret = of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx); - if (ret) - return ret; - } + pr_debug("cputype = 0x%x, package = 0x%x\n", cputype, package); + if (cpufixupctx) + of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx); if (pkgfixupctx) - return of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx); + of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx); return 0; } +static int __st32mp_soc; + +int stm32mp_soc(void) +{ + return __st32mp_soc; +} + static int stm32mp_init(void) { - setup_cpu_type(); - setup_boot_mode(); + u32 boot_ctx; + + if (of_machine_is_compatible("st,stm32mp135")) + __st32mp_soc = 32135; + else if (of_machine_is_compatible("st,stm32mp151")) + __st32mp_soc = 32151; + else if (of_machine_is_compatible("st,stm32mp153")) + __st32mp_soc = 32153; + else if (of_machine_is_compatible("st,stm32mp157")) + __st32mp_soc = 32157; + else + return 0; + + if (__st32mp_soc == 32135) { + boot_ctx = readl(STM32MP13_TAMP_BOOT_CONTEXT); + } else { + stm32mp15_setup_cpu_type(); + boot_ctx = readl(STM32MP15_TAMP_BOOT_CONTEXT); + } + + setup_boot_mode(boot_ctx); return 0; } -core_initcall(stm32mp_init); +postcore_initcall(stm32mp_init); diff --git a/arch/arm/mach-stm32mp/stm32image.c b/arch/arm/mach-stm32mp/stm32image.c index 207df6894d..37d7c73120 100644 --- a/arch/arm/mach-stm32mp/stm32image.c +++ b/arch/arm/mach-stm32mp/stm32image.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #define pr_fmt(fmt) "stm32image: " fmt #include <bootm.h> @@ -5,6 +7,7 @@ #include <init.h> #include <memory.h> #include <linux/sizes.h> +#include <mach/stm32mp/stm32.h> #define BAREBOX_STAGE2_OFFSET 256 @@ -38,11 +41,14 @@ static int do_bootm_stm32image(struct image_data *data) static struct image_handler image_handler_stm32_image_v1_handler = { .name = "STM32 image (v1)", .bootm = do_bootm_stm32image, - .filetype = filetype_stm32_image_v1, + .filetype = filetype_stm32_image_ssbl_v1, }; static int stm32mp_register_stm32image_image_handler(void) { + if (!stm32mp_soc()) + return 0; + return register_image_handler(&image_handler_stm32_image_v1_handler); } late_initcall(stm32mp_register_stm32image_image_handler); |