diff options
Diffstat (limited to 'arch/arm/mach-stm32mp')
-rw-r--r-- | arch/arm/mach-stm32mp/Kconfig | 10 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/include/mach/debug_ll.h | 28 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/include/mach/stm32.h | 35 |
4 files changed, 74 insertions, 0 deletions
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig new file mode 100644 index 0000000000..bcf7293c46 --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig @@ -0,0 +1,10 @@ +if ARCH_STM32MP + +config ARCH_STM32MP1157 + bool + +config MACH_STM32MP157C_DK2 + select ARCH_STM32MP1157 + bool "STM32MP157C-DK2 board" + +endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile new file mode 100644 index 0000000000..16a218658a --- /dev/null +++ b/arch/arm/mach-stm32mp/Makefile @@ -0,0 +1 @@ +obj- := __dummy__.o diff --git a/arch/arm/mach-stm32mp/include/mach/debug_ll.h b/arch/arm/mach-stm32mp/include/mach/debug_ll.h new file mode 100644 index 0000000000..99fedb91fe --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/debug_ll.h @@ -0,0 +1,28 @@ +#ifndef __MACH_STM32MP1_DEBUG_LL_H +#define __MACH_STM32MP1_DEBUG_LL_H + +#include <io.h> +#include <mach/stm32.h> + +#define DEBUG_LL_UART_ADDR STM32_UART4_BASE + +#define CR1_OFFSET 0x00 +#define CR3_OFFSET 0x08 +#define BRR_OFFSET 0x0c +#define ISR_OFFSET 0x1c +#define ICR_OFFSET 0x20 +#define RDR_OFFSET 0x24 +#define TDR_OFFSET 0x28 + +#define USART_ISR_TXE BIT(7) + +static inline void PUTC_LL(int c) +{ + void __iomem *base = IOMEM(DEBUG_LL_UART_ADDR); + + writel(c, base + TDR_OFFSET); + + while ((readl(base + ISR_OFFSET) & USART_ISR_TXE) == 0); +} + +#endif /* __MACH_STM32MP1_DEBUG_LL_H */ diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h new file mode 100644 index 0000000000..f9bdb788b9 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef _MACH_STM32_H_ +#define _MACH_STM32_H_ + +/* + * Peripheral memory map + */ +#define STM32_RCC_BASE 0x50000000 +#define STM32_PWR_BASE 0x50001000 +#define STM32_DBGMCU_BASE 0x50081000 +#define STM32_BSEC_BASE 0x5C005000 +#define STM32_TZC_BASE 0x5C006000 +#define STM32_ETZPC_BASE 0x5C007000 +#define STM32_TAMP_BASE 0x5C00A000 + +#define STM32_USART1_BASE 0x5C000000 +#define STM32_USART2_BASE 0x4000E000 +#define STM32_USART3_BASE 0x4000F000 +#define STM32_UART4_BASE 0x40010000 +#define STM32_UART5_BASE 0x40011000 +#define STM32_USART6_BASE 0x44003000 +#define STM32_UART7_BASE 0x40018000 +#define STM32_UART8_BASE 0x40019000 + +#define STM32_SYSRAM_BASE 0x2FFC0000 +#define STM32_SYSRAM_SIZE SZ_256K + +#define STM32_DDR_BASE 0xC0000000 +#define STM32_DDR_SIZE SZ_1G + +#endif /* _MACH_STM32_H_ */ |