diff options
Diffstat (limited to 'arch/arm/mach-tegra')
20 files changed, 31 insertions, 1392 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 160732fbef..cc256f584a 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,12 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + if ARCH_TEGRA config ARCH_TEXT_BASE hex default 0x0 -config BOARDINFO - default "" - # --------------------------------------------------------- config ARCH_TEGRA_2x_SOC diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 7547951752..ddc029bda2 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,5 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t -CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t +CFLAGS_tegra_avp_init.pbl.o := -mcpu=arm7tdmi -march=armv4t lwl-y += tegra_avp_init.o lwl-y += tegra_maincomplex_init.o obj-y += tegra20.o diff --git a/arch/arm/mach-tegra/include/mach/debug_ll.h b/arch/arm/mach-tegra/include/mach/debug_ll.h deleted file mode 100644 index 290ad5806f..0000000000 --- a/arch/arm/mach-tegra/include/mach/debug_ll.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com> - * - * This file is part of barebox. - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/** @file - * This File contains declaration for early output support - */ -#ifndef __INCLUDE_ARCH_DEBUG_LL_H__ -#define __INCLUDE_ARCH_DEBUG_LL_H__ - -#include <asm/io.h> -#include <mach/iomap.h> - -#define DEBUG_LL_UART_ADDR TEGRA_UARTA_BASE -#define DEBUG_LL_UART_RSHFT 2 - -#define rbr (0 << DEBUG_LL_UART_RSHFT) -#define lsr (5 << DEBUG_LL_UART_RSHFT) -#define LSR_THRE 0x20 /* Xmit holding register empty */ - -static inline void PUTC_LL(char ch) -{ - while (!(__raw_readb(DEBUG_LL_UART_ADDR + lsr) & LSR_THRE)) - ; - - __raw_writeb(ch, DEBUG_LL_UART_ADDR + rbr); -} - -#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */ diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h deleted file mode 100644 index bbe6ae6be6..0000000000 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/iomap.h - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross <ccross@google.com> - * Erik Gilling <konkers@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_IOMAP_H -#define __MACH_TEGRA_IOMAP_H - -#include <linux/sizes.h> - -#define TEGRA_IRAM_BASE 0x40000000 -#define TEGRA_IRAM_SIZE SZ_256K - -#define TEGRA_HOST1X_BASE 0x50000000 -#define TEGRA_HOST1X_SIZE 0x24000 - -#define TEGRA_ARM_PERIF_BASE 0x50040000 -#define TEGRA_ARM_PERIF_SIZE SZ_8K - -#define TEGRA_ARM_PL310_BASE 0x50043000 -#define TEGRA_ARM_PL310_SIZE SZ_4K - -#define TEGRA_ARM_INT_DIST_BASE 0x50041000 -#define TEGRA_ARM_INT_DIST_SIZE SZ_4K - -#define TEGRA_MPE_BASE 0x54040000 -#define TEGRA_MPE_SIZE SZ_256K - -#define TEGRA_VI_BASE 0x54080000 -#define TEGRA_VI_SIZE SZ_256K - -#define TEGRA_ISP_BASE 0x54100000 -#define TEGRA_ISP_SIZE SZ_256K - -#define TEGRA_DISPLAY_BASE 0x54200000 -#define TEGRA_DISPLAY_SIZE SZ_256K - -#define TEGRA_DISPLAY2_BASE 0x54240000 -#define TEGRA_DISPLAY2_SIZE SZ_256K - -#define TEGRA_HDMI_BASE 0x54280000 -#define TEGRA_HDMI_SIZE SZ_256K - -#define TEGRA_GART_BASE 0x58000000 -#define TEGRA_GART_SIZE SZ_32M - -#define TEGRA_UP_TAG_BASE 0x60000000 -#define TEGRA_UP_TAG_SIZE SZ_4K - -#define TEGRA_RES_SEMA_BASE 0x60001000 -#define TEGRA_RES_SEMA_SIZE SZ_4K - -#define TEGRA_HDMI_BASE 0x54280000 -#define TEGRA_HDMI_SIZE SZ_256K - -#define TEGRA_GART_BASE 0x58000000 -#define TEGRA_GART_SIZE SZ_32M - -#define TEGRA_RES_SEMA_BASE 0x60001000 -#define TEGRA_RES_SEMA_SIZE SZ_4K - -#define TEGRA_ARB_SEMA_BASE 0x60002000 -#define TEGRA_ARB_SEMA_SIZE SZ_4K - -#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 -#define TEGRA_PRIMARY_ICTLR_SIZE 64 - -#define TEGRA_ARBGNT_ICTLR_BASE 0x60004040 -#define TEGRA_ARBGNT_ICTLR_SIZE 192 - -#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100 -#define TEGRA_SECONDARY_ICTLR_SIZE 64 - -#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200 -#define TEGRA_TERTIARY_ICTLR_SIZE 64 - -#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300 -#define TEGRA_QUATERNARY_ICTLR_SIZE 64 - -#define TEGRA_TMR1_BASE 0x60005000 -#define TEGRA_TMR1_SIZE 8 - -#define TEGRA_TMR2_BASE 0x60005008 -#define TEGRA_TMR2_SIZE 8 - -#define TEGRA_TMRUS_BASE 0x60005010 -#define TEGRA_TMRUS_SIZE 64 - -#define TEGRA_TMR3_BASE 0x60005050 -#define TEGRA_TMR3_SIZE 8 - -#define TEGRA_TMR4_BASE 0x60005058 -#define TEGRA_TMR4_SIZE 8 - -#define TEGRA_CLK_RESET_BASE 0x60006000 -#define TEGRA_CLK_RESET_SIZE SZ_4K - -#define TEGRA_FLOW_CTRL_BASE 0x60007000 -#define TEGRA_FLOW_CTRL_SIZE 20 - -#define TEGRA_AHB_DMA_BASE 0x60008000 -#define TEGRA_AHB_DMA_SIZE SZ_4K - -#define TEGRA_AHB_DMA_CH0_BASE 0x60009000 -#define TEGRA_AHB_DMA_CH0_SIZE 32 - -#define TEGRA_APB_DMA_BASE 0x6000A000 -#define TEGRA_APB_DMA_SIZE SZ_4K - -#define TEGRA_APB_DMA_CH0_BASE 0x6000B000 -#define TEGRA_APB_DMA_CH0_SIZE 32 - -#define TEGRA_AHB_GIZMO_BASE 0x6000C004 -#define TEGRA_AHB_GIZMO_SIZE 0x10C - -#define TEGRA_STATMON_BASE 0x6000C400 -#define TEGRA_STATMON_SIZE SZ_1K - -#define TEGRA_GPIO_BASE 0x6000D000 -#define TEGRA_GPIO_SIZE SZ_4K - -#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 -#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K - -#define TEGRA_VDE_BASE 0x6001A000 -#define TEGRA_VDE_SIZE (SZ_8K + SZ_4K - SZ_256) - -#define TEGRA_APB_MISC_BASE 0x70000000 -#define TEGRA_APB_MISC_SIZE SZ_4K - -#define TEGRA_APB_MISC_DAS_BASE 0x70000c00 -#define TEGRA_APB_MISC_DAS_SIZE SZ_128 - -#define TEGRA_AC97_BASE 0x70002000 -#define TEGRA_AC97_SIZE SZ_512 - -#define TEGRA_SPDIF_BASE 0x70002400 -#define TEGRA_SPDIF_SIZE SZ_512 - -#define TEGRA_I2S1_BASE 0x70002800 -#define TEGRA_I2S1_SIZE SZ_256 - -#define TEGRA_I2S2_BASE 0x70002A00 -#define TEGRA_I2S2_SIZE SZ_256 - -#define TEGRA_UARTA_BASE 0x70006000 -#define TEGRA_UARTA_SIZE 64 - -#define TEGRA_UARTB_BASE 0x70006040 -#define TEGRA_UARTB_SIZE 64 - -#define TEGRA_UARTC_BASE 0x70006200 -#define TEGRA_UARTC_SIZE SZ_256 - -#define TEGRA_UARTD_BASE 0x70006300 -#define TEGRA_UARTD_SIZE SZ_256 - -#define TEGRA_UARTE_BASE 0x70006400 -#define TEGRA_UARTE_SIZE SZ_256 - -#define TEGRA_NAND_BASE 0x70008000 -#define TEGRA_NAND_SIZE SZ_256 - -#define TEGRA_HSMMC_BASE 0x70008500 -#define TEGRA_HSMMC_SIZE SZ_256 - -#define TEGRA_SNOR_BASE 0x70009000 -#define TEGRA_SNOR_SIZE SZ_4K - -#define TEGRA_PWFM_BASE 0x7000A000 -#define TEGRA_PWFM_SIZE SZ_256 - -#define TEGRA_PWFM0_BASE 0x7000A000 -#define TEGRA_PWFM0_SIZE 4 - -#define TEGRA_PWFM1_BASE 0x7000A010 -#define TEGRA_PWFM1_SIZE 4 - -#define TEGRA_PWFM2_BASE 0x7000A020 -#define TEGRA_PWFM2_SIZE 4 - -#define TEGRA_PWFM3_BASE 0x7000A030 -#define TEGRA_PWFM3_SIZE 4 - -#define TEGRA_MIPI_BASE 0x7000B000 -#define TEGRA_MIPI_SIZE SZ_256 - -#define TEGRA_I2C_BASE 0x7000C000 -#define TEGRA_I2C_SIZE SZ_256 - -#define TEGRA_TWC_BASE 0x7000C100 -#define TEGRA_TWC_SIZE SZ_256 - -#define TEGRA_SPI_BASE 0x7000C380 -#define TEGRA_SPI_SIZE 48 - -#define TEGRA_I2C2_BASE 0x7000C400 -#define TEGRA_I2C2_SIZE SZ_256 - -#define TEGRA_I2C3_BASE 0x7000C500 -#define TEGRA_I2C3_SIZE SZ_256 - -#define TEGRA_OWR_BASE 0x7000C600 -#define TEGRA_OWR_SIZE 80 - -#define TEGRA_DVC_BASE 0x7000D000 -#define TEGRA_DVC_SIZE SZ_512 - -#define TEGRA_SPI1_BASE 0x7000D400 -#define TEGRA_SPI1_SIZE SZ_512 - -#define TEGRA_SPI2_BASE 0x7000D600 -#define TEGRA_SPI2_SIZE SZ_512 - -#define TEGRA_SPI3_BASE 0x7000D800 -#define TEGRA_SPI3_SIZE SZ_512 - -#define TEGRA_SPI4_BASE 0x7000DA00 -#define TEGRA_SPI4_SIZE SZ_512 - -#define TEGRA_RTC_BASE 0x7000E000 -#define TEGRA_RTC_SIZE SZ_256 - -#define TEGRA_KBC_BASE 0x7000E200 -#define TEGRA_KBC_SIZE SZ_256 - -#define TEGRA_PMC_BASE 0x7000E400 -#define TEGRA_PMC_SIZE SZ_256 - -#define TEGRA_MC_BASE 0x7000F000 -#define TEGRA_MC_SIZE SZ_1K - -#define TEGRA_EMC_BASE 0x7000F400 -#define TEGRA_EMC_SIZE SZ_1K - -#define TEGRA_FUSE_BASE 0x7000F800 -#define TEGRA_FUSE_SIZE SZ_1K - -#define TEGRA_KFUSE_BASE 0x7000FC00 -#define TEGRA_KFUSE_SIZE SZ_1K - -#define TEGRA_CSITE_BASE 0x70040000 -#define TEGRA_CSITE_SIZE SZ_256K - -#define TEGRA_SYSCTR0_BASE 0x700F0000 -#define TEGRA_SYSCTR0_SIZE SZ_64K - -#define TEGRA_USB_BASE 0xC5000000 -#define TEGRA_USB_SIZE SZ_16K - -#define TEGRA_USB2_BASE 0xC5004000 -#define TEGRA_USB2_SIZE SZ_16K - -#define TEGRA_USB3_BASE 0xC5008000 -#define TEGRA_USB3_SIZE SZ_16K - -#define TEGRA_SDMMC1_BASE 0xC8000000 -#define TEGRA_SDMMC1_SIZE SZ_512 - -#define TEGRA_SDMMC2_BASE 0xC8000200 -#define TEGRA_SDMMC2_SIZE SZ_512 - -#define TEGRA_SDMMC3_BASE 0xC8000400 -#define TEGRA_SDMMC3_SIZE SZ_512 - -#define TEGRA_SDMMC4_BASE 0xC8000600 -#define TEGRA_SDMMC4_SIZE SZ_512 - -#if defined(CONFIG_TEGRA_DEBUG_UART_NONE) -# define TEGRA_DEBUG_UART_BASE 0 -#elif defined(CONFIG_TEGRA_DEBUG_UARTA) -# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE -#elif defined(CONFIG_TEGRA_DEBUG_UARTB) -# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE -#elif defined(CONFIG_TEGRA_DEBUG_UARTC) -# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE -#elif defined(CONFIG_TEGRA_DEBUG_UARTD) -# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE -#elif defined(CONFIG_TEGRA_DEBUG_UARTE) -# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE -#endif - -#endif diff --git a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h deleted file mode 100644 index 1deae4e565..0000000000 --- a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/compiler.h> -#include "mach/tegra20-car.h" -#include "mach/lowlevel.h" - -static __always_inline -void tegra_dvc_init(void) -{ - int div; - u32 reg; - - /* reset DVC controller and enable clock */ - writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_SET); - reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H); - reg |= CRC_CLK_OUT_ENB_H_DVC; - writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H); - - /* set DVC I2C clock source to CLK_M and aim for 100kHz I2C clock */ - div = ((tegra_get_osc_clock() * 3) >> 22) - 1; - writel((div) | (3 << 30), - TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_DVC); - - /* clear DVC reset */ - tegra_ll_delay_usec(3); - writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_CLR); -} - -static __always_inline -void tegra124_dvc_pinmux(void) -{ - u32 val; - - /* disable tristate for pin PWR_I2C_SCL_PZ6 */ - val = readl(TEGRA_APB_MISC_BASE + 0x32b4); - val &= ~(1 << 4); - writel(val, TEGRA_APB_MISC_BASE + 0x32b4); - - /* disable tristate for pin PWR_I2C_SDA_PZ7 */ - val = readl(TEGRA_APB_MISC_BASE + 0x32b8); - val &= ~(1 << 4); - writel(val, TEGRA_APB_MISC_BASE + 0x32b8); -} - -#define TEGRA_I2C_CNFG 0x00 -#define TEGRA_I2C_CMD_ADDR0 0x04 -#define TEGRA_I2C_CMD_DATA1 0x0c -#define TEGRA_I2C_SEND_2_BYTES 0x0a02 - -static __always_inline -void tegra_dvc_write_addr(u32 addr, u32 config) -{ - writel(addr, TEGRA_DVC_BASE + TEGRA_I2C_CMD_ADDR0); - writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG); -} - -static __always_inline -void tegra_dvc_write_data(u32 data, u32 config) -{ - writel(data, TEGRA_DVC_BASE + TEGRA_I2C_CMD_DATA1); - writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG); -} - -static __always_inline -void tegra30_tps65911_cpu_rail_enable(void) -{ - tegra_dvc_write_addr(0x5a, 2); - /* reg 28, 600mV + (35-3) * 12,5mV = 1,0V */ - tegra_dvc_write_data(0x2328, TEGRA_I2C_SEND_2_BYTES); - tegra_ll_delay_usec(1000); - /* reg 27, VDDctrl enable */ - tegra_dvc_write_data(0x0127, TEGRA_I2C_SEND_2_BYTES); - tegra_ll_delay_usec(10 * 1000); -} - -static __always_inline -void tegra30_tps62366a_ramp_vddcore(void) -{ - tegra_dvc_write_addr(0xc0, 2); - /* set VDDcore to 1,2V */ - tegra_dvc_write_data(0x4601, TEGRA_I2C_SEND_2_BYTES); - tegra_ll_delay_usec(1000); -} - -static __always_inline -void tegra30_tps62361b_ramp_vddcore(void) -{ - tegra_dvc_write_addr(0xc0, 2); - /* set VDDcore to 1,2V */ - tegra_dvc_write_data(0x4603, TEGRA_I2C_SEND_2_BYTES); - tegra_ll_delay_usec(1000); -} - -static __always_inline -void tegra124_as3722_enable_essential_rails(u32 sd0voltage) -{ - /* - * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus. - * First set VDD to 1.0V, then enable the VDD regulator. - */ - tegra_dvc_write_addr(0x80, 2); - tegra_dvc_write_data(sd0voltage | 0x00, TEGRA_I2C_SEND_2_BYTES); - tegra_ll_delay_usec(10 * 1000); - - /* - * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus. - * First set VDD to 1.0V, then enable the VDD regulator. - */ - tegra_dvc_write_addr(0x80, 2); - tegra_dvc_write_data(0x2800 | 0x06, TEGRA_I2C_SEND_2_BYTES); - tegra_ll_delay_usec(10 * 1000); - - /* - * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus. - * First set VDD to 1.2V, then enable the VDD regulator. - */ - tegra_dvc_write_addr(0x80, 2); - tegra_dvc_write_data(0x1000 | 0x12, TEGRA_I2C_SEND_2_BYTES); - tegra_ll_delay_usec(10 * 1000); - - /* - * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus. - * First set it to bypass 3.3V straight thru, then enable the regulator - * - * NOTE: We do this early because doing it later seems to hose the CPU - * power rail/partition startup. Need to debug. - */ - tegra_dvc_write_addr(0x80, 2); - tegra_dvc_write_data(0x3f00 | 0x16, TEGRA_I2C_SEND_2_BYTES); - tegra_ll_delay_usec(10 * 1000); -} diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h deleted file mode 100644 index 31f99eb175..0000000000 --- a/arch/arm/mach-tegra/include/mach/lowlevel.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/** - * @file - * @brief Boot informations provided by the Tegra SoC and it's BootROM. All - * accessor functions are a header only implementations, as they are meant to - * be used by both the main CPU complex (ARMv7) and the AVP (ARMv4). - */ - -#ifndef __TEGRA_LOWLEVEL_H -#define __TEGRA_LOWLEVEL_H - -#include <asm/barebox-arm.h> -#include <linux/compiler.h> -#include <linux/sizes.h> -#include <io.h> -#include <mach/iomap.h> - -/* Bootinfotable */ - -/* location of the BCT in IRAM */ -#define NV_BIT_BCTPTR_T20 0x3c -#define NV_BIT_BCTPTR_T114 0x4c - -/* ODM data */ -#define BCT_ODMDATA_OFFSET 12 /* offset from the _end_ of the BCT */ - -#define T20_ODMDATA_RAMSIZE_SHIFT 28 -#define T20_ODMDATA_RAMSIZE_MASK (3 << T20_ODMDATA_RAMSIZE_SHIFT) -#define T30_ODMDATA_RAMSIZE_MASK (0xf << T20_ODMDATA_RAMSIZE_SHIFT) -#define T20_ODMDATA_UARTTYPE_SHIFT 18 -#define T20_ODMDATA_UARTTYPE_MASK (3 << T20_ODMDATA_UARTTYPE_SHIFT) -#define T20_ODMDATA_UARTID_SHIFT 15 -#define T20_ODMDATA_UARTID_MASK (7 << T20_ODMDATA_UARTID_SHIFT) - -/* chip ID */ -#define APB_MISC_HIDREV 0x804 -#define HIDREV_CHIPID_SHIFT 8 -#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) - -enum tegra_chiptype { - TEGRA_UNK_REV = -1, - TEGRA20 = 0, - TEGRA30 = 1, - TEGRA114 = 2, - TEGRA124 = 3, -}; - -static __always_inline -u32 tegra_read_chipid(void) -{ - return readl(TEGRA_APB_MISC_BASE + APB_MISC_HIDREV); -} - -static __always_inline -enum tegra_chiptype tegra_get_chiptype(void) -{ - u32 hidrev; - - hidrev = readl(TEGRA_APB_MISC_BASE + APB_MISC_HIDREV); - - switch ((hidrev & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT) { - case 0x20: - return TEGRA20; - case 0x30: - return TEGRA30; - case 0x40: - return TEGRA124; - default: - return TEGRA_UNK_REV; - } -} - -static __always_inline -u32 tegra_get_odmdata(void) -{ - u32 bctptr_offset, bctptr, odmdata_offset; - enum tegra_chiptype chiptype = tegra_get_chiptype(); - - switch(chiptype) { - case TEGRA20: - bctptr_offset = NV_BIT_BCTPTR_T20; - odmdata_offset = 4068; - break; - case TEGRA30: - bctptr_offset = NV_BIT_BCTPTR_T20; - odmdata_offset = 6116; - break; - case TEGRA114: - bctptr_offset = NV_BIT_BCTPTR_T114; - odmdata_offset = 1752; - break; - case TEGRA124: - bctptr_offset = NV_BIT_BCTPTR_T114; - odmdata_offset = 1704; - break; - default: - return 0; - } - - bctptr = __raw_readl(TEGRA_IRAM_BASE + bctptr_offset); - - return __raw_readl(bctptr + odmdata_offset); -} - -static __always_inline -int tegra_get_num_cores(void) -{ - switch (tegra_get_chiptype()) { - case TEGRA20: - return 2; - case TEGRA30: - case TEGRA124: - return 4; - default: - return 0; - } -} - -/* Runtime data */ -static __always_inline -int tegra_cpu_is_maincomplex(void) -{ - u32 tag0; - - tag0 = readl(TEGRA_UP_TAG_BASE); - - return (tag0 & 0xff) == 0x55; -} - -static __always_inline -uint32_t tegra20_get_ramsize(void) -{ - switch ((tegra_get_odmdata() & T20_ODMDATA_RAMSIZE_MASK) >> - T20_ODMDATA_RAMSIZE_SHIFT) { - case 1: - return SZ_256M; - default: - case 2: - return SZ_512M; - case 3: - return SZ_1G; - } -} - -static __always_inline -uint32_t tegra30_get_ramsize(void) -{ - switch ((tegra_get_odmdata() & T30_ODMDATA_RAMSIZE_MASK) >> - T20_ODMDATA_RAMSIZE_SHIFT) { - case 0: - case 1: - default: - return SZ_256M; - case 2: - return SZ_512M; - case 3: - return SZ_512M + SZ_256M; - case 4: - return SZ_1G; - case 8: - return SZ_2G - SZ_1M; - } -} - -#define CRC_OSC_CTRL 0x050 -#define CRC_OSC_CTRL_OSC_FREQ_SHIFT 30 -#define CRC_OSC_CTRL_OSC_FREQ_MASK (0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT) - -static __always_inline -int tegra_get_osc_clock(void) -{ - u32 osc_ctrl = readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL); - - switch ((osc_ctrl & CRC_OSC_CTRL_OSC_FREQ_MASK) >> - CRC_OSC_CTRL_OSC_FREQ_SHIFT) { - case 0: - return 13000000; - case 1: - return 19200000; - case 2: - return 12000000; - case 3: - return 26000000; - default: - return 0; - } -} - -#define TIMER_CNTR_1US 0x00 -#define TIMER_USEC_CFG 0x04 - -static __always_inline -void tegra_ll_delay_setup(void) -{ - u32 reg; - - /* - * calibrate timer to run at 1MHz - * TIMERUS_USEC_CFG selects the scale down factor with bits [0:7] - * representing the divisor and bits [8:15] representing the dividend - * each in n+1 form. - */ - switch (tegra_get_osc_clock()) { - case 12000000: - reg = 0x000b; - break; - case 13000000: - reg = 0x000c; - break; - case 19200000: - reg = 0x045f; - break; - case 26000000: - reg = 0x0019; - break; - default: - reg = 0; - break; - } - - writel(reg, TEGRA_TMRUS_BASE + TIMER_USEC_CFG); -} - -static __always_inline -void tegra_ll_delay_usec(int delay) -{ - int timeout = (int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) + delay; - - while ((int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) - timeout < 0); -} - -/* reset vector for the AVP, to be called from board reset vector */ -void tegra_avp_reset_vector(void); - -/* reset vector for the main CPU complex */ -void tegra_maincomplex_entry(char *fdt); - -static __always_inline -void tegra_cpu_lowlevel_setup(char *fdt) -{ - uint32_t r; - - /* set the cpu to SVC32 mode */ - __asm__ __volatile__("mrs %0, cpsr":"=r"(r)); - r &= ~0x1f; - r |= 0xd3; - __asm__ __volatile__("msr cpsr, %0" : : "r"(r)); - - arm_setup_stack(TEGRA_IRAM_BASE + SZ_256K); - - if (tegra_cpu_is_maincomplex()) - tegra_maincomplex_entry(fdt + get_runtime_offset()); - - tegra_ll_delay_setup(); -} - -#endif /* __TEGRA_LOWLEVEL_H */ diff --git a/arch/arm/mach-tegra/include/mach/tegra-bbu.h b/arch/arm/mach-tegra/include/mach/tegra-bbu.h deleted file mode 100644 index 32e2861ac6..0000000000 --- a/arch/arm/mach-tegra/include/mach/tegra-bbu.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2015 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <bbu.h> - -#ifdef CONFIG_BAREBOX_UPDATE -int tegra_bbu_register_emmc_handler(const char *name, char *devicefile, - unsigned long flags); -#else -static int tegra_bbu_register_emmc_handler(const char *name, char *devicefile, - unsigned long flags) -{ - return 0; -}; -#endif diff --git a/arch/arm/mach-tegra/include/mach/tegra-powergate.h b/arch/arm/mach-tegra/include/mach/tegra-powergate.h deleted file mode 100644 index e32250a7fa..0000000000 --- a/arch/arm/mach-tegra/include/mach/tegra-powergate.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2010 Google, Inc - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _MACH_TEGRA_POWERGATE_H_ -#define _MACH_TEGRA_POWERGATE_H_ - -struct clk; -struct reset_control; - -#define TEGRA_POWERGATE_CPU 0 -#define TEGRA_POWERGATE_3D 1 -#define TEGRA_POWERGATE_VENC 2 -#define TEGRA_POWERGATE_PCIE 3 -#define TEGRA_POWERGATE_VDEC 4 -#define TEGRA_POWERGATE_L2 5 -#define TEGRA_POWERGATE_MPE 6 -#define TEGRA_POWERGATE_HEG 7 -#define TEGRA_POWERGATE_SATA 8 -#define TEGRA_POWERGATE_CPU1 9 -#define TEGRA_POWERGATE_CPU2 10 -#define TEGRA_POWERGATE_CPU3 11 -#define TEGRA_POWERGATE_CELP 12 -#define TEGRA_POWERGATE_3D1 13 -#define TEGRA_POWERGATE_CPU0 14 -#define TEGRA_POWERGATE_C0NC 15 -#define TEGRA_POWERGATE_C1NC 16 -#define TEGRA_POWERGATE_SOR 17 -#define TEGRA_POWERGATE_DIS 18 -#define TEGRA_POWERGATE_DISB 19 -#define TEGRA_POWERGATE_XUSBA 20 -#define TEGRA_POWERGATE_XUSBB 21 -#define TEGRA_POWERGATE_XUSBC 22 -#define TEGRA_POWERGATE_VIC 23 -#define TEGRA_POWERGATE_IRAM 24 - -#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D - -#define TEGRA_IO_RAIL_CSIA 0 -#define TEGRA_IO_RAIL_CSIB 1 -#define TEGRA_IO_RAIL_DSI 2 -#define TEGRA_IO_RAIL_MIPI_BIAS 3 -#define TEGRA_IO_RAIL_PEX_BIAS 4 -#define TEGRA_IO_RAIL_PEX_CLK1 5 -#define TEGRA_IO_RAIL_PEX_CLK2 6 -#define TEGRA_IO_RAIL_USB0 9 -#define TEGRA_IO_RAIL_USB1 10 -#define TEGRA_IO_RAIL_USB2 11 -#define TEGRA_IO_RAIL_USB_BIAS 12 -#define TEGRA_IO_RAIL_NAND 13 -#define TEGRA_IO_RAIL_UART 14 -#define TEGRA_IO_RAIL_BB 15 -#define TEGRA_IO_RAIL_AUDIO 17 -#define TEGRA_IO_RAIL_HSIC 19 -#define TEGRA_IO_RAIL_COMP 22 -#define TEGRA_IO_RAIL_HDMI 28 -#define TEGRA_IO_RAIL_PEX_CNTRL 32 -#define TEGRA_IO_RAIL_SDMMC1 33 -#define TEGRA_IO_RAIL_SDMMC3 34 -#define TEGRA_IO_RAIL_SDMMC4 35 -#define TEGRA_IO_RAIL_CAM 36 -#define TEGRA_IO_RAIL_RES 37 -#define TEGRA_IO_RAIL_HV 38 -#define TEGRA_IO_RAIL_DSIB 39 -#define TEGRA_IO_RAIL_DSIC 40 -#define TEGRA_IO_RAIL_DSID 41 -#define TEGRA_IO_RAIL_CSIE 44 -#define TEGRA_IO_RAIL_LVDS 57 -#define TEGRA_IO_RAIL_SYS_DDC 58 - -int tegra_powergate_is_powered(int id); -int tegra_powergate_power_on(int id); -int tegra_powergate_power_off(int id); -int tegra_powergate_remove_clamping(int id); - -/* Must be called with clk disabled, and returns with clk enabled */ -int tegra_powergate_sequence_power_up(int id, struct clk *clk, - struct reset_control *rst); - -#endif /* _MACH_TEGRA_POWERGATE_H_ */ diff --git a/arch/arm/mach-tegra/include/mach/tegra114-sysctr.h b/arch/arm/mach-tegra/include/mach/tegra114-sysctr.h deleted file mode 100644 index 45d17c4d97..0000000000 --- a/arch/arm/mach-tegra/include/mach/tegra114-sysctr.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Register definitions */ -#define TEGRA_SYSCTR0_CNTCR 0x00 -#define TEGRA_SYSCTR0_CNTCR_ENABLE (1 << 0) -#define TEGRA_SYSCTR0_CNTCR_HDBG (1 << 1) - -#define TEGRA_SYSCTR0_CNTSR 0x04 - -#define TEGRA_SYSCTR0_CNTCV0 0x08 - -#define TEGRA_SYSCTR0_CNTCV1 0x0c - -#define TEGRA_SYSCTR0_CNTFID0 0x20 - -#define TEGRA_SYSCTR0_CNTFID1 0x24 diff --git a/arch/arm/mach-tegra/include/mach/tegra124-car.h b/arch/arm/mach-tegra/include/mach/tegra124-car.h deleted file mode 100644 index 1fb924d9f4..0000000000 --- a/arch/arm/mach-tegra/include/mach/tegra124-car.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Register definitions */ -#define CRC_PLLX_MISC_3 0x518 -#define CRC_PLLX_MISC_3_IDDQ (1 << 3) diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h deleted file mode 100644 index 5a35f21c1f..0000000000 --- a/arch/arm/mach-tegra/include/mach/tegra20-car.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Register definitions */ -#define CRC_CLK_OUT_ENB_L 0x010 -#define CRC_CLK_OUT_ENB_L_CACHE2 (1 << 31) -#define CRC_CLK_OUT_ENB_L_VCP (1 << 29) -#define CRC_CLK_OUT_ENB_L_HOST1X (1 << 28) -#define CRC_CLK_OUT_ENB_L_DISP1 (1 << 27) -#define CRC_CLK_OUT_ENB_L_DISP2 (1 << 26) -#define CRC_CLK_OUT_ENB_L_IDE (1 << 25) -#define CRC_CLK_OUT_ENB_L_3D (1 << 24) -#define CRC_CLK_OUT_ENB_L_ISP (1 << 23) -#define CRC_CLK_OUT_ENB_L_USBD (1 << 22) -#define CRC_CLK_OUT_ENB_L_2D (1 << 21) -#define CRC_CLK_OUT_ENB_L_VI (1 << 20) -#define CRC_CLK_OUT_ENB_L_EPP (1 << 19) -#define CRC_CLK_OUT_ENB_L_I2S2 (1 << 18) -#define CRC_CLK_OUT_ENB_L_PWM (1 << 17) -#define CRC_CLK_OUT_ENB_L_TWC (1 << 16) -#define CRC_CLK_OUT_ENB_L_SDMMC4 (1 << 15) -#define CRC_CLK_OUT_ENB_L_SDMMC1 (1 << 14) -#define CRC_CLK_OUT_ENB_L_NDFLASH (1 << 13) -#define CRC_CLK_OUT_ENB_L_I2C1 (1 << 12) -#define CRC_CLK_OUT_ENB_L_I2S1 (1 << 11) -#define CRC_CLK_OUT_ENB_L_SPDIF (1 << 10) -#define CRC_CLK_OUT_ENB_L_SDMMC2 (1 << 9) -#define CRC_CLK_OUT_ENB_L_GPIO (1 << 8) -#define CRC_CLK_OUT_ENB_L_UART2 (1 << 7) -#define CRC_CLK_OUT_ENB_L_UART1 (1 << 6) -#define CRC_CLK_OUT_ENB_L_TMR (1 << 5) -#define CRC_CLK_OUT_ENB_L_RTC (1 << 4) -#define CRC_CLK_OUT_ENB_L_AC97 (1 << 3) -#define CRC_CLK_OUT_ENB_L_CPU (1 << 0) - -#define CRC_CLK_OUT_ENB_H 0x014 -#define CRC_CLK_OUT_ENB_H_DVC (1 << 15) - -#define CRC_CLK_OUT_ENB_U 0x018 - -#define CRC_CCLK_BURST_POLICY 0x020 -#define CRC_CCLK_BURST_POLICY_SYS_STATE_SHIFT 28 -#define CRC_CCLK_BURST_POLICY_SYS_STATE_FIQ 8 -#define CRC_CCLK_BURST_POLICY_SYS_STATE_IRQ 4 -#define CRC_CCLK_BURST_POLICY_SYS_STATE_RUN 2 -#define CRC_CCLK_BURST_POLICY_SYS_STATE_IDLE 1 -#define CRC_CCLK_BURST_POLICY_SYS_STATE_STDBY 0 -#define CRC_CCLK_BURST_POLICY_FIQ_SRC_SHIFT 12 -#define CRC_CCLK_BURST_POLICY_IRQ_SRC_SHIFT 8 -#define CRC_CCLK_BURST_POLICY_RUN_SRC_SHIFT 4 -#define CRC_CCLK_BURST_POLICY_IDLE_SRC_SHIFT 0 -#define CRC_CCLK_BURST_POLICY_SRC_CLKM 0 -#define CRC_CCLK_BURST_POLICY_SRC_PLLC_OUT0 1 -#define CRC_CCLK_BURST_POLICY_SRC_CLKS 2 -#define CRC_CCLK_BURST_POLICY_SRC_PLLM_OUT0 3 -#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT0 4 -#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT4 5 -#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT3 6 -#define CRC_CCLK_BURST_POLICY_SRC_CLKD 7 -#define CRC_CCLK_BURST_POLICY_SRC_PLLX_OUT0 8 - -#define CRC_SUPER_CCLK_DIV 0x024 -#define CRC_SUPER_CDIV_ENB (1 << 31) -#define CRC_SUPER_CDIV_DIS_FROM_COP_FIQ (1 << 27) -#define CRC_SUPER_CDIV_DIS_FROM_CPU_FIQ (1 << 26) -#define CRC_SUPER_CDIV_DIS_FROM_COP_IRQ (1 << 25) -#define CRC_SUPER_CDIV_DIS_FROM_CPU_IRQ (1 << 24) -#define CRC_SUPER_CDIV_DIVIDEND_SHIFT 8 -#define CRC_SUPER_CDIV_DIVIDEND_MASK (0xff << CRC_SUPER_CDIV_DIVIDEND_SHIFT) -#define CRC_SUPER_CDIV_DIVISOR_SHIFT 0 -#define CRC_SUPER_CDIV_DIVISOR_MASK (0xff << CRC_SUPER_CDIV_DIVISOR_SHIFT) - -#define CRC_SCLK_BURST_POLICY 0x028 -#define CRC_SCLK_BURST_POLICY_SYS_STATE_SHIFT 28 -#define CRC_SCLK_BURST_POLICY_SYS_STATE_FIQ 8 -#define CRC_SCLK_BURST_POLICY_SYS_STATE_IRQ 4 -#define CRC_SCLK_BURST_POLICY_SYS_STATE_RUN 2 -#define CRC_SCLK_BURST_POLICY_SYS_STATE_IDLE 1 -#define CRC_SCLK_BURST_POLICY_SYS_STATE_STDBY 0 -#define CRC_SCLK_BURST_POLICY_FIQ_SRC_SHIFT 12 -#define CRC_SCLK_BURST_POLICY_IRQ_SRC_SHIFT 8 -#define CRC_SCLK_BURST_POLICY_RUN_SRC_SHIFT 4 -#define CRC_SCLK_BURST_POLICY_IDLE_SRC_SHIFT 0 -#define CRC_SCLK_BURST_POLICY_SRC_CLKM 0 -#define CRC_SCLK_BURST_POLICY_SRC_PLLC_OUT1 1 -#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT4 2 -#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT3 3 -#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT2 4 -#define CRC_SCLK_BURST_POLICY_SRC_CLKD 5 -#define CRC_SCLK_BURST_POLICY_SRC_CLKS 6 -#define CRC_SCLK_BURST_POLICY_SRC_PLLM_OUT1 7 - -#define CRC_SUPER_SCLK_DIV 0x02c -#define CRC_SUPER_SDIV_ENB (1 << 31) -#define CRC_SUPER_SDIV_DIS_FROM_COP_FIQ (1 << 27) -#define CRC_SUPER_SDIV_DIS_FROM_CPU_FIQ (1 << 26) -#define CRC_SUPER_SDIV_DIS_FROM_COP_IRQ (1 << 25) -#define CRC_SUPER_SDIV_DIS_FROM_CPU_IRQ (1 << 24) -#define CRC_SUPER_SDIV_DIVIDEND_SHIFT 8 -#define CRC_SUPER_SDIV_DIVIDEND_MASK (0xff << CRC_SUPER_SDIV_DIVIDEND_SHIFT) -#define CRC_SUPER_SDIV_DIVISOR_SHIFT 0 -#define CRC_SUPER_SDIV_DIVISOR_MASK (0xff << CRC_SUPER_SDIV_DIVISOR_SHIFT) - -#define CRC_CLK_SYSTEM_RATE 0x030 -#define CRC_CLK_SYSTEM_RATE_AHB_SHIFT 4 -#define CRC_CLK_SYSTEM_RATE_APB_SHIFT 0 - -#define CRC_CLK_CPU_CMPLX 0x04c -#define CRC_CLK_CPU_CMPLX_CPU3_CLK_STP (1 << 11) -#define CRC_CLK_CPU_CMPLX_CPU2_CLK_STP (1 << 10) -#define CRC_CLK_CPU_CMPLX_CPU1_CLK_STP (1 << 9) -#define CRC_CLK_CPU_CMPLX_CPU0_CLK_STP (1 << 8) -#define CRC_CLK_CPU_CMPLX_CPU_BRIDGE_DIV_SHIFT 0 -#define CRC_CLK_CPU_CMPLX_CPU_BRIDGE_DIV_4 3 -#define CRC_CLK_CPU_CMPLX_CPU_BRIDGE_DIV_3 2 -#define CRC_CLK_CPU_CMPLX_CPU_BRIDGE_DIV_2 1 -#define CRC_CLK_CPU_CMPLX_CPU_BRIDGE_DIV_1 0 - -#define CRC_OSC_CTRL 0x050 -#define CRC_OSC_CTRL_OSC_FREQ_SHIFT 30 -#define CRC_OSC_CTRL_OSC_FREQ_MASK (0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT) -#define CRC_OSC_CTRL_PLL_REF_DIV_SHIFT 28 -#define CRC_OSC_CTRL_PLL_REF_DIV_MASK (0x3 << CRC_OSC_CTRL_PLL_REF_DIV_SHIFT) - -#define CRC_PLL_BASE_LOCK 27 -#define CRC_PLLE_MISC_LOCK 11 - -#define CRC_PLL_MISC_LOCK_ENABLE 18 -#define CRC_PLLDU_MISC_LOCK_ENABLE 22 -#define CRC_PLLE_MISC_LOCK_ENABLE 9 - -#define CRC_PLLS_BASE 0x0f0 -#define CRC_PLLS_MISC 0x0f4 - -#define CRC_PLLC_BASE 0x080 -#define CRC_PLLC_OUT 0x084 -#define CRC_PLLC_MISC 0x08c - -#define CRC_PLLM_BASE 0x090 -#define CRC_PLLM_OUT 0x094 -#define CRC_PLLM_MISC 0x09c - -#define CRC_PLLP_BASE 0x0a0 -#define CRC_PLLP_OUTA 0x0a4 -#define CRC_PLLP_OUTB 0x0a8 -#define CRC_PLLP_MISC 0x0ac - -#define CRC_PLLA_BASE 0x0b0 -#define CRC_PLLA_OUT 0x0b4 -#define CRC_PLLA_MISC 0x0bc - -#define CRC_PLLU_BASE 0x0c0 -#define CRC_PLLU_MISC 0x0cc - -#define CRC_PLLD_BASE 0x0d0 -#define CRC_PLLD_MISC 0x0dc - -#define CRC_PLLX_BASE 0x0e0 -#define CRC_PLLX_BASE_BYPASS (1 << 31) -#define CRC_PLLX_BASE_ENABLE (1 << 30) -#define CRC_PLLX_BASE_REF_DIS (1 << 29) -#define CRC_PLLX_BASE_LOCK (1 << 27) -#define CRC_PLLX_BASE_DIVP_SHIFT 20 -#define CRC_PLLX_BASE_DIVP_MASK (0x7 << CRC_PLLX_BASE_DIVP_SHIFT) -#define CRC_PLLX_BASE_DIVN_SHIFT 8 -#define CRC_PLLX_BASE_DIVN_MASK (0x3ff << CRC_PLLX_BASE_DIVN_SHIFT) -#define CRC_PLLX_BASE_DIVM_SHIFT 0 -#define CRC_PLLX_BASE_DIVM_MASK (0xf << CRC_PLLX_BASE_DIVM_SHIFT) - -#define CRC_PLLX_MISC 0x0e4 -#define CRC_PLLX_MISC_SETUP_SHIFT 24 -#define CRC_PLLX_MISC_SETUP_MASK (0xf << CRC_PLLX_MISC_SETUP_SHIFT) -#define CRC_PLLX_MISC_PTS_SHIFT 22 -#define CRC_PLLX_MISC_PTS_MASK (0x3 << CRC_PLLX_MISC_PTS_SHIFT) -#define CRC_PLLX_MISC_DCCON (1 << 20) -#define CRC_PLLX_MISC_LOCK_ENABLE (1 << 18) -#define CRC_PLLX_MISC_LOCK_SEL_SHIFT 12 -#define CRC_PLLX_MISC_LOCK_SEL_MASK (0x3f << CRC_PLLX_MISC_LOCK_SEL_SHIFT) -#define CRC_PLLX_MISC_CPCON_SHIFT 8 -#define CRC_PLLX_MISC_CPCON_MASK (0xf << CRC_PLLX_MISC_CPCON_SHIFT) -#define CRC_PLLX_MISC_LFCON_SHIFT 4 -#define CRC_PLLX_MISC_LFCON_MASK (0xf << CRC_PLLX_MISC_LFCON_SHIFT) -#define CRC_PLLX_MISC_VCOCON_SHIFT 0 -#define CRC_PLLX_MISC_VCOCON_MASK (0xf << CRC_PLLX_MISC_VCOCON_SHIFT) - -#define CRC_PLLE_BASE 0x0e8 -#define CRC_PLLE_MISC 0x0ec - -#define CRC_CLK_SOURCE_I2S1 0x100 -#define CRC_CLK_SOURCE_I2S2 0x104 -#define CRC_CLK_SOURCE_SPDIF_OUT 0x108 -#define CRC_CLK_SOURCE_SPDIF_IN 0x10c -#define CRC_CLK_SOURCE_PWM 0x110 -#define CRC_CLK_SOURCE_SPI 0x114 -#define CRC_CLK_SOURCE_SBC1 0x134 -#define CRC_CLK_SOURCE_SBC2 0x118 -#define CRC_CLK_SOURCE_SBC3 0x11c -#define CRC_CLK_SOURCE_SBC4 0x1b4 -#define CRC_CLK_SOURCE_XIO 0x120 -#define CRC_CLK_SOURCE_TWC 0x12c -#define CRC_CLK_SOURCE_IDE 0x144 -#define CRC_CLK_SOURCE_NDFLASH 0x160 -#define CRC_CLK_SOURCE_VFIR 0x168 -#define CRC_CLK_SOURCE_SDMMC1 0x150 -#define CRC_CLK_SOURCE_SDMMC2 0x154 -#define CRC_CLK_SOURCE_SDMMC3 0x1bc -#define CRC_CLK_SOURCE_SDMMC4 0x164 -#define CRC_CLK_SOURCE_CVE 0x140 -#define CRC_CLK_SOURCE_TVO 0x188 -#define CRC_CLK_SOURCE_TVDAC 0x194 -#define CRC_CLK_SOURCE_HDMI 0x18c -#define CRC_CLK_SOURCE_DISP1 0x138 -#define CRC_CLK_SOURCE_DISP2 0x13c -#define CRC_CLK_SOURCE_CSITE 0x1d4 -#define CRC_CLK_SOURCE_LA 0x1f8 -#define CRC_CLK_SOURCE_OWR 0x1cc -#define CRC_CLK_SOURCE_NOR 0x1d0 -#define CRC_CLK_SOURCE_MIPI 0x174 -#define CRC_CLK_SOURCE_I2C1 0x124 -#define CRC_CLK_SOURCE_I2C2 0x198 -#define CRC_CLK_SOURCE_I2C3 0x1b8 -#define CRC_CLK_SOURCE_DVC 0x128 -#define CRC_CLK_SOURCE_UARTA 0x178 -#define CRC_CLK_SOURCE_UARTB 0x17c -#define CRC_CLK_SOURCE_UARTC 0x1a0 -#define CRC_CLK_SOURCE_UARTD 0x1c0 -#define CRC_CLK_SOURCE_UARTE 0x1c4 -#define CRC_CLK_SOURCE_3D 0x158 -#define CRC_CLK_SOURCE_2D 0x15c -#define CRC_CLK_SOURCE_MPE 0x170 -#define CRC_CLK_SOURCE_EPP 0x16c -#define CRC_CLK_SOURCE_HOST1X 0x180 -#define CRC_CLK_SOURCE_VDE 0x1c8 -#define CRC_CLK_SOURCE_VI 0x148 -#define CRC_CLK_SOURCE_VI_SENSOR 0x1a8 -#define CRC_CLK_SOURCE_EMC 0x19c - -#define CRC_RST_DEV_L_SET 0x300 -#define CRC_RST_DEV_L_CACHE2 (1 << 31) -#define CRC_RST_DEV_L_VCP (1 << 29) -#define CRC_RST_DEV_L_HOST1X (1 << 28) -#define CRC_RST_DEV_L_DISP1 (1 << 27) -#define CRC_RST_DEV_L_DISP2 (1 << 26) -#define CRC_RST_DEV_L_IDE (1 << 25) -#define CRC_RST_DEV_L_3D (1 << 24) -#define CRC_RST_DEV_L_ISP (1 << 23) -#define CRC_RST_DEV_L_USBD (1 << 22) -#define CRC_RST_DEV_L_2D (1 << 21) -#define CRC_RST_DEV_L_VI (1 << 20) -#define CRC_RST_DEV_L_EPP (1 << 19) -#define CRC_RST_DEV_L_I2S2 (1 << 18) -#define CRC_RST_DEV_L_PWM (1 << 17) -#define CRC_RST_DEV_L_TWC (1 << 16) -#define CRC_RST_DEV_L_SDMMC4 (1 << 15) -#define CRC_RST_DEV_L_SDMMC1 (1 << 14) -#define CRC_RST_DEV_L_NDFLASH (1 << 13) -#define CRC_RST_DEV_L_I2C1 (1 << 12) -#define CRC_RST_DEV_L_I2S1 (1 << 11) -#define CRC_RST_DEV_L_SPDIF (1 << 10) -#define CRC_RST_DEV_L_SDMMC2 (1 << 9) -#define CRC_RST_DEV_L_GPIO (1 << 8) -#define CRC_RST_DEV_L_UART2 (1 << 7) -#define CRC_RST_DEV_L_UART1 (1 << 6) -#define CRC_RST_DEV_L_TMR (1 << 5) -#define CRC_RST_DEV_L_AC97 (1 << 3) -#define CRC_RST_DEV_L_SYS (1 << 2) -#define CRC_RST_DEV_L_COP (1 << 1) -#define CRC_RST_DEV_L_CPU (1 << 0) - -#define CRC_RST_DEV_L_CLR 0x304 - -#define CRC_RST_DEV_H_SET 0x308 -#define CRC_RST_DEV_H_DVC (1 << 15) - -#define CRC_RST_DEV_H_CLR 0x30c - -#define CRC_RST_CPU_CMPLX_SET 0x340 - -#define CRC_RST_CPU_CMPLX_CLR 0x344 diff --git a/arch/arm/mach-tegra/include/mach/tegra20-pmc.h b/arch/arm/mach-tegra/include/mach/tegra20-pmc.h deleted file mode 100644 index c379544755..0000000000 --- a/arch/arm/mach-tegra/include/mach/tegra20-pmc.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* register definitions */ -#define PMC_CNTRL 0x000 -#define PMC_CNTRL_FUSE_OVERRIDE (1 << 18) -#define PMC_CNTRL_INTR_POLARITY (1 << 17) -#define PMC_CNTRL_CPUPWRREQ_OE (1 << 16) -#define PMC_CNTRL_CPUPWRREQ_POLARITY (1 << 15) -#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) -#define PMC_CNTRL_AOINIT (1 << 13) -#define PMC_CNTRL_PWRGATE_DIS (1 << 12) -#define PMC_CNTRL_SYSCLK_OE (1 << 11) -#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) -#define PMC_CNTRL_PWRREQ_OE (1 << 9) -#define PMC_CNTRL_PWRREQ_POLARITY (1 << 8) -#define PMC_CNTRL_BLINK_EN (1 << 7) -#define PMC_CNTRL_GLITCHDET_DIS (1 << 6) -#define PMC_CNTRL_LATCHWAKE_EN (1 << 5) -#define PMC_CNTRL_MAIN_RST (1 << 4) -#define PMC_CNTRL_KBC_RST (1 << 3) -#define PMC_CNTRL_RTC_RST (1 << 2) -#define PMC_CNTRL_RTC_CLK_DIS (1 << 1) -#define PMC_CNTRL_KBC_CLK_DIS (1 << 0) - -#define PMC_PWRGATE_TOGGLE 0x030 -#define PMC_PWRGATE_TOGGLE_PARTID_SHIFT 0 -#define PMC_PWRGATE_TOGGLE_PARTID_MASK (0x3 << PMC_PWRGATE_TOGGLE_PARTID_SHIFT) -#define PMC_PWRGATE_TOGGLE_PARTID_CPU 0 -#define PMC_PWRGATE_TOGGLE_PARTID_TD 1 -#define PMC_PWRGATE_TOGGLE_PARTID_VE 2 -#define PMC_PWRGATE_TOGGLE_PARTID_PCX 3 -#define PMC_PWRGATE_TOGGLE_PARTID_VDE 4 -#define PMC_PWRGATE_TOGGLE_PARTID_L2C 5 -#define PMC_PWRGATE_TOGGLE_PARTID_MPE 6 -#define PMC_PWRGATE_TOGGLE_START (1 << 8) - -#define PMC_REMOVE_CLAMPING_CMD 0x034 -#define PMC_REMOVE_CLAMPING_CMD_MPE (1 << 6) -#define PMC_REMOVE_CLAMPING_CMD_L2C (1 << 5) -#define PMC_REMOVE_CLAMPING_CMD_PCX (1 << 4) -#define PMC_REMOVE_CLAMPING_CMD_VDE (1 << 3) -#define PMC_REMOVE_CLAMPING_CMD_VE (1 << 2) -#define PMC_REMOVE_CLAMPING_CMD_TD (1 << 1) -#define PMC_REMOVE_CLAMPING_CMD_CPU (1 << 0) - -#define PMC_PWRGATE_STATUS 0x038 -#define PMC_PWRGATE_STATUS_MPE (1 << 6) -#define PMC_PWRGATE_STATUS_L2C (1 << 5) -#define PMC_PWRGATE_STATUS_VDE (1 << 4) -#define PMC_PWRGATE_STATUS_PCX (1 << 3) -#define PMC_PWRGATE_STATUS_VE (1 << 2) -#define PMC_PWRGATE_STATUS_TD (1 << 1) -#define PMC_PWRGATE_STATUS_CPU (1 << 0) - -#define PMC_PARTID_CRAIL 0 -#define PMC_PARTID_CE0 14 -#define PMC_PARTID_C0NC 15 - -#define PMC_SCRATCH(i) (0x050 + 0x4*i) - -#define PMC_RST_STATUS 0x1b4 -#define PMC_RST_STATUS_RST_SRC_SHIFT 0 -#define PMC_RST_STATUS_RST_SRC_MASK (0x7 << PMC_RST_STATUS_RST_SRC_SHIFT) -#define PMC_RST_STATUS_RST_SRC_POR 0 -#define PMC_RST_STATUS_RST_SRC_WATCHDOG 1 -#define PMC_RST_STATUS_RST_SRC_SENSOR 2 -#define PMC_RST_STATUS_RST_SRC_SW_MAIN 3 -#define PMC_RST_STATUS_RST_SRC_LP0 4 diff --git a/arch/arm/mach-tegra/include/mach/tegra30-car.h b/arch/arm/mach-tegra/include/mach/tegra30-car.h deleted file mode 100644 index 7fb2238dc9..0000000000 --- a/arch/arm/mach-tegra/include/mach/tegra30-car.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Register definitions */ -#define CRC_CLK_OUT_ENB_V 0x360 -#define CRC_CLK_OUT_ENB_V_MSELECT (1 << 3) - -#define CRC_CLK_SOURCE_MSEL 0x3b4 -#define CRC_CLK_SOURCE_MSEL_SRC_SHIFT 30 -#define CRC_CLK_SOURCE_MSEL_SRC_PLLP 0 -#define CRC_CLK_SOURCE_MSEL_SRC_PLLC 1 -#define CRC_CLK_SOURCE_MSEL_SRC_PLLM 2 -#define CRC_CLK_SOURCE_MSEL_SRC_CLKM 3 - -#define CRC_CLK_SOURCE_I2C4 0x3c4 - -#define CRC_RST_DEV_V_SET 0x430 -#define CRC_RST_DEV_V_MSELECT (1 << 3) - -#define CRC_RST_DEV_V_CLR 0x434 - -#define CRC_CLK_OUT_ENB_V_SET 0x440 - -#define CRC_PLLE_AUX 0x48c diff --git a/arch/arm/mach-tegra/include/mach/tegra30-flow.h b/arch/arm/mach-tegra/include/mach/tegra30-flow.h deleted file mode 100644 index 50a3030e5e..0000000000 --- a/arch/arm/mach-tegra/include/mach/tegra30-flow.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#define FLOW_HALT_CPU_EVENTS 0x000 -#define FLOW_MODE_NONE 0 -#define FLOW_MODE_STOP 2 - -#define FLOW_CLUSTER_CONTROL 0x02c -#define FLOW_CLUSTER_CONTROL_ACTIVE_G (0 << 0) -#define FLOW_CLUSTER_CONTROL_ACTIVE_LP (1 << 0) diff --git a/arch/arm/mach-tegra/tegra-bbu.c b/arch/arm/mach-tegra/tegra-bbu.c index 089e6c736a..0a59da04db 100644 --- a/arch/arm/mach-tegra/tegra-bbu.c +++ b/arch/arm/mach-tegra/tegra-bbu.c @@ -17,7 +17,7 @@ #include <common.h> #include <fcntl.h> #include <fs.h> -#include <mach/tegra-bbu.h> +#include <mach/tegra/tegra-bbu.h> #include <malloc.h> static int tegra_bbu_emmc_handler(struct bbu_handler *handler, diff --git a/arch/arm/mach-tegra/tegra20-pmc.c b/arch/arm/mach-tegra/tegra20-pmc.c index f7c7ac918f..11fd8c28be 100644 --- a/arch/arm/mach-tegra/tegra20-pmc.c +++ b/arch/arm/mach-tegra/tegra20-pmc.c @@ -27,11 +27,11 @@ #include <linux/err.h> #include <linux/clk.h> #include <linux/reset.h> -#include <mach/lowlevel.h> -#include <mach/tegra-powergate.h> +#include <mach/tegra/lowlevel.h> +#include <mach/tegra/tegra-powergate.h> #include <reset_source.h> -#include <mach/tegra20-pmc.h> +#include <mach/tegra/tegra20-pmc.h> static void __iomem *pmc_base; static int tegra_num_powerdomains; @@ -200,7 +200,7 @@ static void tegra20_pmc_detect_reset_cause(void) } } -static int tegra20_pmc_probe(struct device_d *dev) +static int tegra20_pmc_probe(struct device *dev) { struct resource *iores; iores = dev_request_mem_resource(dev, 0); @@ -237,8 +237,9 @@ static __maybe_unused struct of_device_id tegra20_pmc_dt_ids[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, tegra20_pmc_dt_ids); -static struct driver_d tegra20_pmc_driver = { +static struct driver tegra20_pmc_driver = { .probe = tegra20_pmc_probe, .name = "tegra20-pmc", .of_compatible = DRV_OF_COMPAT(tegra20_pmc_dt_ids), @@ -246,7 +247,7 @@ static struct driver_d tegra20_pmc_driver = { static int tegra20_pmc_init(void) { - restart_handler_register_fn(tegra20_restart_soc); + restart_handler_register_fn("soc", tegra20_restart_soc); return platform_driver_register(&tegra20_pmc_driver); } coredevice_initcall(tegra20_pmc_init); diff --git a/arch/arm/mach-tegra/tegra20-timer.c b/arch/arm/mach-tegra/tegra20-timer.c index 2ba58bd65e..e3cd216f30 100644 --- a/arch/arm/mach-tegra/tegra20-timer.c +++ b/arch/arm/mach-tegra/tegra20-timer.c @@ -25,7 +25,7 @@ #include <io.h> #include <linux/clk.h> #include <linux/err.h> -#include <mach/lowlevel.h> +#include <mach/tegra/lowlevel.h> /* register definitions */ #define TIMERUS_CNTR_1US 0x10 @@ -41,9 +41,10 @@ static uint64_t tegra20_timer_cs_read(void) static struct clocksource cs = { .read = tegra20_timer_cs_read, .mask = CLOCKSOURCE_MASK(32), + .priority = 80, }; -static int tegra20_timer_probe(struct device_d *dev) +static int tegra20_timer_probe(struct device *dev) { struct resource *iores; u32 reg; @@ -97,15 +98,12 @@ static __maybe_unused struct of_device_id tegra20_timer_dt_ids[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, tegra20_timer_dt_ids); -static struct driver_d tegra20_timer_driver = { +static struct driver tegra20_timer_driver = { .probe = tegra20_timer_probe, .name = "tegra20-timer", .of_compatible = DRV_OF_COMPAT(tegra20_timer_dt_ids), }; -static int tegra20_timer_init(void) -{ - return platform_driver_register(&tegra20_timer_driver); -} -core_initcall(tegra20_timer_init); +core_platform_driver(tegra20_timer_driver); diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c index 10c149a955..d27f775cf9 100644 --- a/arch/arm/mach-tegra/tegra20.c +++ b/arch/arm/mach-tegra/tegra20.c @@ -17,9 +17,9 @@ #include <common.h> #include <init.h> #include <asm/memory.h> -#include <mach/iomap.h> -#include <mach/lowlevel.h> -#include <mach/tegra114-sysctr.h> +#include <mach/tegra/iomap.h> +#include <mach/tegra/lowlevel.h> +#include <mach/tegra/tegra114-sysctr.h> static int tegra20_mem_init(void) { diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c index 8a11e06c53..021bcb6d95 100644 --- a/arch/arm/mach-tegra/tegra_avp_init.c +++ b/arch/arm/mach-tegra/tegra_avp_init.c @@ -20,12 +20,12 @@ #include <common.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/lowlevel.h> -#include <mach/tegra20-car.h> -#include <mach/tegra20-pmc.h> -#include <mach/tegra30-car.h> -#include <mach/tegra30-flow.h> -#include <mach/tegra124-car.h> +#include <mach/tegra/lowlevel.h> +#include <mach/tegra/tegra20-car.h> +#include <mach/tegra/tegra20-pmc.h> +#include <mach/tegra/tegra30-car.h> +#include <mach/tegra/tegra30-flow.h> +#include <mach/tegra/tegra124-car.h> /* instruct the PMIC to enable the CPU power rail */ static void enable_maincomplex_powerrail(void) diff --git a/arch/arm/mach-tegra/tegra_maincomplex_init.c b/arch/arm/mach-tegra/tegra_maincomplex_init.c index 27bb3363a3..2a2272a99f 100644 --- a/arch/arm/mach-tegra/tegra_maincomplex_init.c +++ b/arch/arm/mach-tegra/tegra_maincomplex_init.c @@ -19,9 +19,9 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <asm/errata.h> -#include <mach/lowlevel.h> -#include <mach/tegra20-pmc.h> -#include <mach/tegra20-car.h> +#include <mach/tegra/lowlevel.h> +#include <mach/tegra/tegra20-pmc.h> +#include <mach/tegra/tegra20-car.h> void tegra_maincomplex_entry(char *fdt) { |