diff options
Diffstat (limited to 'arch/arm/mach-zynq')
| -rw-r--r-- | arch/arm/mach-zynq/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/cpu_init.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/include/mach/debug_ll.h | 37 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/include/mach/init.h | 8 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/include/mach/zynq-flash-header.h | 27 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h | 49 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/include/mach/zynq7000-regs.h | 134 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/zynq.c | 4 |
9 files changed, 8 insertions, 259 deletions
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 3e07633e5f..451a344b2e 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + if ARCH_ZYNQ config ARCH_TEXT_BASE @@ -11,7 +13,6 @@ config ZYNQ_DEBUG_LL_UART_BASE config ARCH_ZYNQ7000 bool select CPU_V7 - select CLKDEV_LOOKUP select COMMON_CLK select COMMON_CLK_OF_PROVIDER select ARM_SMP_TWD @@ -27,6 +28,7 @@ menu "select Zynq boards to be built" config MACH_ZEDBOARD bool "Avnet Zynq-7000 ZedBoard" + select ARM_USE_COMPRESSED_DTB select ARCH_ZYNQ7000 endmenu diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index 06c2ce996c..d5e94859a6 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += zynq.o bootm-zynqimg.o lwl-y += cpu_init.o diff --git a/arch/arm/mach-zynq/cpu_init.c b/arch/arm/mach-zynq/cpu_init.c index ca7c4b2979..7194c7e216 100644 --- a/arch/arm/mach-zynq/cpu_init.c +++ b/arch/arm/mach-zynq/cpu_init.c @@ -3,7 +3,7 @@ #include <common.h> #include <asm/barebox-arm-head.h> #include <asm/errata.h> -#include <mach/init.h> +#include <mach/zynq/init.h> void zynq_cpu_lowlevel_init(void) { diff --git a/arch/arm/mach-zynq/include/mach/debug_ll.h b/arch/arm/mach-zynq/include/mach/debug_ll.h deleted file mode 100644 index 6c20dd534d..0000000000 --- a/arch/arm/mach-zynq/include/mach/debug_ll.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * based on mach-imx/include/mach/debug_ll.h - */ - -#ifndef __MACH_DEBUG_LL_H__ -#define __MACH_DEBUG_LL_H__ - -#include <io.h> -#include <mach/zynq7000-regs.h> - -#ifndef CONFIG_ZYNQ_DEBUG_LL_UART_BASE -#warning define ZYNQ_DEBUG_LL_UART_BASE properly for debug_ll -#define ZYNQ_DEBUG_LL_UART_BASE ZYNQ_UART1_BASE_ADDR -#else -#define ZYNQ_DEBUG_LL_UART_BASE CONFIG_ZYNQ_DEBUG_LL_UART_BASE -#endif - -#define ZYNQ_UART_RXTXFIFO 0x30 -#define ZYNQ_UART_CHANNEL_STS 0x2C - -#define ZYNQ_UART_STS_TFUL (1 << 4) -#define ZYNQ_UART_TXDIS (1 << 5) - -static inline void PUTC_LL(int c) -{ - void __iomem *base = (void __iomem *)ZYNQ_DEBUG_LL_UART_BASE; - - if (readl(base) & ZYNQ_UART_TXDIS) - return; - - while ((readl(base + ZYNQ_UART_CHANNEL_STS) & ZYNQ_UART_STS_TFUL) != 0) - ; - - writel(c, base + ZYNQ_UART_RXTXFIFO); -} - -#endif diff --git a/arch/arm/mach-zynq/include/mach/init.h b/arch/arm/mach-zynq/include/mach/init.h deleted file mode 100644 index c458f602e4..0000000000 --- a/arch/arm/mach-zynq/include/mach/init.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef __MACH_INIT_H -#define __MACH_INIT_H - -void zynq_cpu_lowlevel_init(void); - -#endif diff --git a/arch/arm/mach-zynq/include/mach/zynq-flash-header.h b/arch/arm/mach-zynq/include/mach/zynq-flash-header.h deleted file mode 100644 index ba4b67f479..0000000000 --- a/arch/arm/mach-zynq/include/mach/zynq-flash-header.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __MACH_FLASH_HEADER_H -#define __MACH_FLASH_HEADER_H - -#include <stdint.h> - -#define REGINIT_OFFSET 0x0a0 -#define IMAGE_OFFSET 0x8c0 - -#define WIDTH_DETECTION_MAGIC 0xAA995566 -#define IMAGE_IDENTIFICATION 0x584C4E58 /* "XLNX" */ - -struct zynq_flash_header { - uint32_t width_det; - uint32_t image_id; - uint32_t enc_stat; - uint32_t user; - uint32_t flash_offset; - uint32_t length; - uint32_t res0; - uint32_t start_of_exec; - uint32_t total_len; - uint32_t res1; - uint32_t checksum; - uint32_t res2; -}; - -#endif /* __MACH_FLASH_HEADER_H */ diff --git a/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h b/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h deleted file mode 100644 index 4e24064746..0000000000 --- a/arch/arm/mach-zynq/include/mach/zynq7000-header-regs.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (c) 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#define ZYNQ_SLCR_LOCK 0xF8000004 -#define ZYNQ_SLCR_UNLOCK 0xF8000008 -#define ZYNQ_ARM_PLL_CTRL 0xF8000100 -#define ZYNQ_DDR_PLL_CTRL 0xF8000104 -#define ZYNQ_IO_PLL_CTRL 0xF8000108 -#define ZYNQ_PLL_STATUS 0xF800010C -#define ZYNQ_ARM_PLL_CFG 0xF8000110 -#define ZYNQ_DDR_PLL_CFG 0xF8000114 -#define ZYNQ_IO_PLL_CFG 0xF8000118 -#define ZYNQ_ARM_CLK_CTRL 0xF8000120 -#define ZYNQ_DDR_CLK_CTRL 0xF8000124 -#define ZYNQ_DCI_CLK_CTRL 0xF8000128 -#define ZYNQ_APER_CLK_CTRL 0xF800012C -#define ZYNQ_USB0_CLK_CTRL 0xF8000130 -#define ZYNQ_USB1_CLK_CTRL 0xF8000134 -#define ZYNQ_GEM0_RCLK_CTRL 0xF8000138 -#define ZYNQ_GEM1_RCLK_CTRL 0xF800013C -#define ZYNQ_GEM0_CLK_CTRL 0xF8000140 -#define ZYNQ_GEM1_CLK_CTRL 0xF8000144 -#define ZYNQ_SMC_CLK_CTRL 0xF8000148 -#define ZYNQ_LQSPI_CLK_CTRL 0xF800014C -#define ZYNQ_SDIO_CLK_CTRL 0xF8000150 -#define ZYNQ_UART_CLK_CTRL 0xF8000154 -#define ZYNQ_SPI_CLK_CTRL 0xF8000158 -#define ZYNQ_CAN_CLK_CTRL 0xF800015C -#define ZYNQ_CAN_MIOCLK_CTRL 0xF8000160 -#define ZYNQ_DBG_CLK_CTRL 0xF8000164 -#define ZYNQ_PCAP_CLK_CTRL 0xF8000168 -#define ZYNQ_TOPSW_CLK_CTRL 0xF800016C -#define ZYNQ_FPGA0_CLK_CTRL 0xF8000170 -#define ZYNQ_FPGA1_CLK_CTRL 0xF8000180 -#define ZYNQ_FPGA2_CLK_CTRL 0xF8000190 -#define ZYNQ_FPGA3_CLK_CTRL 0xF80001A0 -#define ZYNQ_CLK_621_TRUE 0xF80001C4 diff --git a/arch/arm/mach-zynq/include/mach/zynq7000-regs.h b/arch/arm/mach-zynq/include/mach/zynq7000-regs.h deleted file mode 100644 index eeecfe1ded..0000000000 --- a/arch/arm/mach-zynq/include/mach/zynq7000-regs.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (c) 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#define ZYNQ_UART0_BASE_ADDR 0xE0000000 -#define ZYNQ_UART1_BASE_ADDR 0xE0001000 -#define ZYNQ_I2C0_BASE_ADDR 0xE0004000 -#define ZYNQ_I2C1_BASE_ADDR 0xE0005000 -#define ZYNQ_SPI0_BASE_ADDR 0xE0006000 -#define ZYNQ_SPI1_BASE_ADDR 0xE0007000 -#define ZYNQ_CAN0_BASE_ADDR 0xE0008000 -#define ZYNQ_CAN1_BASE_ADDR 0xE0009000 -#define ZYNQ_GPIO_BASE_ADDR 0xE000A000 -#define ZYNQ_GEM0_BASE_ADDR 0xE000B000 - -#define ZYNQ_SLCR_BASE 0xF8000000 -#define ZYNQ_SLCR_SCL (ZYNQ_SLCR_BASE + 0x000) -#define ZYNQ_SLCR_LOCK (ZYNQ_SLCR_BASE + 0x004) -#define ZYNQ_SLCR_UNLOCK (ZYNQ_SLCR_BASE + 0x008) -#define ZYNQ_SLCR_LOCKSTA (ZYNQ_SLCR_BASE + 0x00C) -#define ZYNQ_CLOCK_CTRL_BASE (ZYNQ_SLCR_BASE + 0x100) -#define ZYNQ_ARM_PLL_CTRL 0x000 -#define ZYNQ_DDR_PLL_CTRL 0x004 -#define ZYNQ_IO_PLL_CTRL 0x008 -#define ZYNQ_PLL_STATUS 0x00C -#define ZYNQ_ARM_PLL_CFG 0x010 -#define ZYNQ_DDR_PLL_CFG 0x014 -#define ZYNQ_IO_PLL_CFG 0x018 -#define ZYNQ_ARM_CLK_CTRL 0x020 -#define ZYNQ_DDR_CLK_CTRL 0x024 -#define ZYNQ_DCI_CLK_CTRL 0x028 -#define ZYNQ_APER_CLK_CTRL 0x02C -#define ZYNQ_USB0_CLK_CTRL 0x030 -#define ZYNQ_USB1_CLK_CTRL 0x034 -#define ZYNQ_GEM0_RCLK_CTRL 0x038 -#define ZYNQ_GEM1_RCLK_CTRL 0x03C -#define ZYNQ_GEM0_CLK_CTRL 0x040 -#define ZYNQ_GEM1_CLK_CTRL 0x044 -#define ZYNQ_SMC_CLK_CTRL 0x048 -#define ZYNQ_LQSPI_CLK_CTRL 0x04C -#define ZYNQ_SDIO_CLK_CTRL 0x050 -#define ZYNQ_UART_CLK_CTRL 0x054 -#define ZYNQ_SPI_CLK_CTRL 0x058 -#define ZYNQ_CAN_CLK_CTRL 0x05C -#define ZYNQ_CAN_MIOCLK_CTRL 0x060 -#define ZYNQ_DBG_CLK_CTRL 0x064 -#define ZYNQ_PCAP_CLK_CTRL 0x068 -#define ZYNQ_TOPSW_CLK_CTRL 0x06C -#define ZYNQ_FPGA0_CLK_CTRL 0x070 -#define ZYNQ_FPGA1_CLK_CTRL 0x080 -#define ZYNQ_FPGA2_CLK_CTRL 0x090 -#define ZYNQ_FPGA3_CLK_CTRL 0x0A0 -#define ZYNQ_CLK_621_TRUE 0x0C4 -#define ZYNQ_RST_CTRL_BASE (ZYNQ_SLCR_BASE + 0x200) -#define ZYNQ_SLCR_BOOT_MODE (ZYNQ_SLCR_BASE + 0x25C) -#define ZYNQ_PSS_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x000) -#define ZYNQ_DDR_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x004) -#define ZYNQ_TOPSW_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x008) -#define ZYNQ_DMAC_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x00C) -#define ZYNQ_USB_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x010) -#define ZYNQ_GEM_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x014) -#define ZYNQ_SDIO_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x018) -#define ZYNQ_SPI_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x01C) -#define ZYNQ_CAN_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x020) -#define ZYNQ_I2C_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x024) -#define ZYNQ_UART_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x028) -#define ZYNQ_GPIO_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x02C) -#define ZYNQ_LQSPI_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x030) -#define ZYNQ_SMC_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x034) -#define ZYNQ_OCM_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x038) -#define ZYNQ_DEVCI_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x03C) -#define ZYNQ_FPGA_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x040) -#define ZYNQ_A9_CPU_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x044) -#define ZYNQ_RS_AWDT_CTRL (ZYNQ_RST_CTRL_BASE + 0x04C) -#define ZYNQ_REBOOT_STATUS (ZYNQ_SLCR_BASE + 0x258) -#define ZYNQ_BOOT_MODE (ZYNQ_SLCR_BASE + 0x25C) -#define ZYNQ_APU_CTRL (ZYNQ_SLCR_BASE + 0x300) -#define ZYNQ_WDT_CLK_SEL (ZYNQ_SLCR_BASE + 0x304) -#define ZYNQ_PSS_IDCODE (ZYNQ_SLCR_BASE + 0x530) -#define ZYNQ_DDR_URGENT (ZYNQ_SLCR_BASE + 0x600) -#define ZYNQ_DDR_CAL_START (ZYNQ_SLCR_BASE + 0x60C) -#define ZYNQ_DDR_REF_START (ZYNQ_SLCR_BASE + 0x614) -#define ZYNQ_DDR_CMD_STA (ZYNQ_SLCR_BASE + 0x618) -#define ZYNQ_DDR_URGENT_SEL (ZYNQ_SLCR_BASE + 0x61C) -#define ZYNQ_DDR_DFI_STATUS (ZYNQ_SLCR_BASE + 0x620) -#define ZYNQ_MIO_BASE (ZYNQ_SLCR_BASE + 0x700) -#define ZYNQ_MIO_LOOPBACK (ZYNQ_MIO_BASE + 0x104) -#define ZYNQ_MIO_MST_TRI0 (ZYNQ_MIO_BASE + 0x10C) -#define ZYNQ_MIO_MST_TRI1 (ZYNQ_MIO_BASE + 0x110) -#define ZYNQ_SD0_WP_SEL (ZYNQ_SLCR_BASE + 0x830) -#define ZYNQ_SD1_WP_SEL (ZYNQ_SLCR_BASE + 0x834) -#define ZYNQ_LVL_SHIFTR_EN (ZYNQ_SLCR_BASE + 0x900) -#define ZYNQ_OCM_CFG (ZYNQ_SLCR_BASE + 0x910) -#define ZYNQ_GPIOB_BASE (ZYNQ_SLCR_BASE + 0xB00) -#define ZYNQ_GPIOB_CTRL (ZYNQ_GPIOB_BASE + 0x000) -#define ZYNQ_GPIOB_CFG_CMOS18 (ZYNQ_GPIOB_BASE + 0x004) -#define ZYNQ_GPIOB_CFG_CMOS25 (ZYNQ_GPIOB_BASE + 0x008) -#define ZYNQ_GPIOB_CFG_CMOS33 (ZYNQ_GPIOB_BASE + 0x00C) -#define ZYNQ_GPIOB_CFG_LVTTL (ZYNQ_GPIOB_BASE + 0x010) -#define ZYNQ_GPIOB_CFG_HSTL (ZYNQ_GPIOB_BASE + 0x014) -#define ZYNQ_GPIOB_DRV_BIAS_CTRL (ZYNQ_GPIOB_BASE + 0x018) -#define ZYNQ_DDRIOB_BASE (ZYNQ_SLCR_BASE + 0xB40) -#define ZYNQ_DDRIOB_ADDR0 (ZYNQ_DDRIOB_BASE + 0x000) -#define ZYNQ_DDRIOB_ADDR1 (ZYNQ_DDRIOB_BASE + 0x004) -#define ZYNQ_DDRIOB_DATA0 (ZYNQ_DDRIOB_BASE + 0x008) -#define ZYNQ_DDRIOB_DATA1 (ZYNQ_DDRIOB_BASE + 0x00C) -#define ZYNQ_DDRIOB_DIFF0 (ZYNQ_DDRIOB_BASE + 0x010) -#define ZYNQ_DDRIOB_DIFF1 (ZYNQ_DDRIOB_BASE + 0x014) -#define ZYNQ_DDRIOB_CLOCK (ZYNQ_DDRIOB_BASE + 0x018) -#define ZYNQ_DDRIOB_DRIVE_SLEW_ADDR (ZYNQ_DDRIOB_BASE + 0x01C) -#define ZYNQ_DDRIOB_DRIVE_SLEW_DATA (ZYNQ_DDRIOB_BASE + 0x020) -#define ZYNQ_DDRIOB_DRIVE_SLEW_DIFF (ZYNQ_DDRIOB_BASE + 0x024) -#define ZYNQ_DDRIOB_DRIVE_SLEW_CLOCK (ZYNQ_DDRIOB_BASE + 0x028) -#define ZYNQ_DDRIOB_DDR_CTRL (ZYNQ_DDRIOB_BASE + 0x02C) -#define ZYNQ_DDRIOB_DCI_CTRL (ZYNQ_DDRIOB_BASE + 0x030) -#define ZYNQ_DDRIOB_DCI_STATUS (ZYNQ_DDRIOB_BASE + 0x034) - -#define ZYNQ_TTC0_BASE_ADDR 0xF8001000 -#define ZYNQ_TTC1_BASE_ADDR 0xF8002000 - -#define ZYNQ_DDRC_BASE 0xF8006000 - -#define CORTEXA9_SCU_TIMER_BASE_ADDR 0xF8F00600 diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c index 806aeb9130..2d76a68a5e 100644 --- a/arch/arm/mach-zynq/zynq.c +++ b/arch/arm/mach-zynq/zynq.c @@ -18,7 +18,7 @@ #include <common.h> #include <init.h> #include <io.h> -#include <mach/zynq7000-regs.h> +#include <mach/zynq/zynq7000-regs.h> #include <restart.h> static void __noreturn zynq_restart_soc(struct restart_handler *rst) @@ -71,7 +71,7 @@ static int zynq_init(void) restart_handler_register_fn("soc", zynq_restart_soc); - bootsource_set(zynq_bootsource_get()); + bootsource_set_raw(zynq_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN); return 0; } |