diff options
Diffstat (limited to 'arch/arm')
30 files changed, 682 insertions, 230 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 0ecfb3e4b3..f2d4d38785 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -115,6 +115,7 @@ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/ +obj-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += technexion-pico-hobbit/ obj-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += technexion-wandboard/ obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/ obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/ diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c index ca22eba393..028b1dddbe 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c @@ -22,7 +22,6 @@ #include <io.h> #include <mfd/imx6q-iomuxc-gpr.h> #include <generated/mach-types.h> -#include <linux/clk.h> #include <i2c/i2c.h> #include <asm/armlinux.h> @@ -181,11 +180,10 @@ int ar8031_phy_fixup(struct phy_device *phydev) #define PHY_ID_AR8031 0x004dd074 #define AR_PHY_ID_MASK 0xffffffff -static int imx6sx_sdb_setup_fec(void) +static void imx6sx_sdb_setup_fec(void) { void __iomem *gprbase = (void *)MX6_IOMUXC_BASE_ADDR + 0x4000; uint32_t val; - struct clk *clk; phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, ar8031_phy_fixup); @@ -193,23 +191,6 @@ static int imx6sx_sdb_setup_fec(void) /* Active high for ncp692 */ gpio_direction_output(IMX_GPIO_NR(4, 16), 1); - clk = clk_lookup("enet_ptp_25m"); - if (IS_ERR(clk)) - goto err; - - clk_enable(clk); - - clk = clk_lookup("enet_ref"); - if (IS_ERR(clk)) - goto err; - clk_enable(clk); - - clk = clk_lookup("enet2_ref_125m"); - if (IS_ERR(clk)) - goto err; - - clk_enable(clk); - val = readl(gprbase + IOMUXC_GPR1); /* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ val &= ~(1 << 13); @@ -226,12 +207,6 @@ static int imx6sx_sdb_setup_fec(void) gpio_direction_output(IMX_GPIO_NR(2, 7), 0); udelay(500); gpio_set_value(IMX_GPIO_NR(2, 7), 1); - - return 0; -err: - pr_err("Setting up DFEC\n"); - - return -EIO; } static int imx6sx_sdb_coredevices_init(void) diff --git a/arch/arm/boards/gateworks-ventana/board.c b/arch/arm/boards/gateworks-ventana/board.c index 82dba7c93d..3ff142ee42 100644 --- a/arch/arm/boards/gateworks-ventana/board.c +++ b/arch/arm/boards/gateworks-ventana/board.c @@ -24,6 +24,19 @@ #include "gsc.h" +static int gw54xx_wdog_of_fixup(struct device_node *root, void *context) +{ + struct device_node *np; + + /* switch to the watchdog with internal reset capabilities */ + np = of_find_node_by_name(root, "wdog@020c0000"); + of_device_disable(np); + np = of_find_node_by_name(root, "wdog@020bc000"); + of_device_enable(np); + + return 0; +} + static int gw54xx_devices_init(void) { struct i2c_client client; @@ -60,6 +73,10 @@ static int gw54xx_devices_init(void) of_eth_register_ethaddr(dnode, mac); } + /* boards before rev E don't have the external watchdog signal */ + if (gsc_get_rev(&client) < 'E') + of_register_fixup(gw54xx_wdog_of_fixup, NULL); + imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); barebox_set_hostname("gw54xx"); diff --git a/arch/arm/boards/gateworks-ventana/gsc.c b/arch/arm/boards/gateworks-ventana/gsc.c index 3614230482..92244d12da 100644 --- a/arch/arm/boards/gateworks-ventana/gsc.c +++ b/arch/arm/boards/gateworks-ventana/gsc.c @@ -65,3 +65,17 @@ int gsc_i2c_write(struct i2c_client *client, u32 addr, const u8 *buf, u16 count) return ret; } + +char gsc_get_rev(struct i2c_client *client) +{ + int i; + u8 model[16]; + + gsc_i2c_read(client, 0x30, model, 16); + for (i = sizeof(model) - 1; i > 0; i--) { + if (model[i] >= 'A') + return model[i]; + } + + return 'A'; +} diff --git a/arch/arm/boards/gateworks-ventana/gsc.h b/arch/arm/boards/gateworks-ventana/gsc.h index a6e7e2232d..13f226265c 100644 --- a/arch/arm/boards/gateworks-ventana/gsc.h +++ b/arch/arm/boards/gateworks-ventana/gsc.h @@ -56,3 +56,5 @@ */ int gsc_i2c_read(struct i2c_client *client, u32 addr, u8 *buf, u16 count); int gsc_i2c_write(struct i2c_client *client, u32 addr, const u8 *buf, u16 count); + +char gsc_get_rev(struct i2c_client *client); diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index ed9453bdda..717a22963a 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -31,7 +31,6 @@ #include <mach/bbu.h> #include <platform_data/eth-fec.h> #include <mfd/imx6q-iomuxc-gpr.h> -#include <linux/clk.h> #include <linux/micrel_phy.h> #include <globalvar.h> @@ -97,48 +96,6 @@ int ksz8081_phy_fixup(struct phy_device *phydev) return 0; } -static int imx6ul_setup_fec(void) -{ - void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000; - uint32_t val; - struct clk *clk; - - phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, - ksz8081_phy_fixup); - - clk = clk_lookup("enet_ptp"); - if (IS_ERR(clk)) - goto err; - - clk_enable(clk); - - clk = clk_lookup("enet_ref"); - if (IS_ERR(clk)) - goto err; - clk_enable(clk); - - clk = clk_lookup("enet_ref_125m"); - if (IS_ERR(clk)) - goto err; - - clk_enable(clk); - - val = readl(gprbase + IOMUXC_GPR1); - /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/ - val &= ~(1 << 13); - val |= (1 << 17); - /* Use 50M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], set gpr1[18]*/ - val &= ~(1 << 14); - val |= (1 << 18); - writel(val, gprbase + IOMUXC_GPR1); - - return 0; -err: - pr_err("Setting up DFEC\n"); - - return -EIO; -} - static int physom_imx6_devices_init(void) { int ret; @@ -178,7 +135,10 @@ static int physom_imx6_devices_init(void) barebox_set_hostname("phyCORE-i.MX6UL"); default_environment_path = "/chosen/environment-nand"; default_envdev = "NAND flash"; - imx6ul_setup_fec(); + + phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, + ksz8081_phy_fixup); + } else return 0; diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg new file mode 100644 index 0000000000..4a827e4dfa --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg @@ -0,0 +1,9 @@ + +#define SETUP_MDCFG0 \ + wm 32 0x021B000C 0x676B52F3 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021B0040 0x00000047; \ + wm 32 0x021B0000 0x83180000 + +#include "flash-header-phytec-pcl063.h" diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 3ab88f4a52..07ac4437ab 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -54,7 +54,8 @@ static void __noreturn start_imx6_phytec_common(uint32_t size, int cpu_type = __imx6_cpu_type(); void *fdt; - if (cpu_type == IMX6_CPUTYPE_IMX6UL) { + if (cpu_type == IMX6_CPUTYPE_IMX6UL + || cpu_type == IMX6_CPUTYPE_IMX6ULL) { arm_cpu_lowlevel_init(); /* OCRAM Free Area is 0x00907000 to 0x00918000 (68KB) */ arm_setup_stack(0x00910000 - 8); @@ -69,7 +70,8 @@ static void __noreturn start_imx6_phytec_common(uint32_t size, fdt = fdt_blob_fixed_offset - get_runtime_offset(); - if (cpu_type == IMX6_CPUTYPE_IMX6UL) + if (cpu_type == IMX6_CPUTYPE_IMX6UL + || cpu_type == IMX6_CPUTYPE_IMX6ULL) barebox_arm_entry(0x80000000, size, fdt); else barebox_arm_entry(0x10000000, size, fdt); @@ -111,3 +113,4 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false); +PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_256mb, imx6ull_phytec_phycore_som, SZ_256M, false); diff --git a/arch/arm/boards/technexion-pico-hobbit/Makefile b/arch/arm/boards/technexion-pico-hobbit/Makefile new file mode 100644 index 0000000000..b60dcd2bc1 --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/Makefile @@ -0,0 +1,7 @@ +obj-y += board.o +lwl-y += lowlevel.o +extra-y += flash-header-imx6ul-pico-hobbit-256.dcd.S \ + flash-header-imx6ul-pico-hobbit-256.dcd \ + flash-header-imx6ul-pico-hobbit-512.dcd.S \ + flash-header-imx6ul-pico-hobbit-512.dcd +bbenv-y += defaultenv-pico-hobbit diff --git a/arch/arm/boards/technexion-pico-hobbit/board.c b/arch/arm/boards/technexion-pico-hobbit/board.c new file mode 100644 index 0000000000..d3109fc390 --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/board.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2017 Michael Grzeschik, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + * + */ + +#include <asm/armlinux.h> +#include <asm/io.h> +#include <bootsource.h> +#include <common.h> +#include <environment.h> +#include <envfs.h> +#include <gpio.h> +#include <init.h> +#include <mach/generic.h> +#include <mach/imx6-regs.h> +#include <mach/imx6.h> +#include <mach/bbu.h> +#include <linux/sizes.h> +#include <linux/phy.h> +#include <mfd/imx6q-iomuxc-gpr.h> + +#include <linux/micrel_phy.h> + +static int ksz8081_phy_fixup(struct phy_device *dev) +{ + phy_write(dev, 0x1f, 0x8190); + phy_write(dev, 0x16, 0x202); + + return 0; +} + +static int pico_hobbit_device_init(void) +{ + if (!of_machine_is_compatible("technexion,imx6ul-pico-hobbit")) + return 0; + + phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, + ksz8081_phy_fixup); + + imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc0.barebox", + BBU_HANDLER_FLAG_DEFAULT); + + barebox_set_hostname("pico-hobbit"); + + defaultenv_append_directory(defaultenv_pico_hobbit); + + return 0; +} +device_initcall(pico_hobbit_device_init); diff --git a/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/init/automount b/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/init/automount new file mode 100644 index 0000000000..fdcfa36045 --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/init/automount @@ -0,0 +1,11 @@ +#!/bin/sh + +# automount tftp server based on $eth1.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth1 && mount -t tftp $eth1.serverip /mnt/tftp' + +# automount nfs server's nfsroot + +mkdir -p /mnt/nfs +automount /mnt/nfs 'ifup eth1 && mount -t nfs ${eth1.serverip}:/home/${global.user}/nfsroot/${global.hostname} /mnt/nfs' diff --git a/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/network/eth1 b/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/network/eth1 new file mode 100644 index 0000000000..dfe63971df --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/defaultenv-pico-hobbit/network/eth1 @@ -0,0 +1,18 @@ +#!/bin/sh + +# ip setting (static/dhcp) +ip=dhcp +global.dhcp.vendor_id=barebox-${global.hostname} + +# static setup used if ip=static +ipaddr= +netmask= +gateway= +serverip= + +# MAC address if needed +#ethaddr=xx:xx:xx:xx:xx:xx + +# put code to discover eth1 (i.e. 'usb') to /env/network/eth1-discover + +exit 0 diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg new file mode 100644 index 0000000000..12cda04e60 --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg @@ -0,0 +1,64 @@ +loadaddr 0x80000000 +soc imx6 +dcdofs 0x400 + +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +wm 32 0x020E04B4 0x000C0000 +wm 32 0x020E04AC 0x00000000 +wm 32 0x020E027C 0x00000030 +wm 32 0x020E0250 0x00000030 +wm 32 0x020E024C 0x00000030 +wm 32 0x020E0490 0x00000030 +wm 32 0x020E0288 0x00000030 +wm 32 0x020E0270 0x00000000 +wm 32 0x020E0260 0x00000030 +wm 32 0x020E0264 0x00000030 +wm 32 0x020E04A0 0x00000030 +wm 32 0x020E0494 0x00020000 +wm 32 0x020E0280 0x00000030 +wm 32 0x020E0284 0x00000030 +wm 32 0x020E04B0 0x00020000 +wm 32 0x020E0498 0x00000030 +wm 32 0x020E04A4 0x00000030 +wm 32 0x020E0244 0x00000030 +wm 32 0x020E0248 0x00000030 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B0800 0xA1390003 +wm 32 0x021B080C 0x00000000 +wm 32 0x021B083C 0x01380134 +wm 32 0x021B0848 0x40404244 +wm 32 0x021B0850 0x40405050 +wm 32 0x021B081C 0x33333333 +wm 32 0x021B0820 0x33333333 +wm 32 0x021B082C 0xf3333333 +wm 32 0x021B0830 0xf3333333 +wm 32 0x021B08C0 0x00921012 +wm 32 0x021B08b8 0x00000800 +wm 32 0x021B0004 0x0002002D +wm 32 0x021B0008 0x00333030 +wm 32 0x021B000C 0x676B52F3 +wm 32 0x021B0010 0xB66D8B63 +wm 32 0x021B0014 0x01FF00DB +wm 32 0x021B0018 0x00201740 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B002C 0x000026D2 +wm 32 0x021B0030 0x006B1023 +wm 32 0x021B0040 0x00000047 +wm 32 0x021B0000 0x83180000 +wm 32 0x021B001C 0x02008032 +wm 32 0x021B001C 0x00008033 +wm 32 0x021B001C 0x00048031 +wm 32 0x021B001C 0x15208030 +wm 32 0x021B001C 0x04008040 +wm 32 0x021B0020 0x00000800 +wm 32 0x021B0818 0x00000227 +wm 32 0x021B0004 0x0002552D +wm 32 0x021B0404 0x00011006 +wm 32 0x021B001C 0x00000000 diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg new file mode 100644 index 0000000000..0a1915b982 --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg @@ -0,0 +1,65 @@ +loadaddr 0x80000000 +soc imx6 +dcdofs 0x400 + +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +wm 32 0x020E04B4 0x000C0000 +wm 32 0x020E04AC 0x00000000 +wm 32 0x020E027C 0x00000030 +wm 32 0x020E0250 0x00000030 +wm 32 0x020E024C 0x00000030 +wm 32 0x020E0490 0x00000030 +wm 32 0x020E0288 0x00000030 +wm 32 0x020E0270 0x00000000 +wm 32 0x020E0260 0x00000030 +wm 32 0x020E0264 0x00000030 +wm 32 0x020E04A0 0x00000030 +wm 32 0x020E0494 0x00020000 +wm 32 0x020E0280 0x00000030 +wm 32 0x020E0284 0x00000030 +wm 32 0x020E04B0 0x00020000 +wm 32 0x020E0498 0x00000030 +wm 32 0x020E04A4 0x00000030 +wm 32 0x020E0244 0x00000030 +wm 32 0x020E0248 0x00000030 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B0800 0xA1390003 +wm 32 0x021B080C 0x00000000 +wm 32 0x021B083C 0x41570155 +wm 32 0x021B0848 0x4040474A +wm 32 0x021B0850 0x40405550 +wm 32 0x021B081C 0x33333333 +wm 32 0x021B0820 0x33333333 +wm 32 0x021B082C 0xf3333333 +wm 32 0x021B0830 0xf3333333 +wm 32 0x021B08C0 0x00921012 +wm 32 0x021B08b8 0x00000800 +wm 32 0x021B0004 0x0002002D +wm 32 0x021B0008 0x1b333030 +wm 32 0x021B000C 0x676B52F3 +wm 32 0x021B0010 0xB66D0B63 +wm 32 0x021B0014 0x01FF00DB +wm 32 0x021B0018 0x00201740 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B002C 0x000026D2 +wm 32 0x021B0030 0x006B1023 +wm 32 0x021B0040 0x0000004f +wm 32 0x021B0000 0x84180000 +wm 32 0x021B0890 0x23400a38 +wm 32 0x021B001C 0x02008032 +wm 32 0x021B001C 0x00008033 +wm 32 0x021B001C 0x00048031 +wm 32 0x021B001C 0x15208030 +wm 32 0x021B001C 0x04008040 +wm 32 0x021B0020 0x00000800 +wm 32 0x021B0818 0x00000227 +wm 32 0x021B0004 0x0002552D +wm 32 0x021B0404 0x00011006 +wm 32 0x021B001C 0x00000000 diff --git a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c new file mode 100644 index 0000000000..aad55127bf --- /dev/null +++ b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c @@ -0,0 +1,78 @@ +#include <common.h> +#include <linux/sizes.h> +#include <mach/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/imx6-regs.h> +#include <io.h> +#include <debug_ll.h> +#include <mach/esdctl.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <image-metadata.h> + +#define MX6_UART6_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x7C000) + +static inline void setup_uart(void) +{ + void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); + void __iomem *uart = IOMEM(MX6_UART6_BASE_ADDR); + + imx6_ungate_all_peripherals(); + + writel(0x8, iomuxbase + 0x1d4); + writel(0x1b0b1, iomuxbase + 0x0460); + writel(0x8, iomuxbase + 0x1d8); + writel(0x1b0b1, iomuxbase + 0x0460); + + imx6_uart_setup(uart); + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static void __noreturn start_imx6_pico_hobbit_common(uint32_t size, + bool do_early_uart_config, + void *fdt_blob_fixed_offset) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + arm_setup_stack(0x00910000 - 8); + + arm_early_mmu_cache_invalidate(); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + if (do_early_uart_config && IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + /* disable all watchdog powerdown counters */ + writew(0x0, 0x020bc008); + writew(0x0, 0x020c0008); + writew(0x0, 0x021e4008); + + fdt = fdt_blob_fixed_offset - get_runtime_offset(); + + imx6ul_barebox_entry(fdt); +} + +BAREBOX_IMD_TAG_STRING(pico_hobbit_mx6_memsize_SZ_256M, IMD_TYPE_PARAMETER, "memsize=256", 0); +BAREBOX_IMD_TAG_STRING(pico_hobbit_mx6_memsize_SZ_512M, IMD_TYPE_PARAMETER, "memsize=512", 0); + +#define EDM1_ENTRY(name, fdt_name, memory_size, do_early_uart_config) \ + ENTRY_FUNCTION(name, r0, r1, r2) \ + { \ + extern char __dtb_##fdt_name##_start[]; \ + \ + IMD_USED(pico_hobbit_mx6_memsize_##memory_size); \ + \ + start_imx6_pico_hobbit_common(memory_size, do_early_uart_config, \ + __dtb_##fdt_name##_start); \ + } + +EDM1_ENTRY(start_imx6ul_pico_hobbit_256mb, imx6ul_pico_hobbit, SZ_256M, true); +EDM1_ENTRY(start_imx6ul_pico_hobbit_512mb, imx6ul_pico_hobbit, SZ_512M, true); diff --git a/arch/arm/boards/technexion-wandboard/board.c b/arch/arm/boards/technexion-wandboard/board.c index e7b51cc728..2e1f6254c2 100644 --- a/arch/arm/boards/technexion-wandboard/board.c +++ b/arch/arm/boards/technexion-wandboard/board.c @@ -63,7 +63,8 @@ static int ar8031_phy_fixup(struct phy_device *dev) static int wandboard_device_init(void) { - if (!of_machine_is_compatible("wand,imx6dl-wandboard")) + if (!of_machine_is_compatible("wand,imx6dl-wandboard") && + !of_machine_is_compatible("wand,imx6q-wandboard")) return 0; phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, ar8031_phy_fixup); diff --git a/arch/arm/boards/technexion-wandboard/lowlevel.c b/arch/arm/boards/technexion-wandboard/lowlevel.c index d3eb9a03e9..9aae429d45 100644 --- a/arch/arm/boards/technexion-wandboard/lowlevel.c +++ b/arch/arm/boards/technexion-wandboard/lowlevel.c @@ -276,7 +276,6 @@ static unsigned long wandboard_dram_init(void) __udelay(100); - mmdc_do_write_level_calibration(); mmdc_do_dqs_calibration(); #ifdef DEBUG mmdc_print_calibration_results(); @@ -286,11 +285,25 @@ static unsigned long wandboard_dram_init(void) static void setup_uart(void) { + int cpu_type = __imx6_cpu_type(); void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; - /* mux the uart */ - writel(0x00000003, iomuxbase + 0x4c); - writel(0x00000000, iomuxbase + 0x8fc); + /* mux UART1 TX on PAD_CSI0_DATA10 */ + switch (cpu_type) { + case IMX6_CPUTYPE_IMX6S: + case IMX6_CPUTYPE_IMX6DL: + writel(0x00000003, iomuxbase + 0x4c); + writel(0x0001b0b1, iomuxbase + 0x360); + writel(0x00000000, iomuxbase + 0x8fc); + break; + case IMX6_CPUTYPE_IMX6Q: + writel(0x00000003, iomuxbase + 0x280); + writel(0x0001b0b1, iomuxbase + 0x650); + writel(0x00000001, iomuxbase + 0x920); + break; + default: + return; + } imx6_ungate_all_peripherals(); imx6_uart_setup((void *)MX6_UART1_BASE_ADDR); diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index ab837cc55f..7bbd93240d 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -23,6 +23,7 @@ CONFIG_MACH_SABRESD=y CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB=y CONFIG_MACH_NITROGEN6=y CONFIG_MACH_SOLIDRUN_MICROSOM=y +CONFIG_MACH_TECHNEXION_PICO_HOBBIT=y CONFIG_MACH_TECHNEXION_WANDBOARD=y CONFIG_MACH_EMBEST_RIOTBOARD=y CONFIG_MACH_UDOO=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2342d35a4b..806d386001 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -53,7 +53,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \ imx6q-phytec-phycore-som-emmc.dtb.o \ imx6dl-phytec-phycore-som-nand.dtb.o \ imx6dl-phytec-phycore-som-emmc.dtb.o \ - imx6ul-phytec-phycore-som.dtb.o + imx6ul-phytec-phycore-som.dtb.o \ + imx6ull-phytec-phycore-som.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o @@ -74,6 +75,7 @@ pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-humm imx6dl-hummingboard2.dtb.o imx6q-hummingboard2.dtb.o \ imx6q-h100.dtb.o pbl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o +pbl-dtb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o pbl-dtb-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o pbl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o pbl-dtb-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o diff --git a/arch/arm/dts/imx6q-gw54xx.dts b/arch/arm/dts/imx6q-gw54xx.dts index 8113542c66..ec0f3632ba 100644 --- a/arch/arm/dts/imx6q-gw54xx.dts +++ b/arch/arm/dts/imx6q-gw54xx.dts @@ -22,3 +22,11 @@ &sata { status = "okay"; }; + +&wdog1 { + status = "okay"; +}; + +&wdog2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts index 65a936551e..73f7dbe9a6 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts @@ -13,173 +13,29 @@ /dts-v1/; #include <arm/imx6ul.dtsi> +#include "imx6ul-phytec-phycore-som.dtsi" / { model = "Phytec phyCORE-i.MX6 Ultra Lite SOM"; compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; - - chosen { - linux,stdout-path = &uart1; - - environment-nand { - compatible = "barebox,environment"; - device-path = &gpmi, "partname:barebox-environment"; - status = "disabled"; - }; - - environment-sd1 { - compatible = "barebox,environment"; - device-path = &usdhc1, "partname:barebox-environment"; - status = "disabled"; - }; - }; }; &fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - reg = <1>; - }; - }; }; &gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - fsl,no-blockmark-swap; status = "okay"; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0x400000>; - }; - - partition@400000 { - label = "barebox-environment"; - reg = <0x400000 0x100000>; - }; - - partition@500000 { - label = "root"; - reg = <0x500000 0x0>; - }; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 =<&pinctrl_i2c1>; - clock-frequency = <100000>; status = "okay"; - - eeprom@52 { - compatible = "cat,24c32"; - reg = <0x52>; - }; }; &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; status = "okay"; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "barebox"; - reg = <0x0 0xe0000>; - }; - - partition@e0000 { - label = "barebox-environment"; - reg = <0xe0000 0x20000>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - - imx6ul-phytec-phycore-som { - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 - >; - }; - - pinctrl_i2c1: i2cgrp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ - >; - }; - }; }; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi new file mode 100644 index 0000000000..96beef4e72 --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp <c.hemp@phytec.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + chosen { + linux,stdout-path = &uart1; + + environment-nand { + compatible = "barebox,environment"; + device-path = &gpmi, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-sd1 { + compatible = "barebox,environment"; + device-path = &usdhc1, "partname:barebox-environment"; + status = "disabled"; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + fsl,no-blockmark-swap; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "barebox-environment"; + reg = <0x400000 0x100000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "disabled"; + + eeprom@52 { + compatible = "cat,24c32"; + reg = <0x52>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx6ul-phytec-phycore-som { + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2cgrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6ul-pico-hobbit.dts b/arch/arm/dts/imx6ul-pico-hobbit.dts new file mode 100644 index 0000000000..478b2411b4 --- /dev/null +++ b/arch/arm/dts/imx6ul-pico-hobbit.dts @@ -0,0 +1,35 @@ +#include <arm/imx6ul-pico-hobbit.dts> + +/ { + chosen { + linux,stdout-path = &uart1; + + environment@0 { + compatible = "barebox,environment"; + device-path = &environment_usdhc1; + }; + }; + + memory { + /delete-property/ device_type; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xc0000>; + }; + + environment_usdhc1: partition@c0000 { + label = "barebox-environment"; + reg = <0xc0000 0x40000>; + }; +}; + +&fec2 { + phy-reset-post-delay = <1>; +}; diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts new file mode 100644 index 0000000000..de04132a02 --- /dev/null +++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller <s.riedmueller@phytec.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <arm/imx6ull.dtsi> +#include "imx6ul-phytec-phycore-som.dtsi" + +/ { + model = "Phytec phyCORE-i.MX6 ULL SOM"; + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ull"; +}; + +&fec1 { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 80f53ce124..6110924af6 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -343,6 +343,12 @@ config MACH_SOLIDRUN_MICROSOM bool "SolidRun MicroSOM based devices" select ARCH_IMX6 +config MACH_TECHNEXION_PICO_HOBBIT + bool "Technexion Pico Hobbit" + select ARCH_IMX6 + select ARCH_IMX6UL + select ARM_USE_COMPRESSED_DTB + config MACH_TECHNEXION_WANDBOARD bool "Technexion Wandboard" select ARCH_IMX6 diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index 19907397f9..9400105c66 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -67,6 +67,8 @@ static int imx_soc_from_dt(void) return IMX_CPU_IMX6; if (of_machine_is_compatible("fsl,imx6ul")) return IMX_CPU_IMX6; + if (of_machine_is_compatible("fsl,imx6ull")) + return IMX_CPU_IMX6; if (of_machine_is_compatible("fsl,imx7s")) return IMX_CPU_IMX7; if (of_machine_is_compatible("fsl,imx7d")) diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index 44a8dbefd0..5afbf6b30f 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -121,6 +121,16 @@ void imx6_setup_ipu_qos(void) } } +void imx6ul_enet_clk_init(void) +{ + void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000; + uint32_t val; + + val = readl(gprbase + IOMUXC_GPR1); + val |= (0x3 << 17); + writel(val, gprbase + IOMUXC_GPR1); +} + int imx6_init(void) { const char *cputypestr; @@ -159,6 +169,10 @@ int imx6_init(void) break; case IMX6_CPUTYPE_IMX6UL: cputypestr = "i.MX6 UltraLite"; + imx6ul_enet_clk_init(); + break; + case IMX6_CPUTYPE_IMX6ULL: + cputypestr = "i.MX6 ULL"; break; default: cputypestr = "unknown i.MX6"; diff --git a/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h b/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h index f4804fe63f..60f730f8ec 100644 --- a/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h +++ b/arch/arm/mach-imx/include/mach/habv3-imx25-gencsf.h @@ -4,8 +4,8 @@ * are expected in these config variables: * * CONFIG_HABV3_SRK_PEM - * CONFIG_HABV3_SRK_PEM - * CONFIG_HABV3_IMG_CRT_PEM + * CONFIG_HABV3_CSF_CRT_DER + * CONFIG_HABV3_IMG_CRT_DER */ super_root_key CONFIG_HABV3_SRK_PEM @@ -23,21 +23,26 @@ hab [Install SRK] hab File = "not-used" hab [Install CSFK] +/* target key index in keystore 1 */ hab File = CONFIG_HABV3_CSF_CRT_DER hab [Authenticate CSF] -/* below is the command that unlock the access to the DryIce registers */ +/* unlock the access to the DryIce registers */ hab [Write Data] hab Width = 4 hab Address Data = 0x53FFC03C 0xCA693569 hab [Install Key] +/* verification key index in key store (1...4) */ +/* in contrast to documentation 0 seems to be valid, too */ hab Verification index = 1 +/* target key index in key store (1...4) */ hab Target index = 2 hab File = CONFIG_HABV3_IMG_CRT_DER hab [Authenticate Data] +/* verification key index in key store (2...4) */ hab Verification index = 2 hab_blocks diff --git a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h index 1a143a8b18..0649caa0cb 100644 --- a/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h +++ b/arch/arm/mach-imx/include/mach/habv4-imx6-gencsf.h @@ -22,6 +22,7 @@ hab # SRK index within SRK-Table 0..3 hab Source index = 0 hab [Install CSFK] +/* target key index in keystore 1 */ hab File = CONFIG_HABV4_CSF_CRT_PEM hab [Authenticate CSF] @@ -31,14 +32,14 @@ hab Engine = CAAM hab Features = RNG hab [Install Key] -/* verification key index in key store (0, 2...5) */ +/* verification key index in key store (0, 2...4) */ hab Verification index = 0 -/* target key index in key store (2...5) */ +/* target key index in key store (2...4) */ hab Target index = 2 hab File = CONFIG_HABV4_IMG_CRT_PEM hab [Authenticate Data] -/* verification key index in key store (2...5) */ +/* verification key index in key store (2...4) */ hab Verification index = 2 -hab_blocks
\ No newline at end of file +hab_blocks diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h index 327676bc69..6ad53433cb 100644 --- a/arch/arm/mach-imx/include/mach/imx6.h +++ b/arch/arm/mach-imx/include/mach/imx6.h @@ -18,6 +18,7 @@ void imx6_init_lowlevel(void); #define IMX6_CPUTYPE_IMX6D 0x263 #define IMX6_CPUTYPE_IMX6Q 0x463 #define IMX6_CPUTYPE_IMX6UL 0x164 +#define IMX6_CPUTYPE_IMX6ULL 0x165 #define SCU_CONFIG 0x04 @@ -82,6 +83,7 @@ DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D); DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX); DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL); DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL); +DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL); static inline int __imx6_cpu_revision(void) { |