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-rw-r--r--arch/mips/lib/Makefile2
-rw-r--r--arch/mips/lib/barebox.lds.S6
-rw-r--r--arch/mips/lib/bootm.c25
-rw-r--r--arch/mips/lib/c-r4k.c68
-rw-r--r--arch/mips/lib/cpu-probe.c61
-rw-r--r--arch/mips/lib/cpuinfo.c6
-rw-r--r--arch/mips/lib/dma-default.c47
-rw-r--r--arch/mips/lib/genex.S31
-rw-r--r--arch/mips/lib/memcpy.S37
-rw-r--r--arch/mips/lib/pbl.lds.S7
-rw-r--r--arch/mips/lib/reloc.c13
-rw-r--r--arch/mips/lib/setjmp.S48
-rw-r--r--arch/mips/lib/traps.c5
13 files changed, 216 insertions, 140 deletions
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 1ef340202a..00d72d0a1a 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -10,7 +10,7 @@ obj-y += reloc.o
obj-y += sections.o
obj-y += shutdown.o
obj-y += dma-default.o
-obj-$(CONFIG_HAS_ARCH_SJLJ) += setjmp.o
+obj-$(CONFIG_ARCH_HAS_SJLJ) += setjmp.o
obj-$(CONFIG_MIPS_OPTIMIZED_STRING_FUNCTIONS) += memcpy.o
obj-$(CONFIG_MIPS_OPTIMIZED_STRING_FUNCTIONS) += memset.o
diff --git a/arch/mips/lib/barebox.lds.S b/arch/mips/lib/barebox.lds.S
index c954df41f3..0720f9295d 100644
--- a/arch/mips/lib/barebox.lds.S
+++ b/arch/mips/lib/barebox.lds.S
@@ -3,10 +3,9 @@
* Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
*/
+#include <asm/barebox.lds.h>
-#include <asm-generic/barebox.lds.h>
-
-OUTPUT_ARCH(mips)
+OUTPUT_ARCH(BAREBOX_OUTPUT_ARCH)
ENTRY(_start)
SECTIONS
{
@@ -67,5 +66,4 @@ SECTIONS
. = ALIGN(4);
__bss_stop = .;
}
-
}
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 655535737e..86573dec7f 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -16,12 +16,21 @@
static int do_bootm_barebox(struct image_data *data)
{
- void (*barebox)(void);
+ void (*barebox)(int, void *);
+ void *fdt = NULL;
barebox = read_file(data->os_file, NULL);
if (!barebox)
return -EINVAL;
+ if (data->oftree_file) {
+ fdt = bootm_get_devicetree(data);
+ if (IS_ERR(fdt)) {
+ pr_err("Failed to load dtb\n");
+ return PTR_ERR(fdt);
+ }
+ }
+
if (data->dryrun) {
free(barebox);
return 0;
@@ -29,7 +38,7 @@ static int do_bootm_barebox(struct image_data *data)
shutdown_barebox();
- barebox();
+ barebox(-2, fdt);
restart_machine();
}
@@ -57,25 +66,25 @@ static int do_bootm_elf(struct image_data *data)
fdt = bootm_get_devicetree(data);
if (IS_ERR(fdt)) {
- ret = PTR_ERR(fdt);
- goto bootm_free_fdt;
+ pr_err("Failed to load dtb\n");
+ return PTR_ERR(fdt);
}
- pr_info("Starting application at 0x%08lx, dts 0x%08lx...\n",
- phys_to_virt(data->os_address), data->of_root_node);
+ pr_info("Starting application at 0x%08lx, dts 0x%p...\n",
+ data->os_address, data->of_root_node);
if (data->dryrun)
goto bootm_free_fdt;
ret = of_overlay_load_firmware();
if (ret)
- return ret;
+ goto bootm_free_fdt;
shutdown_barebox();
entry = (void *) (unsigned long) data->os_address;
- entry(-2, phys_to_virt((unsigned long)fdt));
+ entry(-2, fdt);
pr_err("ELF application terminated\n");
ret = -EINVAL;
diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index 8bc0a7a411..44cf57d99b 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -13,6 +13,8 @@
#include <asm/cpu-info.h>
#include <asm/bitops.h>
+#define INDEX_BASE CKSEG0
+
#define cache_op(op,addr) \
__asm__ __volatile__( \
" .set push \n" \
@@ -23,67 +25,67 @@
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop) \
+static inline void blast_##pfx##cache(void) \
+{ \
+ const unsigned long lsize = current_cpu_data.desc.linesz; \
+ const unsigned long start = INDEX_BASE; \
+ const unsigned long size = current_cpu_data.desc.waysize \
+ * current_cpu_data.desc.ways; \
+ const unsigned long aend = start + size - 1; \
+ unsigned long addr; \
+ \
+ if (current_cpu_data.desc.flags & MIPS_CACHE_NOT_PRESENT) \
+ return; \
+ \
+ for (addr = start; addr <= aend; addr += lsize) \
+ cache_op(indexop, addr); \
+}
+
#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop) \
static inline void blast_##pfx##cache##_range(unsigned long start, \
unsigned long end) \
{ \
- unsigned long lsize = current_cpu_data.desc.linesz; \
- unsigned long addr = start & ~(lsize - 1); \
- unsigned long aend = (end - 1) & ~(lsize - 1); \
+ const unsigned long lsize = current_cpu_data.desc.linesz; \
+ const unsigned long astart = ALIGN_DOWN(start, lsize); \
+ const unsigned long aend = ALIGN_DOWN(end - 1, lsize); \
+ unsigned long addr; \
\
if (current_cpu_data.desc.flags & MIPS_CACHE_NOT_PRESENT) \
return; \
\
- while (1) { \
+ for (addr = astart; addr <= aend; addr += lsize) \
cache_op(hitop, addr); \
- if (addr == aend) \
- break; \
- addr += lsize; \
- } \
}
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D)
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD)
+
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD)
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D)
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD)
void flush_cache_all(void)
{
- struct cpuinfo_mips *c = &current_cpu_data;
- unsigned long lsize;
- unsigned long addr;
- unsigned long aend;
- unsigned int icache_size, dcache_size;
-
- dcache_size = c->dcache.waysize * c->dcache.ways;
- lsize = c->dcache.linesz;
- aend = (CKSEG0 + dcache_size - 1) & ~(lsize - 1);
- for (addr = CKSEG0; addr <= aend; addr += lsize)
- cache_op(Index_Writeback_Inv_D, addr);
-
- icache_size = c->icache.waysize * c->icache.ways;
- lsize = c->icache.linesz;
- aend = (CKSEG0 + icache_size - 1) & ~(lsize - 1);
- for (addr = CKSEG0; addr <= aend; addr += lsize)
- cache_op(Index_Invalidate_I, addr);
-
- /* secondatory cache skipped */
+ blast_dcache();
+ blast_icache();
+ blast_scache();
}
void dma_flush_range(unsigned long start, unsigned long end)
{
blast_dcache_range(start, end);
-
- /* secondatory cache skipped */
+ blast_scache_range(start, end);
}
void dma_inv_range(unsigned long start, unsigned long end)
{
blast_inv_dcache_range(start, end);
-
- /* secondatory cache skipped */
+ blast_inv_scache_range(start, end);
}
-void r4k_cache_init(void);
-
static void probe_pcache(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
diff --git a/arch/mips/lib/cpu-probe.c b/arch/mips/lib/cpu-probe.c
index cbde43a595..fc20281597 100644
--- a/arch/mips/lib/cpu-probe.c
+++ b/arch/mips/lib/cpu-probe.c
@@ -17,7 +17,7 @@
#include <asm-generic/memory_layout.h>
#include <init.h>
-const char *__cpu_name;
+const char *__cpu_name = "unknown";
struct cpuinfo_mips cpu_data[1];
static char unknown_isa[] = KERN_ERR \
@@ -102,15 +102,72 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
{
decode_configs(c);
switch (c->processor_id & 0xff00) {
+ case PRID_IMP_QEMU_GENERIC:
+ c->cputype = CPU_QEMU_GENERIC;
+ __cpu_name = "MIPS GENERIC QEMU";
+ break;
+ case PRID_IMP_4KC:
+ c->cputype = CPU_4KC;
+ __cpu_name = "MIPS 4Kc";
+ break;
+ case PRID_IMP_4KEC:
+ case PRID_IMP_4KECR2:
+ c->cputype = CPU_4KEC;
+ __cpu_name = "MIPS 4KEc";
+ break;
+ case PRID_IMP_4KSC:
+ case PRID_IMP_4KSD:
+ c->cputype = CPU_4KSC;
+ __cpu_name = "MIPS 4KSc";
+ break;
+ case PRID_IMP_5KC:
+ c->cputype = CPU_5KC;
+ __cpu_name = "MIPS 5Kc";
+ break;
+ case PRID_IMP_5KE:
+ c->cputype = CPU_5KE;
+ __cpu_name = "MIPS 5KE";
+ break;
+ case PRID_IMP_20KC:
+ c->cputype = CPU_20KC;
+ __cpu_name = "MIPS 20Kc";
+ break;
case PRID_IMP_24K:
- case PRID_IMP_24KE:
c->cputype = CPU_24K;
__cpu_name = "MIPS 24Kc";
break;
+ case PRID_IMP_24KE:
+ c->cputype = CPU_24K;
+ __cpu_name = "MIPS 24KEc";
+ break;
+ case PRID_IMP_25KF:
+ c->cputype = CPU_25KF;
+ __cpu_name = "MIPS 25Kc";
+ break;
+ case PRID_IMP_34K:
+ c->cputype = CPU_34K;
+ __cpu_name = "MIPS 34Kc";
+ break;
case PRID_IMP_74K:
c->cputype = CPU_74K;
__cpu_name = "MIPS 74Kc";
break;
+ case PRID_IMP_M14KC:
+ c->cputype = CPU_M14KC;
+ __cpu_name = "MIPS M14Kc";
+ break;
+ case PRID_IMP_M14KEC:
+ c->cputype = CPU_M14KEC;
+ __cpu_name = "MIPS M14KEc";
+ break;
+ case PRID_IMP_1004K:
+ c->cputype = CPU_1004K;
+ __cpu_name = "MIPS 1004Kc";
+ break;
+ case PRID_IMP_1074K:
+ c->cputype = CPU_1074K;
+ __cpu_name = "MIPS 1074Kc";
+ break;
}
}
diff --git a/arch/mips/lib/cpuinfo.c b/arch/mips/lib/cpuinfo.c
index fd27920f9b..41ec7b8d53 100644
--- a/arch/mips/lib/cpuinfo.c
+++ b/arch/mips/lib/cpuinfo.c
@@ -25,12 +25,12 @@ static int do_cpuinfo(int argc, char *argv[])
icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
- printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
+ printk("Primary instruction cache %ukB, %s, %s, linesize %d bytes.\n",
icache_size >> 10,
c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
way_string[c->icache.ways], c->icache.linesz);
- printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+ printk("Primary data cache %ukB, %s, %s, %s, linesize %d bytes\n",
dcache_size >> 10, way_string[c->dcache.ways],
(c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
(c->dcache.flags & MIPS_CACHE_ALIASES) ?
@@ -39,7 +39,7 @@ static int do_cpuinfo(int argc, char *argv[])
if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
return 0;
scache_size = c->scache.sets * c->scache.ways * c->scache.linesz;
- printk("Secondary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+ printk("Secondary data cache %ukB, %s, %s, %s, linesize %d bytes\n",
scache_size >> 10, way_string[c->scache.ways],
(c->scache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
(c->scache.flags & MIPS_CACHE_ALIASES) ?
diff --git a/arch/mips/lib/dma-default.c b/arch/mips/lib/dma-default.c
index fbe627c24c..74aa8af55c 100644
--- a/arch/mips/lib/dma-default.c
+++ b/arch/mips/lib/dma-default.c
@@ -4,45 +4,40 @@
*/
#include <dma.h>
+#include <linux/bug.h>
#include <asm/io.h>
-#if defined(CONFIG_CPU_MIPS32) || \
- defined(CONFIG_CPU_MIPS64)
-static inline void __dma_sync_mips(unsigned long addr, size_t size,
- enum dma_data_direction direction)
+void arch_sync_dma_for_cpu(void *vaddr, size_t size,
+ enum dma_data_direction dir)
{
- switch (direction) {
+ unsigned long start = (unsigned long)vaddr;
+
+ switch (dir) {
case DMA_TO_DEVICE:
- dma_flush_range(addr, addr + size);
break;
-
case DMA_FROM_DEVICE:
- dma_inv_range(addr, addr + size);
- break;
-
case DMA_BIDIRECTIONAL:
- dma_flush_range(addr, addr + size);
+ dma_inv_range(start, start + size);
break;
-
default:
BUG();
}
}
-#else
-static inline void __dma_sync_mips(void *addr, size_t size,
- enum dma_data_direction direction)
-{
-}
-#endif
-void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
- enum dma_data_direction dir)
+void arch_sync_dma_for_device(void *vaddr, size_t size,
+ enum dma_data_direction dir)
{
- __dma_sync_mips(address, size, dir);
-}
+ unsigned long start = (unsigned long)vaddr;
-void dma_sync_single_for_device(dma_addr_t address, size_t size,
- enum dma_data_direction dir)
-{
- __dma_sync_mips(address, size, dir);
+ switch (dir) {
+ case DMA_FROM_DEVICE:
+ dma_inv_range(start, start + size);
+ break;
+ case DMA_TO_DEVICE:
+ case DMA_BIDIRECTIONAL:
+ dma_flush_range(start, start + size);
+ break;
+ default:
+ BUG();
+ }
}
diff --git a/arch/mips/lib/genex.S b/arch/mips/lib/genex.S
index d75a652e4d..27dd9de67a 100644
--- a/arch/mips/lib/genex.S
+++ b/arch/mips/lib/genex.S
@@ -2,7 +2,6 @@
#include <asm/asm.h>
#include <asm/regdef.h>
-#include <asm/mipsregs.h>
#include <asm/stackframe.h>
.text
@@ -11,31 +10,19 @@
.set noreorder
.align 5
-/* Exception vector */
-NESTED(handle_reserved, 0, sp)
+NESTED(exception_vec, 0, sp)
+ j handle_reserved
+ nop
+EXPORT(exception_vec_end)
+END(exception_vec)
+
+handle_reserved:
SAVE_ALL
- la k0, barebox_exc_handler
- jal k0
+ PTR_LA k0, barebox_exc_handler
+ j k0
move a0, sp
- /* will never return here */
- END(handle_reserved)
-
-/* General exception vector */
-NESTED(except_vec3_generic, 0, sp)
- .set noat
- mfc0 k1, CP0_CAUSE
- la k0, exception_handlers
- andi k1, k1, 0x7c
- addu k0, k0, k1
- lw k0, (k0)
- nop
- jr k0
- nop
- END(except_vec3_generic)
- .set at
FEXPORT(ret_from_exception)
.set noat
RESTORE_ALL_AND_RET
- nop
.set at
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index cee0319dcf..5c01dbdcd3 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -20,7 +20,26 @@
#define src a1
#define len a2
-#define LOADK lw /* No exception */
+#ifdef CONFIG_64BIT
+
+#define LOAD(reg, addr) ld reg, addr
+#define LOADL(reg, addr) ldl reg, addr
+#define LOADR(reg, addr) ldr reg, addr
+#define STOREL(reg, addr) sdl reg, addr
+#define STORER(reg, addr) sdr reg, addr
+#define STORE(reg, addr) sd reg, addr
+#define ADD daddu
+#define SUB dsubu
+#define SRL dsrl
+#define SRA dsra
+#define SLL dsll
+#define SLLV dsllv
+#define SRLV dsrlv
+#define NBYTES 8
+#define LOG_NBYTES 3
+
+#else
+
#define LOAD(reg, addr) lw reg, addr
#define LOADL(reg, addr) lwl reg, addr
#define LOADR(reg, addr) lwr reg, addr
@@ -37,6 +56,8 @@
#define NBYTES 4
#define LOG_NBYTES 2
+#endif /* CONFIG_64BIT */
+
#define LOADB(reg, addr) lb reg, addr
#define STOREB(reg, addr) sb reg, addr
@@ -101,8 +122,8 @@ LEAF(memcpy) /* a0=dst a1=src a2=len */
LOAD(t2, UNIT(2)(src))
LOAD(t3, UNIT(3)(src))
SUB len, len, 8*NBYTES
- LOAD(t4, UNIT(4)(src))
- LOAD(t7, UNIT(5)(src))
+ LOAD(ta0, UNIT(4)(src))
+ LOAD(ta3, UNIT(5)(src))
STORE(t0, UNIT(0)(dst))
STORE(t1, UNIT(1)(dst))
LOAD(t0, UNIT(6)(src))
@@ -111,8 +132,8 @@ LEAF(memcpy) /* a0=dst a1=src a2=len */
ADD dst, dst, 8*NBYTES
STORE(t2, UNIT(-6)(dst))
STORE(t3, UNIT(-5)(dst))
- STORE(t4, UNIT(-4)(dst))
- STORE(t7, UNIT(-3)(dst))
+ STORE(ta0, UNIT(-4)(dst))
+ STORE(ta3, UNIT(-3)(dst))
STORE(t0, UNIT(-2)(dst))
STORE(t1, UNIT(-1)(dst))
bne len, rem, 1b
@@ -263,6 +284,12 @@ LEAF(memcpy) /* a0=dst a1=src a2=len */
COPY_BYTE(0)
COPY_BYTE(1)
+#ifdef CONFIG_64BIT
+ COPY_BYTE(2)
+ COPY_BYTE(3)
+ COPY_BYTE(4)
+ COPY_BYTE(5)
+#endif
LOADB(t0, NBYTES-2(src))
SUB len, len, 1
jr ra
diff --git a/arch/mips/lib/pbl.lds.S b/arch/mips/lib/pbl.lds.S
index 75069b0c50..4cf0398f33 100644
--- a/arch/mips/lib/pbl.lds.S
+++ b/arch/mips/lib/pbl.lds.S
@@ -4,13 +4,13 @@
* (C) Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*/
-#include <asm-generic/barebox.lds.h>
+#include <asm/barebox.lds.h>
#include <asm-generic/memory_layout.h>
#include <linux/sizes.h>
#define BASE (TEXT_BASE - SZ_2M)
-OUTPUT_ARCH("mips")
+OUTPUT_ARCH(BAREBOX_OUTPUT_ARCH)
SECTIONS
{
. = BASE;
@@ -48,7 +48,8 @@ SECTIONS
.piggydata : {
*(.piggydata)
}
- __piggydata_end = . - BASE;
+
+ .image_end : { KEEP(*(.__image_end)) }
pbl_image_size = .;
diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c
index b084a88be7..a9078aa813 100644
--- a/arch/mips/lib/reloc.c
+++ b/arch/mips/lib/reloc.c
@@ -41,7 +41,7 @@
#include <asm-generic/memory_layout.h>
void main_entry(void *fdt, u32 fdt_size);
-void relocate_code(void *fdt, u32 fdt_size, u32 relocaddr);
+void __noreturn relocate_code(void *fdt, u32 fdt_size, u32 relocaddr);
/**
* read_uint() - Read an unsigned integer from the buffer
@@ -106,10 +106,9 @@ static void apply_reloc(unsigned int type, void *addr, long off)
}
}
-void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
+void __noreturn relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
{
- unsigned long addr, length, bss_len;
- u32 relocaddr, new_stack;
+ unsigned long addr, length, bss_len, relocaddr, new_stack;
uint8_t *buf;
unsigned int type;
long off;
@@ -121,9 +120,9 @@ void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
length = __bss_stop - __image_start;
relocaddr = ALIGN_DOWN(ram_size - length, SZ_64K);
if (IS_ENABLED(CONFIG_MMU)) {
- relocaddr = KSEG0ADDR(relocaddr);
+ relocaddr = CKSEG0ADDR(relocaddr);
} else {
- relocaddr = KSEG1ADDR(relocaddr);
+ relocaddr = CKSEG1ADDR(relocaddr);
}
new_stack = relocaddr - MALLOC_SIZE - 16;
@@ -134,7 +133,7 @@ void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
* space in the Barebox binary & complexity in handling them.
*/
off = relocaddr - (unsigned long)__image_start;
- if (off & 0xffff)
+ if (!IS_ALIGNED(off, SZ_64K))
panic("Mis-aligned relocation\n");
/* Copy Barebox to RAM */
diff --git a/arch/mips/lib/setjmp.S b/arch/mips/lib/setjmp.S
index b09a7c5529..42a2ec15a9 100644
--- a/arch/mips/lib/setjmp.S
+++ b/arch/mips/lib/setjmp.S
@@ -6,34 +6,34 @@
/* int setjmp (jmp_buf); */
LEAF(setjmp)
- sw ra, (0 * 4)(a0)
- sw sp, (1 * 4)(a0)
- sw s0, (2 * 4)(a0)
- sw s1, (3 * 4)(a0)
- sw s2, (4 * 4)(a0)
- sw s3, (5 * 4)(a0)
- sw s4, (6 * 4)(a0)
- sw s5, (7 * 4)(a0)
- sw s6, (8 * 4)(a0)
- sw s7, (9 * 4)(a0)
- sw fp, (10 * 4)(a0)
+ REG_S ra, (0 * SZREG)(a0)
+ REG_S sp, (1 * SZREG)(a0)
+ REG_S s0, (2 * SZREG)(a0)
+ REG_S s1, (3 * SZREG)(a0)
+ REG_S s2, (4 * SZREG)(a0)
+ REG_S s3, (5 * SZREG)(a0)
+ REG_S s4, (6 * SZREG)(a0)
+ REG_S s5, (7 * SZREG)(a0)
+ REG_S s6, (8 * SZREG)(a0)
+ REG_S s7, (9 * SZREG)(a0)
+ REG_S fp, (10 * SZREG)(a0)
move v0, zero
j ra
END(setjmp)
/* volatile void longjmp (jmp_buf, int); */
LEAF(longjmp)
- lw ra, (0 * 4)(a0)
- lw sp, (1 * 4)(a0)
- lw s0, (2 * 4)(a0)
- lw s1, (3 * 4)(a0)
- lw s2, (4 * 4)(a0)
- lw s3, (5 * 4)(a0)
- lw s4, (6 * 4)(a0)
- lw s5, (7 * 4)(a0)
- lw s6, (8 * 4)(a0)
- lw s7, (9 * 4)(a0)
- lw fp, (10 * 4)(a0)
+ REG_L ra, (0 * SZREG)(a0)
+ REG_L sp, (1 * SZREG)(a0)
+ REG_L s0, (2 * SZREG)(a0)
+ REG_L s1, (3 * SZREG)(a0)
+ REG_L s2, (4 * SZREG)(a0)
+ REG_L s3, (5 * SZREG)(a0)
+ REG_L s4, (6 * SZREG)(a0)
+ REG_L s5, (7 * SZREG)(a0)
+ REG_L s6, (8 * SZREG)(a0)
+ REG_L s7, (9 * SZREG)(a0)
+ REG_L fp, (10 * SZREG)(a0)
bne a1, zero, 1f
li a1, 1
1:
@@ -43,8 +43,8 @@ END(longjmp)
/* int initjmp(jmp_buf jmp, void __noreturn (*func)(void), void *stack_top); */
LEAF(initjmp)
- sw a1, (0 * 4)(a0)
- sw a2, (1 * 4)(a0)
+ REG_S a1, (0 * SZREG)(a0)
+ REG_S a2, (1 * SZREG)(a0)
move v0, zero
j ra
END(initjmp)
diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
index ff0a54af8e..638a511fee 100644
--- a/arch/mips/lib/traps.c
+++ b/arch/mips/lib/traps.c
@@ -153,7 +153,8 @@ static void show_regs(const struct pt_regs *regs)
printf("Status: %08x\n", (uint32_t)regs->cp0_status);
printf("Cause : %08x\n", (uint32_t)regs->cp0_cause);
- printf("Config: %08x\n\n", read_c0_config());
+ printf("Config: %08x\n", read_c0_config());
+ printf("BadVA : %0*lx\n\n", field, regs->cp0_badvaddr);
}
void barebox_exc_handler(struct pt_regs *regs)
@@ -173,7 +174,7 @@ void barebox_exc_handler(struct pt_regs *regs)
"move\t$29, %0\n\t"
"j\tret_from_exception"
:/* no outputs */
- :"r" (&regs));
+ :"r" (regs));
/* Unreached */
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-01 12:06:15 +0000