diff options
Diffstat (limited to 'arch/powerpc/mach-mpc85xx/include')
| -rw-r--r-- | arch/powerpc/mach-mpc85xx/include/mach/clock.h | 18 | ||||
| -rw-r--r-- | arch/powerpc/mach-mpc85xx/include/mach/config_mpc85xx.h | 64 | ||||
| -rw-r--r-- | arch/powerpc/mach-mpc85xx/include/mach/early_udelay.h | 36 | ||||
| -rw-r--r-- | arch/powerpc/mach-mpc85xx/include/mach/ffs64.h | 20 | ||||
| -rw-r--r-- | arch/powerpc/mach-mpc85xx/include/mach/fsl_i2c.h | 17 | ||||
| -rw-r--r-- | arch/powerpc/mach-mpc85xx/include/mach/gianfar.h | 30 | ||||
| -rw-r--r-- | arch/powerpc/mach-mpc85xx/include/mach/gpio.h | 15 | ||||
| -rw-r--r-- | arch/powerpc/mach-mpc85xx/include/mach/immap_85xx.h | 202 | ||||
| -rw-r--r-- | arch/powerpc/mach-mpc85xx/include/mach/mmu.h | 52 | ||||
| -rw-r--r-- | arch/powerpc/mach-mpc85xx/include/mach/mpc85xx.h | 23 |
10 files changed, 477 insertions, 0 deletions
diff --git a/arch/powerpc/mach-mpc85xx/include/mach/clock.h b/arch/powerpc/mach-mpc85xx/include/mach/clock.h new file mode 100644 index 0000000000..0e68cf6667 --- /dev/null +++ b/arch/powerpc/mach-mpc85xx/include/mach/clock.h @@ -0,0 +1,18 @@ +#ifndef __ASM_ARCH_CLOCKS_H +#define __ASM_ARCH_CLOCKS_H + +#include <mach/config_mpc85xx.h> + +struct sys_info { + unsigned long freqProcessor[MAX_CPUS]; + unsigned long freqSystemBus; + unsigned long freqDDRBus; + unsigned long freqLocalBus; +}; + +unsigned long fsl_get_bus_freq(ulong dummy); +unsigned long fsl_get_ddr_freq(ulong dummy); +unsigned long fsl_get_timebase_clock(void); +unsigned long fsl_get_i2c_freq(void); +void fsl_get_sys_info(struct sys_info *sysInfo); +#endif /* __ASM_ARCH_CLOCKS_H */ diff --git a/arch/powerpc/mach-mpc85xx/include/mach/config_mpc85xx.h b/arch/powerpc/mach-mpc85xx/include/mach/config_mpc85xx.h new file mode 100644 index 0000000000..fad2c47d11 --- /dev/null +++ b/arch/powerpc/mach-mpc85xx/include/mach/config_mpc85xx.h @@ -0,0 +1,64 @@ +/* + * Copyright 2012 GE Intelligent Platforms, Inc. + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _ASM_MPC85xx_CONFIG_H_ +#define _ASM_MPC85xx_CONFIG_H_ + +#define RESET_VECTOR 0xfffffffc + +/* Number of TLB CAM entries we have on FSL Book-E chips */ +#if defined(CONFIG_E500) +#define NUM_TLBCAMS 16 +#endif + +#if defined(CONFIG_P2020) +#define MAX_CPUS 2 +#define FSL_NUM_LAWS 12 +#define FSL_SEC_COMPAT 2 +#define FSL_NUM_TSEC 3 +#define FSL_ERRATUM_A005125 +#define PPC_E500_DEBUG_TLB 2 + +#elif defined(CONFIG_MPC8544) +#define MAX_CPUS 1 +#define FSL_NUM_LAWS 10 +#define FSL_NUM_TSEC 2 +#define FSL_ERRATUM_A005125 +#define PPC_E500_DEBUG_TLB 0 + +#elif defined(CONFIG_P1022) +#define MAX_CPUS 2 +#define FSL_NUM_LAWS 12 +#define FSL_NUM_TSEC 2 +#define FSL_SEC_COMPAT 2 +#define PPC_E500_DEBUG_TLB 2 +#define FSL_TSECV2 +#define FSL_ERRATUM_A005125 + +#elif defined(CONFIG_P1010) +#define MAX_CPUS 1 +#define FSL_NUM_LAWS 12 +#define FSL_NUM_TSEC 3 +#define FSL_SEC_COMPAT 4 +#define FSL_ERRATUM_A005125 +#define PPC_E500_DEBUG_TLB 2 +#define FSL_TSECV2 + +#else +#error Processor type not defined for this platform +#endif + +#endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/arch/powerpc/mach-mpc85xx/include/mach/early_udelay.h b/arch/powerpc/mach-mpc85xx/include/mach/early_udelay.h new file mode 100644 index 0000000000..b8dc501251 --- /dev/null +++ b/arch/powerpc/mach-mpc85xx/include/mach/early_udelay.h @@ -0,0 +1,36 @@ +/* + * Copyright 2012 GE Intelligent Platforms, Inc. + * + * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> + +/* early_udelay: delay execution before timers are initialized + * + * "usecs * 100" gives a time of around 1 second on a 1Ghz CPU. + */ +static inline void early_udelay(unsigned long usecs) +{ + uint64_t start; + uint32_t loops = usecs * 100; + + start = get_ticks(); + + while ((get_ticks() - start) < loops) + ; +} diff --git a/arch/powerpc/mach-mpc85xx/include/mach/ffs64.h b/arch/powerpc/mach-mpc85xx/include/mach/ffs64.h new file mode 100644 index 0000000000..045498c513 --- /dev/null +++ b/arch/powerpc/mach-mpc85xx/include/mach/ffs64.h @@ -0,0 +1,20 @@ +/* + * Copyright 2013 GE Intelligent Platforms, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <linux/log2.h> + +static inline int ffs64(u64 x) +{ + return __ilog2_u64(x & -x) + 1ull; +} diff --git a/arch/powerpc/mach-mpc85xx/include/mach/fsl_i2c.h b/arch/powerpc/mach-mpc85xx/include/mach/fsl_i2c.h new file mode 100644 index 0000000000..d187c6cf49 --- /dev/null +++ b/arch/powerpc/mach-mpc85xx/include/mach/fsl_i2c.h @@ -0,0 +1,17 @@ +/* + * Copyright 2013 GE Intelligent Platforms, Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +void fsl_i2c_init(void __iomem *i2c, int speed, int slaveadd); +int fsl_i2c_read(void __iomem *i2c, uint8_t dev, uint addr, int alen, + uint8_t *data, int length); +void fsl_i2c_stop(void __iomem *i2c); diff --git a/arch/powerpc/mach-mpc85xx/include/mach/gianfar.h b/arch/powerpc/mach-mpc85xx/include/mach/gianfar.h new file mode 100644 index 0000000000..660cb1e98f --- /dev/null +++ b/arch/powerpc/mach-mpc85xx/include/mach/gianfar.h @@ -0,0 +1,30 @@ +/* + * Copyright 2012 GE Intelligent Platforms, Inc. + * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2003, Motorola, Inc. + * based on tsec.h by Xianghua Xiao and Andy Fleming 2003-2009 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Platform data for the Motorola Triple Speed Ethernet Controller + */ + +#define GFAR_TBIPA_OFFSET 0x030 /* TBI PHY address */ +#define GFAR_TBIPA_END 0x1f /* Last valid PHY address */ + +struct gfar_info_struct { + unsigned int phyaddr; + unsigned int tbiana; + unsigned int tbicr; + unsigned int mdiobus_tbi; +}; + +int fsl_eth_init(int num, struct gfar_info_struct *gf); diff --git a/arch/powerpc/mach-mpc85xx/include/mach/gpio.h b/arch/powerpc/mach-mpc85xx/include/mach/gpio.h new file mode 100644 index 0000000000..b41ecc5214 --- /dev/null +++ b/arch/powerpc/mach-mpc85xx/include/mach/gpio.h @@ -0,0 +1,15 @@ +/* + * Copyright 2013 GE Intelligent Platforms, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef _MACH_PPC_GPIO_H +#define _MACH_PPC_GPIO_H + +extern void fsl_enable_gpiout(void); + +#endif /* _MACH_PPC_GPIO_H */ diff --git a/arch/powerpc/mach-mpc85xx/include/mach/immap_85xx.h b/arch/powerpc/mach-mpc85xx/include/mach/immap_85xx.h new file mode 100644 index 0000000000..abcdb5c1e0 --- /dev/null +++ b/arch/powerpc/mach-mpc85xx/include/mach/immap_85xx.h @@ -0,0 +1,202 @@ +/* + * MPC85xx Internal Memory Map + * + * Copyright 2007-2011 Freescale Semiconductor, Inc. + * + * Copyright(c) 2002,2003 Motorola Inc. + * Xianghua Xiao (x.xiao@motorola.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __IMMAP_85xx__ +#define __IMMAP_85xx__ + +#include <asm/types.h> +#include <asm/fsl_lbc.h> +#include <asm/fsl_ifc.h> +#include <asm/config.h> + +#define MPC85xx_LOCAL_OFFSET 0x0000 +#define MPC85xx_ECM_OFFSET 0x1000 +#define MPC85xx_DDR_OFFSET 0x2000 +#define MPC85xx_LBC_OFFSET 0x5000 +#define MPC85xx_PCI1_OFFSET 0x8000 + +#define MPC85xx_GPIO_OFFSET 0xf000 +#define MPC85xx_IFC_OFFSET 0x1e000 +#define MPC85xx_L2_OFFSET 0x20000 +#ifdef FSL_TSECV2 +#define TSEC1_OFFSET 0xB0000 +#else +#define TSEC1_OFFSET 0x24000 +#endif + +#define MPC85xx_PIC_OFFSET 0x40000 +#define MPC85xx_GUTS_OFFSET 0xe0000 + +#define MPC85xx_LOCAL_ADDR (CFG_IMMR + MPC85xx_LOCAL_OFFSET) +#define MPC85xx_ECM_ADDR (CFG_IMMR + MPC85xx_ECM_OFFSET) +#define MPC85xx_GUTS_ADDR (CFG_IMMR + MPC85xx_GUTS_OFFSET) +#define MPC85xx_DDR_ADDR (CFG_IMMR + MPC85xx_DDR_OFFSET) +#define LBC_ADDR (CFG_IMMR + MPC85xx_LBC_OFFSET) +#define IFC_ADDR (CFG_IMMR + MPC85xx_IFC_OFFSET) +#define MPC85xx_GPIO_ADDR (CFG_IMMR + MPC85xx_GPIO_OFFSET) +#define MPC85xx_L2_ADDR (CFG_IMMR + MPC85xx_L2_OFFSET) +#define MPC8xxx_PIC_ADDR (CFG_IMMR + MPC85xx_PIC_OFFSET) + +/* Local-Access Registers */ +#define MPC85xx_LOCAL_BPTR_OFFSET 0x20 /* Boot Page Translation */ + +/* ECM Registers */ +#define MPC85xx_ECM_EEBPCR_OFFSET 0x00 /* ECM CCB Port Configuration */ +#define MPC85xx_ECM_EEDR_OFFSET 0xE00 /* ECM error detect register */ +#define MPC85xx_ECM_EEER_OFFSET 0xE08 /* ECM error enable register */ + +/* + * DDR Memory Controller Register Offsets + */ +/* Chip Select 0, 1,2, 3 Memory Bounds */ +#define MPC85xx_DDR_CS0_BNDS_OFFSET 0x000 +#define MPC85xx_DDR_CS1_BNDS_OFFSET 0x008 +#define MPC85xx_DDR_CS2_BNDS_OFFSET 0x010 +#define MPC85xx_DDR_CS3_BNDS_OFFSET 0x018 +/* Chip Select 0, 1, 2, 3 Configuration */ +#define MPC85xx_DDR_CS0_CONFIG_OFFSET 0x080 +#define MPC85xx_DDR_CS1_CONFIG_OFFSET 0x084 +#define MPC85xx_DDR_CS2_CONFIG_OFFSET 0x088 +#define MPC85xx_DDR_CS3_CONFIG_OFFSET 0x08c +/* Chip Select 0, 1, 2, 3 Configuration 2 */ +#define MPC85xx_DDR_CS0_CONFIG_2_OFFSET 0x0c0 +#define MPC85xx_DDR_CS1_CONFIG_2_OFFSET 0x0c4 +#define MPC85xx_DDR_CS2_CONFIG_2_OFFSET 0x0c8 +#define MPC85xx_DDR_CS3_CONFIG_2_OFFSET 0x0cc +/* SDRAM Timing Configuration 0, 1, 2, 3 */ +#define MPC85xx_DDR_TIMING_CFG_3_OFFSET 0x100 +#define MPC85xx_DDR_TIMING_CFG_0_OFFSET 0x104 +#define MPC85xx_DDR_TIMING_CFG_1_OFFSET 0x108 +#define MPC85xx_DDR_TIMING_CFG_2_OFFSET 0x10c +/* SDRAM Control Configuration */ +#define MPC85xx_DDR_SDRAM_CFG_OFFSET 0x110 +#define MPC85xx_DDR_SDRAM_CFG_2_OFFSET 0x114 +/* SDRAM Mode Configuration */ +#define MPC85xx_DDR_SDRAM_MODE_OFFSET 0x118 +#define MPC85xx_DDR_SDRAM_MODE_2_OFFSET 0x11c +/* SDRAM Mode Control */ +#define MPC85xx_DDR_SDRAM_MD_CNTL_OFFSET 0x120 +/* SDRAM Interval Configuration */ +#define MPC85xx_DDR_SDRAM_INTERVAL_OFFSET 0x124 +/* SDRAM Data initialization */ +#define MPC85xx_DDR_SDRAM_DATA_INIT_OFFSET 0x128 +/* SDRAM Clock Control */ +#define MPC85xx_DDR_SDRAM_CLK_CNTL_OFFSET 0x130 +/* training init and extended addr */ +#define MPC85xx_DDR_SDRAM_INIT_ADDR_OFFSET 0x148 +#define MPC85xx_DDR_SDRAM_INIT_ADDR_EXT_OFFSET 0x14c +/* SDRAM Timing Configuration 4,5 */ +#define MPC85xx_DDR_TIMING_CFG_4_OFFSET 0x160 +#define MPC85xx_DDR_TIMING_CFG_5_OFFSET 0x164 +/* DDR ZQ calibration control */ +#define MPC85xx_DDR_ZQ_CNTL_OFFSET 0x170 +/* DDR write leveling control */ +#define MPC85xx_DDR_WRLVL_CNTL_OFFSET 0x174 +/* Self Refresh Counter */ +#define MPC85xx_DDR_SR_CNTL_OFFSET 0x17c +/* DDR SDRAM Register Control Word */ +#define MPC85xx_DDR_SDRAM_RCW_1_OFFSET 0x180 +#define MPC85xx_DDR_SDRAM_RCW_2_OFFSET 0x184 +/* DDR write leveling control */ +#define MPC85xx_DDR_WRLVL_CNTL_2_OFFSET 0x190 +#define MPC85xx_DDR_WRLVL_CNTL_3_OFFSET 0x194 +/* DDR Control Driver */ +#define MPC85xx_DDR_DDRCDR1_OFFSET 0xb28 +#define MPC85xx_DDR_DDRCDR2_OFFSET 0xb2c +/* DDR IP block revision */ +#define MPC85xx_DDR_IP_REV1_OFFSET 0xbf8 +#define MPC85xx_DDR_IP_REV2_OFFSET 0xbfc +/* Memory Error Disable */ +#define MPC85xx_DDR_ERR_DISABLE_OFFSET 0xe44 +#define MPC85xx_DDR_ERR_INT_EN_OFFSET 0xe48 + +#define DDR_OFF(REGNAME) (MPC85xx_DDR_##REGNAME##_OFFSET) + +/* + * GPIO Register Offsets + */ +#define MPC85xx_GPIO_GPDIR 0x00 +#define MPC85xx_GPIO_GPDAT 0x08 +#define MPC85xx_GPIO_GPDIR_OFFSET 0x00 +#define MPC85xx_GPIO_GPDAT_OFFSET 0x08 + +/* Global Utilities Registers */ +#define MPC85xx_GPIOCR_OFFSET 0x30 +#define MPC85xx_GPIOCR_GPOUT 0x00000200 +#define MPC85xx_GPOUTDR_OFFSET 0x40 +#define MPC85xx_GPIOBIT(i) (1 << (31 - i)) +#define MPC85xx_GPINDR_OFFSET 0x50 + +#define MPC85xx_DEVDISR_OFFSET 0x70 +#define MPC85xx_DEVDISR_TSEC1 0x00000080 +#define MPC85xx_DEVDISR_TSEC2 0x00000040 +#define MPC85xx_DEVDISR_TSEC3 0x00000020 + +/* + * L2 Cache Register Offsets + */ +#define MPC85xx_L2_CTL_OFFSET 0x0 /* L2 configuration 0 */ +#define MPC85xx_L2CTL_L2E 0x80000000 +#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 +#define MPC85xx_L2_L2SRBAR0_OFFSET 0x100 +#define MPC85xx_L2_L2ERRDIS_OFFSET 0xe44 +#define MPC85xx_L2ERRDIS_MBECC 0x00000008 +#define MPC85xx_L2ERRDIS_SBECC 0x00000004 + +/* PIC registers offsets */ +#define MPC85xx_PIC_WHOAMI_OFFSET 0x090 +#define MPC85xx_PIC_FRR_OFFSET 0x1000 /* Feature Reporting */ +/* PIC registers fields values and masks. */ +#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 +#define MPC8xxx_PICFRR_NCPU_SHIFT 8 +#define MPC85xx_PICGCR_RST 0x80000000 +#define MPC85xx_PICGCR_M 0x20000000 + +#define MPC85xx_PIC_IACK0_OFFSET 0x600a0 /* IRQ Acknowledge for + Processor 0 */ + +/* Global Utilities Register Offsets and field values */ +#define MPC85xx_GUTS_PORPLLSR_OFFSET 0x0 +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 +#define MPC85xx_GUTS_PORDEVSR2_OFFSET 0x14 +#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 +#define MPC85xx_GUTS_PMUXCR_OFFSET 0x60 +#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 +#define MPC85xx_GUTS_PMUXCR2_OFFSET 0x64 +#define MPC85xx_GUTS_DEVDISR_OFFSET 0x70 +#define MPC85xx_DEVDISR_TB0 0x00004000 +#define MPC85xx_DEVDISR_TB1 0x00001000 +#define MPC85xx_GUTS_RSTCR_OFFSET 0xb0 + +#define GFAR_BASE_ADDR (CFG_IMMR + TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CFG_IMMR + 0x24000) + +#define I2C1_BASE_ADDR (CFG_IMMR + 0x3000) +#define I2C2_BASE_ADDR (CFG_IMMR + 0x3100) + +/* Global Timer Registers */ +#define MPC8xxx_PIC_TFRR_OFFSET 0x10F0 + +#define PCI1_BASE_ADDR (CFG_IMMR + MPC85xx_PCI1_OFFSET) +#endif /*__IMMAP_85xx__*/ diff --git a/arch/powerpc/mach-mpc85xx/include/mach/mmu.h b/arch/powerpc/mach-mpc85xx/include/mach/mmu.h new file mode 100644 index 0000000000..e2ecc62ef0 --- /dev/null +++ b/arch/powerpc/mach-mpc85xx/include/mach/mmu.h @@ -0,0 +1,52 @@ +/* + * Copyright 2012 GE Intelligent Platforms, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef _MPC85XX_MMU_H_ +#define _MPC85XX_MMU_H_ + +#ifdef CONFIG_E500 +#include <asm/mmu.h> + +#ifndef __ASSEMBLY__ +extern int e500_find_free_tlbcam(void); +extern void e500_read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, + unsigned long *epn, phys_addr_t *rpn); +extern void e500_read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, + unsigned long *epn, phys_addr_t *rpn); +extern void e500_set_tlb(u8 tlb, u32 epn, u64 rpn, u8 perms, u8 wimge, + u8 ts, u8 esel, u8 tsize, u8 iprot); +extern void e500_disable_tlb(u8 esel); +extern void e500_invalidate_tlb(u8 tlb); +extern void e500_init_tlbs(void); +extern int e500_find_tlb_idx(void *addr, u8 tlbsel); +extern void e500_init_used_tlb_cams(void); + +extern unsigned int e500_setup_ddr_tlbs(unsigned int memsize_in_meg); +extern void e500_write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, + u32 _mas7); + +#define FSL_SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz,\ + _iprot) \ + { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \ + .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \ + .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \ + .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \ + .mas7 = FSL_BOOKE_MAS7(_rpn), } + +struct fsl_e_tlb_entry { + u32 mas0; + u32 mas1; + u32 mas2; + u32 mas3; + u32 mas7; +}; +extern struct fsl_e_tlb_entry tlb_table[]; +extern int num_tlb_entries; +#endif +#endif +#endif /* _MPC85XX_MMU_H_ */ diff --git a/arch/powerpc/mach-mpc85xx/include/mach/mpc85xx.h b/arch/powerpc/mach-mpc85xx/include/mach/mpc85xx.h new file mode 100644 index 0000000000..1d9993ace9 --- /dev/null +++ b/arch/powerpc/mach-mpc85xx/include/mach/mpc85xx.h @@ -0,0 +1,23 @@ +/* + * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright(c) 2003 Motorola Inc. + */ + +#ifndef __MPC85xx_H__ +#define __MPC85xx_H__ + +/* define for common ppc_asm.tmpl */ +#define EXC_OFF_SYS_RESET 0x100 /* System reset */ +#define _START_OFFSET 0 + +#ifndef __ASSEMBLY__ +int fsl_l2_cache_init(void); +int fsl_cpu_numcores(void); + +phys_size_t fsl_get_effective_memsize(void); + +#endif /* __ASSEMBLY__ */ + +#define END_OF_MEM (fsl_get_effective_memsize()) + +#endif /* __MPC85xx_H__ */ |