9 files changed, 41 insertions, 73 deletions

diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 53c759e4ef..63beb80722 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
 obj-y				+= common.o
 obj-$(CONFIG_ARCH_ARMADA_370)	+= armada-370.o corediv.o
 obj-$(CONFIG_ARCH_ARMADA_XP)	+= armada-xp.o corediv.o
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
index 8d02ed93d9..d2ad1ba0cc 100644
--- a/drivers/clk/mvebu/armada-370.c
+++ b/drivers/clk/mvebu/armada-370.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Marvell Armada 370 SoC clocks
  *
@@ -5,10 +6,6 @@
  *
  * Based on Linux Marvell MVEBU clock providers
  *   Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <common.h>
diff --git a/drivers/clk/mvebu/armada-38x.c b/drivers/clk/mvebu/armada-38x.c
index d2d7c2a225..80865965e1 100644
--- a/drivers/clk/mvebu/armada-38x.c
+++ b/drivers/clk/mvebu/armada-38x.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Marvell Armada 380/385 SoC clocks
  *
@@ -6,10 +7,6 @@
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  * Andrew Lunn <andrew@lunn.ch>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <common.h>
@@ -20,7 +17,7 @@
 /*
  * Core Clocks
  *
- * Armada XP Sample At Reset is a 64 bit bitfiled split in two
+ * Armada XP Sample At Reset is a 64 bit bitfield split in two
  * register of 32 bits
  */
 
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
index ffe4f2736d..f0276d32f5 100644
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Marvell Armada XP SoC clocks
  *
@@ -5,10 +6,6 @@
  *
  * Based on Linux Marvell MVEBU clock providers
  *   Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <common.h>
@@ -19,7 +16,7 @@
 /*
  * Core Clocks
  *
- * Armada XP Sample At Reset is a 64 bit bitfiled split in two
+ * Armada XP Sample At Reset is a 64 bit bitfield split in two
  * register of 32 bits
  */
 
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index 609e63697c..4ed2193e58 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Marvell EBU SoC common clock handling
  *
@@ -5,10 +6,6 @@
  *
  * Based on Linux Marvell MVEBU clock providers
  *   Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <common.h>
@@ -41,11 +38,12 @@ static struct of_device_id mvebu_coreclk_ids[] = {
 	  .data = &mv88f6180_coreclks },
 	{ }
 };
+MODULE_DEVICE_TABLE(of, mvebu_coreclk_ids);
 
-static int mvebu_coreclk_probe(struct device_d *dev)
+static int mvebu_coreclk_probe(struct device *dev)
 {
 	struct resource *iores;
-	struct device_node *np = dev->device_node;
+	struct device_node *np = dev->of_node;
 	const struct of_device_id *match;
 	const struct coreclk_soc_desc *desc;
 	const char *tclk_name = "tclk";
@@ -99,17 +97,13 @@ static int mvebu_coreclk_probe(struct device_d *dev)
 	return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 }
 
-static struct driver_d mvebu_coreclk_driver = {
+static struct driver mvebu_coreclk_driver = {
 	.probe	= mvebu_coreclk_probe,
 	.name	= "mvebu-core-clk",
 	.of_compatible = DRV_OF_COMPAT(mvebu_coreclk_ids),
 };
 
-static int mvebu_coreclk_init(void)
-{
-	return platform_driver_register(&mvebu_coreclk_driver);
-}
-core_initcall(mvebu_coreclk_init);
+core_platform_driver(mvebu_coreclk_driver);
 
 /*
  * Clock Gating Control
@@ -154,11 +148,12 @@ static struct of_device_id mvebu_clk_gating_ids[] = {
 	  .data = &kirkwood_gating_desc },
 	{ }
 };
+MODULE_DEVICE_TABLE(of, mvebu_clk_gating_ids);
 
-static int mvebu_clk_gating_probe(struct device_d *dev)
+static int mvebu_clk_gating_probe(struct device *dev)
 {
 	struct resource *iores;
-	struct device_node *np = dev->device_node;
+	struct device_node *np = dev->of_node;
 	const struct of_device_id *match;
 	const struct clk_gating_soc_desc *desc;
 	struct clk_gating_ctrl *ctrl;
@@ -204,14 +199,10 @@ static int mvebu_clk_gating_probe(struct device_d *dev)
 	return of_clk_add_provider(np, clk_gating_get_src, ctrl);
 }
 
-static struct driver_d mvebu_clk_gating_driver = {
+static struct driver mvebu_clk_gating_driver = {
 	.probe	= mvebu_clk_gating_probe,
 	.name	= "mvebu-clk-gating",
 	.of_compatible = DRV_OF_COMPAT(mvebu_clk_gating_ids),
 };
 
-static int mvebu_clk_gating_init(void)
-{
-	return platform_driver_register(&mvebu_clk_gating_driver);
-}
-postcore_initcall(mvebu_clk_gating_init);
+postcore_platform_driver(mvebu_clk_gating_driver);
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
index a3b27247f7..8256d9c2f0 100644
--- a/drivers/clk/mvebu/common.h
+++ b/drivers/clk/mvebu/common.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Marvell EBU SoC common clock handling
  *
@@ -5,10 +6,6 @@
  *
  * Based on Linux Marvell MVEBU clock providers
  *   Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __CLK_MVEBU_COMMON_H_
diff --git a/drivers/clk/mvebu/corediv.c b/drivers/clk/mvebu/corediv.c
index 87b1f8bd7c..7ca53faca4 100644
--- a/drivers/clk/mvebu/corediv.c
+++ b/drivers/clk/mvebu/corediv.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * MVEBU Core divider clock
  *
@@ -6,10 +7,6 @@
  * Based on Linux driver
  *   Copyright (C) 2013 Marvell
  *   Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <common.h>
@@ -54,7 +51,7 @@ struct clk_corediv_soc_desc {
  * existing in the current SoC.
  */
 struct clk_corediv {
-	struct clk clk;
+	struct clk_hw hw;
 	void __iomem *reg;
 	const struct clk_corediv_desc *desc;
 	const struct clk_corediv_soc_desc *soc_desc;
@@ -73,11 +70,11 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = {
 
 #define CORE_CLK_DIV_RATIO_MASK	0xff
 
-#define to_corediv_clk(p) container_of(p, struct clk_corediv, clk)
+#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
 
-static int clk_corediv_is_enabled(struct clk *clk)
+static int clk_corediv_is_enabled(struct clk_hw *hw)
 {
-	struct clk_corediv *corediv = to_corediv_clk(clk);
+	struct clk_corediv *corediv = to_corediv_clk(hw);
 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
 	const struct clk_corediv_desc *desc = corediv->desc;
 	u32 enable_mask = BIT(desc->fieldbit) << soc_desc->enable_bit_offset;
@@ -85,9 +82,9 @@ static int clk_corediv_is_enabled(struct clk *clk)
 	return !!(readl(corediv->reg) & enable_mask);
 }
 
-static int clk_corediv_enable(struct clk *clk)
+static int clk_corediv_enable(struct clk_hw *hw)
 {
-	struct clk_corediv *corediv = to_corediv_clk(clk);
+	struct clk_corediv *corediv = to_corediv_clk(hw);
 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
 	const struct clk_corediv_desc *desc = corediv->desc;
 	u32 reg;
@@ -99,9 +96,9 @@ static int clk_corediv_enable(struct clk *clk)
 	return 0;
 }
 
-static void clk_corediv_disable(struct clk *clk)
+static void clk_corediv_disable(struct clk_hw *hw)
 {
-	struct clk_corediv *corediv = to_corediv_clk(clk);
+	struct clk_corediv *corediv = to_corediv_clk(hw);
 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
 	const struct clk_corediv_desc *desc = corediv->desc;
 	u32 reg;
@@ -111,10 +108,10 @@ static void clk_corediv_disable(struct clk *clk)
 	writel(reg, corediv->reg);
 }
 
-static unsigned long clk_corediv_recalc_rate(struct clk *clk,
+static unsigned long clk_corediv_recalc_rate(struct clk_hw *hw,
 					     unsigned long parent_rate)
 {
-	struct clk_corediv *corediv = to_corediv_clk(clk);
+	struct clk_corediv *corediv = to_corediv_clk(hw);
 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
 	const struct clk_corediv_desc *desc = corediv->desc;
 	u32 reg, div;
@@ -124,7 +121,7 @@ static unsigned long clk_corediv_recalc_rate(struct clk *clk,
 	return parent_rate / div;
 }
 
-static long clk_corediv_round_rate(struct clk *clk, unsigned long rate,
+static long clk_corediv_round_rate(struct clk_hw *hw, unsigned long rate,
 				   unsigned long *parent_rate)
 {
 	/* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */
@@ -139,10 +136,10 @@ static long clk_corediv_round_rate(struct clk *clk, unsigned long rate,
 	return *parent_rate / div;
 }
 
-static int clk_corediv_set_rate(struct clk *clk, unsigned long rate,
+static int clk_corediv_set_rate(struct clk_hw *hw, unsigned long rate,
 				unsigned long parent_rate)
 {
-	struct clk_corediv *corediv = to_corediv_clk(clk);
+	struct clk_corediv *corediv = to_corediv_clk(hw);
 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
 	const struct clk_corediv_desc *desc = corediv->desc;
 	u32 reg, div;
@@ -196,11 +193,12 @@ static struct of_device_id mvebu_corediv_clk_ids[] = {
 	  .data = &armada370_corediv_soc },
 	{ }
 };
+MODULE_DEVICE_TABLE(of, mvebu_corediv_clk_ids);
 
-static int mvebu_corediv_clk_probe(struct device_d *dev)
+static int mvebu_corediv_clk_probe(struct device *dev)
 {
 	struct resource *iores;
-	struct device_node *np = dev->device_node;
+	struct device_node *np = dev->of_node;
 	const struct of_device_id *match;
 	const struct clk_corediv_soc_desc *soc_desc;
 	struct clk_corediv *corediv;
@@ -228,7 +226,7 @@ static int mvebu_corediv_clk_probe(struct device_d *dev)
 
 	for (n = 0; n < clk_data.clk_num; n++) {
 		const char *clk_name;
-		struct clk *clk = &corediv->clk;
+		struct clk *clk = &corediv->hw.clk;
 
 		if (of_property_read_string_index(np,
 				"clock-output-names", n, &clk_name)) {
@@ -245,20 +243,16 @@ static int mvebu_corediv_clk_probe(struct device_d *dev)
 		corediv->desc = &soc_desc->descs[n];
 		corediv->reg = base;
 		clk_data.clks[n] = clk;
-		WARN_ON(IS_ERR_VALUE(clk_register(clk)));
+		WARN_ON(IS_ERR_VALUE(bclk_register(clk)));
 	}
 
 	return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 }
 
-static struct driver_d mvebu_corediv_clk_driver = {
+static struct driver mvebu_corediv_clk_driver = {
 	.probe	= mvebu_corediv_clk_probe,
 	.name	= "mvebu-corediv-clk",
 	.of_compatible = DRV_OF_COMPAT(mvebu_corediv_clk_ids),
 };
 
-static int mvebu_corediv_clk_init(void)
-{
-	return platform_driver_register(&mvebu_corediv_clk_driver);
-}
-postcore_initcall(mvebu_corediv_clk_init);
+postcore_platform_driver(mvebu_corediv_clk_driver);
diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c
index 9bdf89a623..ca9af2671d 100644
--- a/drivers/clk/mvebu/dove.c
+++ b/drivers/clk/mvebu/dove.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Marvell Dove SoC clocks
  *
@@ -5,10 +6,6 @@
  *
  * Based on Linux Marvell MVEBU clock providers
  *   Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <common.h>
diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c
index 5024baf18e..252bf2c69a 100644
--- a/drivers/clk/mvebu/kirkwood.c
+++ b/drivers/clk/mvebu/kirkwood.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Marvell Kirkwood SoC clocks
  *
@@ -5,10 +6,6 @@
  *
  * Based on Linux Marvell MVEBU clock providers
  *   Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <common.h>