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-rw-r--r--drivers/clk/mxs/Makefile1
-rw-r--r--drivers/clk/mxs/clk-div.c44
-rw-r--r--drivers/clk/mxs/clk-frac.c40
-rw-r--r--drivers/clk/mxs/clk-imx23.c27
-rw-r--r--drivers/clk/mxs/clk-imx28.c94
-rw-r--r--drivers/clk/mxs/clk-lcdif.c21
-rw-r--r--drivers/clk/mxs/clk-pll.c40
-rw-r--r--drivers/clk/mxs/clk-ref.c48
-rw-r--r--drivers/clk/mxs/clk.h3
9 files changed, 144 insertions, 174 deletions
diff --git a/drivers/clk/mxs/Makefile b/drivers/clk/mxs/Makefile
index fb4e5dbeea..e1e3e5d70f 100644
--- a/drivers/clk/mxs/Makefile
+++ b/drivers/clk/mxs/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_ARCH_MXS) += clk-ref.o clk-pll.o clk-frac.o clk-div.o
obj-$(CONFIG_DRIVER_VIDEO_STM) += clk-lcdif.o
diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c
index 797e5a274f..17083a051a 100644
--- a/drivers/clk/mxs/clk-div.c
+++ b/drivers/clk/mxs/clk-div.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
@@ -34,40 +28,40 @@ struct clk_div {
u8 busy;
};
-static inline struct clk_div *to_clk_div(struct clk *clk)
+static inline struct clk_div *to_clk_div(struct clk_hw *hw)
{
- struct clk_divider *divider = container_of(clk, struct clk_divider, clk);
+ struct clk_divider *divider = to_clk_divider(hw);
return container_of(divider, struct clk_div, divider);
}
-static unsigned long clk_div_recalc_rate(struct clk *clk,
+static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct clk_div *div = to_clk_div(clk);
+ struct clk_div *div = to_clk_div(hw);
- return div->ops->recalc_rate(&div->divider.clk, parent_rate);
+ return div->ops->recalc_rate(&div->divider.hw, parent_rate);
}
-static long clk_div_round_rate(struct clk *clk, unsigned long rate,
+static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
- struct clk_div *div = to_clk_div(clk);
+ struct clk_div *div = to_clk_div(hw);
- return div->ops->round_rate(&div->divider.clk, rate, prate);
+ return div->ops->round_rate(&div->divider.hw, rate, prate);
}
-static int clk_div_set_rate(struct clk *clk, unsigned long rate,
+static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
- struct clk_div *div = to_clk_div(clk);
+ struct clk_div *div = to_clk_div(hw);
int ret;
- ret = div->ops->set_rate(&div->divider.clk, rate, parent_rate);
+ ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
if (ret)
return ret;
- if (clk_is_enabled(clk))
+ if (clk_hw_is_enabled(hw))
while (readl(div->reg) & 1 << div->busy);
return 0;
@@ -88,10 +82,10 @@ struct clk *mxs_clk_div(const char *name, const char *parent_name,
div = xzalloc(sizeof(*div));
div->parent = parent_name;
- div->divider.clk.name = name;
- div->divider.clk.ops = &clk_div_ops;
- div->divider.clk.parent_names = &div->parent;
- div->divider.clk.num_parents = 1;
+ div->divider.hw.clk.name = name;
+ div->divider.hw.clk.ops = &clk_div_ops;
+ div->divider.hw.clk.parent_names = &div->parent;
+ div->divider.hw.clk.num_parents = 1;
div->reg = reg;
div->busy = busy;
@@ -102,9 +96,9 @@ struct clk *mxs_clk_div(const char *name, const char *parent_name,
div->divider.flags = CLK_DIVIDER_ONE_BASED;
div->ops = &clk_divider_ops;
- ret = clk_register(&div->divider.clk);
+ ret = bclk_register(&div->divider.hw.clk);
if (ret)
return ERR_PTR(ret);
- return &div->divider.clk;
+ return &div->divider.hw.clk;
}
diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c
index 7aa85045a4..6fb479dfad 100644
--- a/drivers/clk/mxs/clk-frac.c
+++ b/drivers/clk/mxs/clk-frac.c
@@ -1,19 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <io.h>
-#include <asm-generic/div64.h>
+#include <linux/math64.h>
#include "clk.h"
@@ -29,7 +23,7 @@
* when the divider is adjusted.
*/
struct clk_frac {
- struct clk clk;
+ struct clk_hw hw;
const char *parent;
void __iomem *reg;
u8 shift;
@@ -37,12 +31,12 @@ struct clk_frac {
u8 busy;
};
-#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, clk)
+#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw)
-static unsigned long clk_frac_recalc_rate(struct clk *clk,
+static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct clk_frac *frac = to_clk_frac(clk);
+ struct clk_frac *frac = to_clk_frac(hw);
u32 div;
div = readl(frac->reg) >> frac->shift;
@@ -51,10 +45,10 @@ static unsigned long clk_frac_recalc_rate(struct clk *clk,
return (parent_rate >> frac->width) * div;
}
-static long clk_frac_round_rate(struct clk *clk, unsigned long rate,
+static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
- struct clk_frac *frac = to_clk_frac(clk);
+ struct clk_frac *frac = to_clk_frac(hw);
unsigned long parent_rate = *prate;
u32 div;
u64 tmp;
@@ -73,10 +67,10 @@ static long clk_frac_round_rate(struct clk *clk, unsigned long rate,
return (parent_rate >> frac->width) * div;
}
-static int clk_frac_set_rate(struct clk *clk, unsigned long rate,
+static int clk_frac_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
- struct clk_frac *frac = to_clk_frac(clk);
+ struct clk_frac *frac = to_clk_frac(hw);
u32 div, val;
u64 tmp;
@@ -96,7 +90,7 @@ static int clk_frac_set_rate(struct clk *clk, unsigned long rate,
val |= div << frac->shift;
writel(val, frac->reg);
- if (clk_is_enabled(clk))
+ if (clk_hw_is_enabled(hw))
while (readl(frac->reg) & 1 << frac->busy);
return 0;
@@ -119,18 +113,18 @@ struct clk *mxs_clk_frac(const char *name, const char *parent_name,
return ERR_PTR(-ENOMEM);
frac->parent = parent_name;
- frac->clk.name = name;
- frac->clk.ops = &clk_frac_ops;
- frac->clk.parent_names = &frac->parent;
- frac->clk.num_parents = 1;
+ frac->hw.clk.name = name;
+ frac->hw.clk.ops = &clk_frac_ops;
+ frac->hw.clk.parent_names = &frac->parent;
+ frac->hw.clk.num_parents = 1;
frac->reg = reg;
frac->shift = shift;
frac->width = width;
- ret = clk_register(&frac->clk);
+ ret = bclk_register(&frac->hw.clk);
if (ret)
return ERR_PTR(ret);
- return &frac->clk;
+ return &frac->hw.clk;
}
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index 526efc52be..d931adda38 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -1,18 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <common.h>
@@ -22,7 +10,7 @@
#include <io.h>
#include <linux/clkdev.h>
#include <linux/err.h>
-#include <mach/imx23-regs.h>
+#include <mach/mxs/imx23-regs.h>
#include "clk.h"
@@ -124,7 +112,7 @@ static int __init mx23_clocks_init(void __iomem *regs)
return 0;
}
-static int imx23_ccm_probe(struct device_d *dev)
+static int imx23_ccm_probe(struct device *dev)
{
struct resource *iores;
void __iomem *regs;
@@ -146,15 +134,12 @@ static __maybe_unused struct of_device_id imx23_ccm_dt_ids[] = {
/* sentinel */
}
};
+MODULE_DEVICE_TABLE(of, imx23_ccm_dt_ids);
-static struct driver_d imx23_ccm_driver = {
+static struct driver imx23_ccm_driver = {
.probe = imx23_ccm_probe,
.name = "imx23-clkctrl",
.of_compatible = DRV_OF_COMPAT(imx23_ccm_dt_ids),
};
-static int imx23_ccm_init(void)
-{
- return platform_driver_register(&imx23_ccm_driver);
-}
-postcore_initcall(imx23_ccm_init);
+postcore_platform_driver(imx23_ccm_driver);
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 12bc9dd977..c2faddb6f4 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -1,18 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <common.h>
@@ -22,7 +10,8 @@
#include <io.h>
#include <linux/clkdev.h>
#include <linux/err.h>
-#include <mach/imx28-regs.h>
+#include <mach/mxs/imx28-regs.h>
+#include <of_address.h>
#include "clk.h"
@@ -50,6 +39,9 @@
#define FRAC1 (regs + 0x01c0)
#define CLKSEQ (regs + 0x01d0)
+static void __iomem *digctrl;
+#define DIGCTRL digctrl
+
static const char *sel_cpu[] = { "ref_cpu", "ref_xtal", };
static const char *sel_io0[] = { "ref_io0", "ref_xtal", };
static const char *sel_io1[] = { "ref_io1", "ref_xtal", };
@@ -68,14 +60,17 @@ enum imx28_clk {
emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
- fec_sleep, fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,
- lcdif_comp, clk_max
+ fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,
+ lcdif_comp, fec_sleep, clk_max
};
static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
-static int __init mx28_clocks_init(void __iomem *regs)
+static int __init mx28_clocks_init(struct device *dev, void __iomem *regs)
{
+ struct device_node *dcnp;
+
clks[ref_xtal] = clk_fixed("ref_xtal", 24000000);
clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
@@ -132,6 +127,13 @@ static int __init mx28_clocks_init(void __iomem *regs)
clks[lcdif_comp] = mxs_clk_lcdif("lcdif_comp", clks[ref_pix],
clks[lcdif_div], clks[lcdif]);
+ dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl");
+ if (dcnp) {
+ digctrl = of_iomap(dcnp, 0);
+ clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2);
+ clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16);
+ }
+
clk_set_rate(clks[ref_io0], 480000000);
clk_set_rate(clks[ref_io1], 480000000);
clk_set_parent(clks[ssp0_sel], clks[ref_io0]);
@@ -143,30 +145,37 @@ static int __init mx28_clocks_init(void __iomem *regs)
clk_set_rate(clks[ssp2], 96000000);
clk_set_rate(clks[ssp3], 96000000);
clk_set_parent(clks[lcdif_sel], clks[ref_pix]);
- clk_enable(clks[enet_out]);
-
- clkdev_add_physbase(clks[ssp0], IMX_SSP0_BASE, NULL);
- clkdev_add_physbase(clks[ssp1], IMX_SSP1_BASE, NULL);
- clkdev_add_physbase(clks[ssp2], IMX_SSP2_BASE, NULL);
- clkdev_add_physbase(clks[ssp3], IMX_SSP3_BASE, NULL);
- clkdev_add_physbase(clks[fec], IMX_FEC0_BASE, NULL);
- clkdev_add_physbase(clks[xbus], IMX_DBGUART_BASE, NULL);
- clkdev_add_physbase(clks[hbus], IMX_OCOTP_BASE, NULL);
- clkdev_add_physbase(clks[hbus], MXS_APBH_BASE, NULL);
- clkdev_add_physbase(clks[uart], IMX_UART0_BASE, NULL);
- clkdev_add_physbase(clks[uart], IMX_UART1_BASE, NULL);
- clkdev_add_physbase(clks[uart], IMX_UART2_BASE, NULL);
- clkdev_add_physbase(clks[uart], IMX_UART3_BASE, NULL);
- clkdev_add_physbase(clks[uart], IMX_UART4_BASE, NULL);
- clkdev_add_physbase(clks[gpmi], MXS_GPMI_BASE, NULL);
- clkdev_add_physbase(clks[pwm], IMX_PWM_BASE, NULL);
- if (IS_ENABLED(CONFIG_DRIVER_VIDEO_STM))
- clkdev_add_physbase(clks[lcdif_comp], IMX_FB_BASE, NULL);
+ clk_set_parent(clks[gpmi_sel], clks[ref_gpmi]);
+
+ if (dev->of_node) {
+ clk_data.clks = clks;
+ clk_data.clk_num = clk_max;
+ of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
+ &clk_data);
+ } else {
+ clkdev_add_physbase(clks[ssp0], IMX_SSP0_BASE, NULL);
+ clkdev_add_physbase(clks[ssp1], IMX_SSP1_BASE, NULL);
+ clkdev_add_physbase(clks[ssp2], IMX_SSP2_BASE, NULL);
+ clkdev_add_physbase(clks[ssp3], IMX_SSP3_BASE, NULL);
+ clkdev_add_physbase(clks[fec], IMX_FEC0_BASE, NULL);
+ clkdev_add_physbase(clks[xbus], IMX_DBGUART_BASE, NULL);
+ clkdev_add_physbase(clks[hbus], IMX_OCOTP_BASE, NULL);
+ clkdev_add_physbase(clks[hbus], MXS_APBH_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART0_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART1_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART2_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART3_BASE, NULL);
+ clkdev_add_physbase(clks[uart], IMX_UART4_BASE, NULL);
+ clkdev_add_physbase(clks[gpmi], MXS_GPMI_BASE, NULL);
+ clkdev_add_physbase(clks[pwm], IMX_PWM_BASE, NULL);
+ if (IS_ENABLED(CONFIG_DRIVER_VIDEO_STM))
+ clkdev_add_physbase(clks[lcdif_comp], IMX_FB_BASE, NULL);
+ }
return 0;
}
-static int imx28_ccm_probe(struct device_d *dev)
+static int imx28_ccm_probe(struct device *dev)
{
struct resource *iores;
void __iomem *regs;
@@ -176,7 +185,7 @@ static int imx28_ccm_probe(struct device_d *dev)
return PTR_ERR(iores);
regs = IOMEM(iores->start);
- mx28_clocks_init(regs);
+ mx28_clocks_init(dev, regs);
return 0;
}
@@ -188,15 +197,12 @@ static __maybe_unused struct of_device_id imx28_ccm_dt_ids[] = {
/* sentinel */
}
};
+MODULE_DEVICE_TABLE(of, imx28_ccm_dt_ids);
-static struct driver_d imx28_ccm_driver = {
+static struct driver imx28_ccm_driver = {
.probe = imx28_ccm_probe,
.name = "imx28-clkctrl",
.of_compatible = DRV_OF_COMPAT(imx28_ccm_dt_ids),
};
-static int imx28_ccm_init(void)
-{
- return platform_driver_register(&imx28_ccm_driver);
-}
-postcore_initcall(imx28_ccm_init);
+postcore_platform_driver(imx28_ccm_driver);
diff --git a/drivers/clk/mxs/clk-lcdif.c b/drivers/clk/mxs/clk-lcdif.c
index 86dfe890f9..a395701262 100644
--- a/drivers/clk/mxs/clk-lcdif.c
+++ b/drivers/clk/mxs/clk-lcdif.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
#include <common.h>
#include <io.h>
#include <linux/clk.h>
@@ -6,18 +7,18 @@
#include "clk.h"
struct clk_lcdif {
- struct clk clk;
+ struct clk_hw hw;
struct clk *frac, *div, *gate;
const char *parent;
};
-#define to_clk_lcdif(_hw) container_of(_hw, struct clk_lcdif, clk)
+#define to_clk_lcdif(_hw) container_of(_hw, struct clk_lcdif, hw)
-static int clk_lcdif_set_rate(struct clk *clk, unsigned long rate,
+static int clk_lcdif_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long unused)
{
- struct clk_lcdif *lcdif = to_clk_lcdif(clk);
+ struct clk_lcdif *lcdif = to_clk_lcdif(hw);
unsigned long frac, div, best_div = 1;
int delta, best_delta = 0x7fffffff;
unsigned long frate, rrate, best_frate;
@@ -62,14 +63,14 @@ struct clk *mxs_clk_lcdif(const char *name, struct clk *frac, struct clk *div,
lcdif->frac = frac;
lcdif->div = div;
lcdif->gate = gate;
- lcdif->clk.name = name;
- lcdif->clk.ops = &clk_lcdif_ops;
- lcdif->clk.parent_names = &lcdif->parent;
- lcdif->clk.num_parents = 1;
+ lcdif->hw.clk.name = name;
+ lcdif->hw.clk.ops = &clk_lcdif_ops;
+ lcdif->hw.clk.parent_names = &lcdif->parent;
+ lcdif->hw.clk.num_parents = 1;
- ret = clk_register(&lcdif->clk);
+ ret = bclk_register(&lcdif->hw.clk);
if (ret)
return ERR_PTR(ret);
- return &lcdif->clk;
+ return &lcdif->hw.clk;
}
diff --git a/drivers/clk/mxs/clk-pll.c b/drivers/clk/mxs/clk-pll.c
index 1b1c9b3543..2c55ab7d8b 100644
--- a/drivers/clk/mxs/clk-pll.c
+++ b/drivers/clk/mxs/clk-pll.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
@@ -30,18 +24,18 @@
* and the shift of gate bit is always 31.
*/
struct clk_pll {
- struct clk clk;
+ struct clk_hw hw;
const char *parent;
void __iomem *base;
u8 power;
unsigned long rate;
};
-#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, clk)
+#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
-static int clk_pll_enable(struct clk *clk)
+static int clk_pll_enable(struct clk_hw *hw)
{
- struct clk_pll *pll = to_clk_pll(clk);
+ struct clk_pll *pll = to_clk_pll(hw);
writel(1 << pll->power, pll->base + SET);
@@ -52,18 +46,18 @@ static int clk_pll_enable(struct clk *clk)
return 0;
}
-static void clk_pll_disable(struct clk *clk)
+static void clk_pll_disable(struct clk_hw *hw)
{
- struct clk_pll *pll = to_clk_pll(clk);
+ struct clk_pll *pll = to_clk_pll(hw);
writel(1 << 31, pll->base + SET);
writel(1 << pll->power, pll->base + CLR);
}
-static int clk_pll_is_enabled(struct clk *clk)
+static int clk_pll_is_enabled(struct clk_hw *hw)
{
- struct clk_pll *pll = to_clk_pll(clk);
+ struct clk_pll *pll = to_clk_pll(hw);
u32 val;
val = readl(pll->base);
@@ -74,10 +68,10 @@ static int clk_pll_is_enabled(struct clk *clk)
return 1;
}
-static unsigned long clk_pll_recalc_rate(struct clk *clk,
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct clk_pll *pll = to_clk_pll(clk);
+ struct clk_pll *pll = to_clk_pll(hw);
return pll->rate;
}
@@ -98,18 +92,18 @@ struct clk *mxs_clk_pll(const char *name, const char *parent_name,
pll = xzalloc(sizeof(*pll));
pll->parent = parent_name;
- pll->clk.name = name;
- pll->clk.ops = &clk_pll_ops;
- pll->clk.parent_names = &pll->parent;
- pll->clk.num_parents = 1;
+ pll->hw.clk.name = name;
+ pll->hw.clk.ops = &clk_pll_ops;
+ pll->hw.clk.parent_names = &pll->parent;
+ pll->hw.clk.num_parents = 1;
pll->base = base;
pll->rate = rate;
pll->power = power;
- ret = clk_register(&pll->clk);
+ ret = bclk_register(&pll->hw.clk);
if (ret)
ERR_PTR(ret);
- return &pll->clk;
+ return &pll->hw.clk;
}
diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c
index 8d0be05615..d483c9c6b2 100644
--- a/drivers/clk/mxs/clk-ref.c
+++ b/drivers/clk/mxs/clk-ref.c
@@ -1,19 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <io.h>
-#include <asm-generic/div64.h>
+#include <linux/math64.h>
#include "clk.h"
@@ -29,20 +23,20 @@
* as pll rate * (18 / FRAC), where FRAC = 18 ~ 35.
*/
struct clk_ref {
- struct clk clk;
+ struct clk_hw hw;
const char *parent;
void __iomem *reg;
u8 idx;
};
-#define to_clk_ref(_hw) container_of(_hw, struct clk_ref, clk)
+#define to_clk_ref(_hw) container_of(_hw, struct clk_ref, hw)
#define SET 0x4
#define CLR 0x8
-static int clk_ref_is_enabled(struct clk *clk)
+static int clk_ref_is_enabled(struct clk_hw *hw)
{
- struct clk_ref *ref = to_clk_ref(clk);
+ struct clk_ref *ref = to_clk_ref(hw);
u32 reg = readl(ref->reg);
if (reg & 1 << ((ref->idx + 1) * 8 - 1))
@@ -51,26 +45,26 @@ static int clk_ref_is_enabled(struct clk *clk)
return 1;
}
-static int clk_ref_enable(struct clk *clk)
+static int clk_ref_enable(struct clk_hw *hw)
{
- struct clk_ref *ref = to_clk_ref(clk);
+ struct clk_ref *ref = to_clk_ref(hw);
writel(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR);
return 0;
}
-static void clk_ref_disable(struct clk *clk)
+static void clk_ref_disable(struct clk_hw *hw)
{
- struct clk_ref *ref = to_clk_ref(clk);
+ struct clk_ref *ref = to_clk_ref(hw);
writel(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET);
}
-static unsigned long clk_ref_recalc_rate(struct clk *clk,
+static unsigned long clk_ref_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct clk_ref *ref = to_clk_ref(clk);
+ struct clk_ref *ref = to_clk_ref(hw);
u64 tmp = parent_rate;
u8 frac = (readl(ref->reg) >> (ref->idx * 8)) & 0x3f;
@@ -80,7 +74,7 @@ static unsigned long clk_ref_recalc_rate(struct clk *clk,
return tmp;
}
-static long clk_ref_round_rate(struct clk *clk, unsigned long rate,
+static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
unsigned long parent_rate = *prate;
@@ -103,10 +97,10 @@ static long clk_ref_round_rate(struct clk *clk, unsigned long rate,
return tmp;
}
-static int clk_ref_set_rate(struct clk *clk, unsigned long rate,
+static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
- struct clk_ref *ref = to_clk_ref(clk);
+ struct clk_ref *ref = to_clk_ref(hw);
u64 tmp = parent_rate;
u32 val;
u32 frac, shift = ref->idx * 8;
@@ -146,17 +140,17 @@ struct clk *mxs_clk_ref(const char *name, const char *parent_name,
ref = xzalloc(sizeof(*ref));
ref->parent = parent_name;
- ref->clk.name = name;
- ref->clk.ops = &clk_ref_ops;
- ref->clk.parent_names = &ref->parent;
- ref->clk.num_parents = 1;
+ ref->hw.clk.name = name;
+ ref->hw.clk.ops = &clk_ref_ops;
+ ref->hw.clk.parent_names = &ref->parent;
+ ref->hw.clk.num_parents = 1;
ref->reg = reg;
ref->idx = idx;
- ret = clk_register(&ref->clk);
+ ret = bclk_register(&ref->hw.clk);
if (ret)
return ERR_PTR(ret);
- return &ref->clk;
+ return &ref->hw.clk;
}
diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h
index 00895de507..a93361a9ea 100644
--- a/drivers/clk/mxs/clk.h
+++ b/drivers/clk/mxs/clk.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __MXS_CLK_H
#define __MXS_CLK_H
@@ -34,7 +35,7 @@ static inline struct clk *mxs_clk_fixed(const char *name, int rate)
static inline struct clk *mxs_clk_gate(const char *name,
const char *parent_name, void __iomem *reg, u8 shift)
{
- return clk_gate_inverted(name, parent_name, reg, shift, 0);
+ return clk_gate_inverted(name, parent_name, reg, shift, CLK_SET_RATE_PARENT);
}
static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 16:13:02 +0000