diff options
Diffstat (limited to 'drivers/ddr')
29 files changed, 1718 insertions, 2017 deletions
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index d92c272b58..0b0d7a8893 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -1,2 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only source "drivers/ddr/fsl/Kconfig" -source "drivers/ddr/imx8m/Kconfig" +source "drivers/ddr/imx/Kconfig" diff --git a/drivers/ddr/Makefile b/drivers/ddr/Makefile index 7e33182cbc..e5d7bd14db 100644 --- a/drivers/ddr/Makefile +++ b/drivers/ddr/Makefile @@ -1,2 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_DDR_FSL) += fsl/ -obj-$(CONFIG_IMX8M_DRAM) += imx8m/ +obj-$(CONFIG_IMX_DRAM) += imx/ diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 9cae9028a2..48f553b0c4 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -1,5 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only config DDR_FSL - bool + bool "Freescale DDR support" + depends on ARCH_LAYERSCAPE if DDR_FSL diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile index 86ac4b820a..787b4453f3 100644 --- a/drivers/ddr/fsl/Makefile +++ b/drivers/ddr/fsl/Makefile @@ -1,12 +1,8 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: GPL-2.0-only # # Copyright 2008-2014 Freescale Semiconductor, Inc. pbl-y += main.o util.o ctrl_regs.o options.o lc_common_dimm_params.o -pbl-y += ddr1_dimm_params.o -pbl-y += ddr2_dimm_params.o -pbl-y += ddr3_dimm_params.o -pbl-y += ddr4_dimm_params.o obj-y += arm_ddr_gen3.o pbl-y += fsl_ddr_gen4.o diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index c016917a3f..1cbdb1446f 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2013 Freescale Semiconductor, Inc. * @@ -21,7 +21,7 @@ * Dividing the initialization to two steps to deassert DDR reset signal * to comply with JEDEC specs for RDIMMs. */ -void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step) +void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step, bool little_endian) { struct ccsr_ddr __iomem *ddr = c->base; const fsl_ddr_cfg_regs_t *regs = &c->fsl_ddr_config_reg; @@ -30,6 +30,11 @@ void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step) u32 total_gb_size_per_controller; int timeout; + if (little_endian) + ddr_endianess = DDR_ENDIANESS_LE; + else + ddr_endianess = DDR_ENDIANESS_BE; + if (step == 2) goto step2; diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 4957320d60..7c882946b9 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2008-2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP Semiconductor @@ -284,7 +284,7 @@ static void set_timing_cfg_0(struct fsl_ddr_controller *c) /* * for single quad-rank DIMM and two-slot DIMMs * to avoid ODT overlap - */ + */ switch (avoid_odt_overlap(c, dimm_params)) { case 2: twrt_mclk = 2; @@ -1111,7 +1111,7 @@ static void set_ddr_sdram_mode_9(struct fsl_ddr_controller *c, unsigned short esdmode5; /* Extended SDRAM mode 5 */ int rtt_park = 0; bool four_cs = false; - const unsigned int mclk_ps = get_memory_clk_period_ps(0); + const unsigned int mclk_ps = get_memory_clk_period_ps(c); if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) && diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c deleted file mode 100644 index 268bf5bde4..0000000000 --- a/drivers/ddr/fsl/ddr1_dimm_params.c +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ -#include <common.h> -#include <soc/fsl/fsl_ddr_sdram.h> -#include <linux/log2.h> -#include "fsl_ddr.h" - -/* - * Calculate the Density of each Physical Rank. - * Returned size is in bytes. - * - * Study these table from Byte 31 of JEDEC SPD Spec. - * - * DDR I DDR II - * Bit Size Size - * --- ----- ------ - * 7 high 512MB 512MB - * 6 256MB 256MB - * 5 128MB 128MB - * 4 64MB 16GB - * 3 32MB 8GB - * 2 16MB 4GB - * 1 2GB 2GB - * 0 low 1GB 1GB - * - * Reorder Table to be linear by stripping the bottom - * 2 or 5 bits off and shifting them up to the top. - */ - -static unsigned long long -compute_ranksize(unsigned int mem_type, unsigned char row_dens) -{ - unsigned long long bsize; - - /* Bottom 2 bits up to the top. */ - bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)); - bsize <<= 24ULL; - debug("DDR: DDR I rank density = 0x%16llx\n", bsize); - - return bsize; -} - -/* - * Convert a two-nibble BCD value into a cycle time. - * While the spec calls for nano-seconds, picos are returned. - * - * This implements the tables for bytes 9, 23 and 25 for both - * DDR I and II. No allowance for distinguishing the invalid - * fields absent for DDR I yet present in DDR II is made. - * (That is, cycle times of .25, .33, .66 and .75 ns are - * allowed for both DDR II and I.) - */ -static unsigned int -convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) -{ - /* Table look up the lower nibble, allow DDR I & II. */ - unsigned int tenths_ps[16] = { - 0, - 100, - 200, - 300, - 400, - 500, - 600, - 700, - 800, - 900, - 250, /* This and the next 3 entries valid ... */ - 330, /* ... only for tCK calculations. */ - 660, - 750, - 0, /* undefined */ - 0 /* undefined */ - }; - - unsigned int whole_ns = (spd_val & 0xF0) >> 4; - unsigned int tenth_ns = spd_val & 0x0F; - unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; - - return ps; -} - -static unsigned int -convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val) -{ - unsigned int tenth_ns = (spd_val & 0xF0) >> 4; - unsigned int hundredth_ns = spd_val & 0x0F; - unsigned int ps = tenth_ns * 100 + hundredth_ns * 10; - - return ps; -} - -static unsigned int byte40_table_ps[8] = { - 0, - 250, - 330, - 500, - 660, - 750, - 0, /* supposed to be RFC, but not sure what that means */ - 0 /* Undefined */ -}; - -static unsigned int -compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc) -{ - return ((trctrfc_ext & 0x1) * 256 + trfc) * 1000 - + byte40_table_ps[(trctrfc_ext >> 1) & 0x7]; -} - -static unsigned int -compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc) -{ - return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7]; -} - -/* - * tCKmax from DDR I SPD Byte 43 - * - * Bits 7:2 == whole ns - * Bits 1:0 == quarter ns - * 00 == 0.00 ns - * 01 == 0.25 ns - * 10 == 0.50 ns - * 11 == 0.75 ns - * - * Returns picoseconds. - */ -static unsigned int -compute_tckmax_from_spd_ps(unsigned int byte43) -{ - return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250; -} - -/* - * Determine Refresh Rate. Ignore self refresh bit on DDR I. - * Table from SPD Spec, Byte 12, converted to picoseconds and - * filled in with "default" normal values. - */ -static unsigned int -determine_refresh_rate_ps(const unsigned int spd_refresh) -{ - unsigned int refresh_time_ps[8] = { - 15625000, /* 0 Normal 1.00x */ - 3900000, /* 1 Reduced .25x */ - 7800000, /* 2 Extended .50x */ - 31300000, /* 3 Extended 2.00x */ - 62500000, /* 4 Extended 4.00x */ - 125000000, /* 5 Extended 8.00x */ - 15625000, /* 6 Normal 1.00x filler */ - 15625000, /* 7 Normal 1.00x filler */ - }; - - return refresh_time_ps[spd_refresh & 0x7]; -} - -/* - * The purpose of this function is to compute a suitable - * CAS latency given the DRAM clock period. The SPD only - * defines at most 3 CAS latencies. Typically the slower in - * frequency the DIMM runs at, the shorter its CAS latency can be. - * If the DIMM is operating at a sufficiently low frequency, - * it may be able to run at a CAS latency shorter than the - * shortest SPD-defined CAS latency. - * - * If a CAS latency is not found, 0 is returned. - * - * Do this by finding in the standard speed bin table the longest - * tCKmin that doesn't exceed the value of mclk_ps (tCK). - * - * An assumption made is that the SDRAM device allows the - * CL to be programmed for a value that is lower than those - * advertised by the SPD. This is not always the case, - * as those modes not defined in the SPD are optional. - * - * CAS latency de-rating based upon values JEDEC Standard No. 79-E - * Table 11. - * - * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2 - */ - /* CL2.0 CL2.5 CL3.0 */ -unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 }; - -static unsigned int -compute_derated_DDR1_CAS_latency(unsigned int mclk_ps) -{ - const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins); - unsigned int lowest_tCKmin_found = 0; - unsigned int lowest_tCKmin_CL = 0; - unsigned int i; - - debug("mclk_ps = %u\n", mclk_ps); - - for (i = 0; i < num_speed_bins; i++) { - unsigned int x = ddr1_speed_bins[i]; - debug("i=%u, x = %u, lowest_tCKmin_found = %u\n", - i, x, lowest_tCKmin_found); - if (x && lowest_tCKmin_found <= x && x <= mclk_ps) { - lowest_tCKmin_found = x; - lowest_tCKmin_CL = i + 1; - } - } - - debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL); - - return lowest_tCKmin_CL; -} - -/* - * ddr1_compute_dimm_parameters for DDR1 SPD - * - * Compute DIMM parameters based upon the SPD information in spd. - * Writes the results to the struct dimm_params structure pointed by pdimm. - * - * FIXME: use #define for the retvals - */ -unsigned int ddr1_compute_dimm_parameters(struct fsl_ddr_controller *c, - const struct ddr1_spd_eeprom *spd, - struct dimm_params *pdimm) -{ - int ret; - - ret = ddr1_spd_check(spd); - if (ret) { - printf("DIMM: failed checksum\n"); - return 2; - } - - /* - * The part name in ASCII in the SPD EEPROM is not null terminated. - * Guarantee null termination here by presetting all bytes to 0 - * and copying the part name in ASCII from the SPD onto it - */ - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); - - /* DIMM organization parameters */ - pdimm->n_ranks = spd->nrows; - pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens); - pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; - pdimm->data_width = spd->dataw_lsb; - pdimm->primary_sdram_width = spd->primw; - pdimm->ec_sdram_width = spd->ecw; - - /* - * FIXME: Need to determine registered_dimm status. - * 1 == register buffered - * 0 == unbuffered - */ - pdimm->registered_dimm = 0; /* unbuffered */ - - /* SDRAM device parameters */ - pdimm->n_row_addr = spd->nrow_addr; - pdimm->n_col_addr = spd->ncol_addr; - pdimm->n_banks_per_sdram_device = spd->nbanks; - pdimm->edc_config = spd->config; - pdimm->burst_lengths_bitmask = spd->burstl; - - /* - * Calculate the Maximum Data Rate based on the Minimum Cycle time. - * The SPD clk_cycle field (tCKmin) is measured in tenths of - * nanoseconds and represented as BCD. - */ - pdimm->tckmin_x_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); - pdimm->tckmin_x_minus_1_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); - pdimm->tckmin_x_minus_2_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); - - pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax); - - /* - * Compute CAS latencies defined by SPD - * The SPD caslat_x should have at least 1 and at most 3 bits set. - * - * If cas_lat after masking is 0, the __ilog2 function returns - * 255 into the variable. This behavior is abused once. - */ - pdimm->caslat_x = ilog2(spd->cas_lat); - pdimm->caslat_x_minus_1 = ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x)); - pdimm->caslat_x_minus_2 = ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x) - & ~(1 << pdimm->caslat_x_minus_1)); - - /* Compute CAS latencies below that defined by SPD */ - pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency( - get_memory_clk_period_ps(c)); - - /* Compute timing parameters */ - pdimm->trcd_ps = spd->trcd * 250; - pdimm->trp_ps = spd->trp * 250; - pdimm->tras_ps = spd->tras * 1000; - - pdimm->twr_ps = mclk_to_picos(c, 3); - pdimm->twtr_ps = mclk_to_picos(c, 1); - pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc); - - pdimm->trrd_ps = spd->trrd * 250; - pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc); - - pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); - - pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); - pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); - pdimm->tds_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); - pdimm->tdh_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - - pdimm->trtp_ps = mclk_to_picos(c, 2); /* By the book. */ - pdimm->tdqsq_max_ps = spd->tdqsq * 10; - pdimm->tqhs_ps = spd->tqhs * 10; - - return 0; -} diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c deleted file mode 100644 index 3f8b56330d..0000000000 --- a/drivers/ddr/fsl/ddr2_dimm_params.c +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <soc/fsl/fsl_ddr_sdram.h> -#include <linux/log2.h> -#include "fsl_ddr.h" - -/* - * Calculate the Density of each Physical Rank. - * Returned size is in bytes. - * - * Study these table from Byte 31 of JEDEC SPD Spec. - * - * DDR I DDR II - * Bit Size Size - * --- ----- ------ - * 7 high 512MB 512MB - * 6 256MB 256MB - * 5 128MB 128MB - * 4 64MB 16GB - * 3 32MB 8GB - * 2 16MB 4GB - * 1 2GB 2GB - * 0 low 1GB 1GB - * - * Reorder Table to be linear by stripping the bottom - * 2 or 5 bits off and shifting them up to the top. - * - */ -static unsigned long long -compute_ranksize(unsigned int mem_type, unsigned char row_dens) -{ - unsigned long long bsize; - - /* Bottom 5 bits up to the top. */ - bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)); - bsize <<= 27ULL; - debug("DDR: DDR II rank density = 0x%16llx\n", bsize); - - return bsize; -} - -/* - * Convert a two-nibble BCD value into a cycle time. - * While the spec calls for nano-seconds, picos are returned. - * - * This implements the tables for bytes 9, 23 and 25 for both - * DDR I and II. No allowance for distinguishing the invalid - * fields absent for DDR I yet present in DDR II is made. - * (That is, cycle times of .25, .33, .66 and .75 ns are - * allowed for both DDR II and I.) - */ -static unsigned int -convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) -{ - /* Table look up the lower nibble, allow DDR I & II. */ - unsigned int tenths_ps[16] = { - 0, - 100, - 200, - 300, - 400, - 500, - 600, - 700, - 800, - 900, - 250, /* This and the next 3 entries valid ... */ - 330, /* ... only for tCK calculations. */ - 660, - 750, - 0, /* undefined */ - 0 /* undefined */ - }; - - unsigned int whole_ns = (spd_val & 0xF0) >> 4; - unsigned int tenth_ns = spd_val & 0x0F; - unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; - - return ps; -} - -static unsigned int -convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val) -{ - unsigned int tenth_ns = (spd_val & 0xF0) >> 4; - unsigned int hundredth_ns = spd_val & 0x0F; - unsigned int ps = tenth_ns * 100 + hundredth_ns * 10; - - return ps; -} - -static unsigned int byte40_table_ps[8] = { - 0, - 250, - 330, - 500, - 660, - 750, - 0, /* supposed to be RFC, but not sure what that means */ - 0 /* Undefined */ -}; - -static unsigned int -compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc) -{ - return (((trctrfc_ext & 0x1) * 256) + trfc) * 1000 - + byte40_table_ps[(trctrfc_ext >> 1) & 0x7]; -} - -static unsigned int -compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc) -{ - return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7]; -} - -/* - * Determine Refresh Rate. Ignore self refresh bit on DDR I. - * Table from SPD Spec, Byte 12, converted to picoseconds and - * filled in with "default" normal values. - */ -static unsigned int -determine_refresh_rate_ps(const unsigned int spd_refresh) -{ - unsigned int refresh_time_ps[8] = { - 15625000, /* 0 Normal 1.00x */ - 3900000, /* 1 Reduced .25x */ - 7800000, /* 2 Extended .50x */ - 31300000, /* 3 Extended 2.00x */ - 62500000, /* 4 Extended 4.00x */ - 125000000, /* 5 Extended 8.00x */ - 15625000, /* 6 Normal 1.00x filler */ - 15625000, /* 7 Normal 1.00x filler */ - }; - - return refresh_time_ps[spd_refresh & 0x7]; -} - -/* - * The purpose of this function is to compute a suitable - * CAS latency given the DRAM clock period. The SPD only - * defines at most 3 CAS latencies. Typically the slower in - * frequency the DIMM runs at, the shorter its CAS latency can. - * be. If the DIMM is operating at a sufficiently low frequency, - * it may be able to run at a CAS latency shorter than the - * shortest SPD-defined CAS latency. - * - * If a CAS latency is not found, 0 is returned. - * - * Do this by finding in the standard speed bin table the longest - * tCKmin that doesn't exceed the value of mclk_ps (tCK). - * - * An assumption made is that the SDRAM device allows the - * CL to be programmed for a value that is lower than those - * advertised by the SPD. This is not always the case, - * as those modes not defined in the SPD are optional. - * - * CAS latency de-rating based upon values JEDEC Standard No. 79-2C - * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS, - * and tRC for corresponding bin" - * - * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3 - * Not certain if any good value exists for CL=2 - */ - /* CL2 CL3 CL4 CL5 CL6 CL7*/ -unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 }; - -static unsigned int -compute_derated_DDR2_CAS_latency(unsigned int mclk_ps) -{ - const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins); - unsigned int lowest_tCKmin_found = 0; - unsigned int lowest_tCKmin_CL = 0; - unsigned int i; - - debug("mclk_ps = %u\n", mclk_ps); - - for (i = 0; i < num_speed_bins; i++) { - unsigned int x = ddr2_speed_bins[i]; - debug("i=%u, x = %u, lowest_tCKmin_found = %u\n", - i, x, lowest_tCKmin_found); - if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) { - lowest_tCKmin_found = x; - lowest_tCKmin_CL = i + 2; - } - } - - debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL); - - return lowest_tCKmin_CL; -} - -/* - * ddr2_compute_dimm_parameters for DDR2 SPD - * - * Compute DIMM parameters based upon the SPD information in spd. - * Writes the results to the struct dimm_params structure pointed by pdimm. - * - * FIXME: use #define for the retvals - */ -unsigned int ddr2_compute_dimm_parameters(struct fsl_ddr_controller *c, - const struct ddr2_spd_eeprom *spd, - struct dimm_params *pdimm) -{ - int ret; - - ret = ddr2_spd_check(spd); - if (ret) { - printf("DIMM: failed checksum\n"); - return 2; - } - - /* - * The part name in ASCII in the SPD EEPROM is not null terminated. - * Guarantee null termination here by presetting all bytes to 0 - * and copying the part name in ASCII from the SPD onto it - */ - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); - - /* DIMM organization parameters */ - pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1; - pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens); - pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; - pdimm->data_width = spd->dataw; - pdimm->primary_sdram_width = spd->primw; - pdimm->ec_sdram_width = spd->ecw; - - /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ - switch (spd->dimm_type) { - case DDR2_SPD_DIMMTYPE_RDIMM: - case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM: - case DDR2_SPD_DIMMTYPE_MINI_RDIMM: - /* Registered/buffered DIMMs */ - pdimm->registered_dimm = 1; - break; - - case DDR2_SPD_DIMMTYPE_UDIMM: - case DDR2_SPD_DIMMTYPE_SO_DIMM: - case DDR2_SPD_DIMMTYPE_MICRO_DIMM: - case DDR2_SPD_DIMMTYPE_MINI_UDIMM: - /* Unbuffered DIMMs */ - pdimm->registered_dimm = 0; - break; - - case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM: - default: - printf("unknown dimm_type 0x%02X\n", spd->dimm_type); - return 1; - } - - /* SDRAM device parameters */ - pdimm->n_row_addr = spd->nrow_addr; - pdimm->n_col_addr = spd->ncol_addr; - pdimm->n_banks_per_sdram_device = spd->nbanks; - pdimm->edc_config = spd->config; - pdimm->burst_lengths_bitmask = spd->burstl; - - /* - * Calculate the Maximum Data Rate based on the Minimum Cycle time. - * The SPD clk_cycle field (tCKmin) is measured in tenths of - * nanoseconds and represented as BCD. - */ - pdimm->tckmin_x_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); - pdimm->tckmin_x_minus_1_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); - pdimm->tckmin_x_minus_2_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); - - pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax); - - /* - * Compute CAS latencies defined by SPD - * The SPD caslat_x should have at least 1 and at most 3 bits set. - * - * If cas_lat after masking is 0, the __ilog2 function returns - * 255 into the variable. This behavior is abused once. - */ - pdimm->caslat_x = ilog2(spd->cas_lat); - pdimm->caslat_x_minus_1 = ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x)); - pdimm->caslat_x_minus_2 = ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x) - & ~(1 << pdimm->caslat_x_minus_1)); - - /* Compute CAS latencies below that defined by SPD */ - pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency( - get_memory_clk_period_ps(c)); - - /* Compute timing parameters */ - pdimm->trcd_ps = spd->trcd * 250; - pdimm->trp_ps = spd->trp * 250; - pdimm->tras_ps = spd->tras * 1000; - - pdimm->twr_ps = spd->twr * 250; - pdimm->twtr_ps = spd->twtr * 250; - pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc); - - pdimm->trrd_ps = spd->trrd * 250; - pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc); - - pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); - - pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); - pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); - pdimm->tds_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); - pdimm->tdh_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - - pdimm->trtp_ps = spd->trtp * 250; - pdimm->tdqsq_max_ps = spd->tdqsq * 10; - pdimm->tqhs_ps = spd->tqhs * 10; - - return 0; -} diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c deleted file mode 100644 index 1665e792c3..0000000000 --- a/drivers/ddr/fsl/ddr3_dimm_params.c +++ /dev/null @@ -1,325 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - * - * calculate the organization and timing parameter - * from ddr3 spd, please refer to the spec - * JEDEC standard No.21-C 4_01_02_11R18.pdf - */ - -#include <common.h> -#include <soc/fsl/fsl_ddr_sdram.h> -#include "fsl_ddr.h" - -/* - * Calculate the Density of each Physical Rank. - * Returned size is in bytes. - * - * each rank size = - * sdram capacity(bit) / 8 * primary bus width / sdram width - * - * where: sdram capacity = spd byte4[3:0] - * primary bus width = spd byte8[2:0] - * sdram width = spd byte7[2:0] - * - * SPD byte4 - sdram density and banks - * bit[3:0] size(bit) size(byte) - * 0000 256Mb 32MB - * 0001 512Mb 64MB - * 0010 1Gb 128MB - * 0011 2Gb 256MB - * 0100 4Gb 512MB - * 0101 8Gb 1GB - * 0110 16Gb 2GB - * - * SPD byte8 - module memory bus width - * bit[2:0] primary bus width - * 000 8bits - * 001 16bits - * 010 32bits - * 011 64bits - * - * SPD byte7 - module organiztion - * bit[2:0] sdram device width - * 000 4bits - * 001 8bits - * 010 16bits - * 011 32bits - * - */ -static unsigned long long -compute_ranksize(const struct ddr3_spd_eeprom *spd) -{ - unsigned long long bsize; - - int nbit_sdram_cap_bsize = 0; - int nbit_primary_bus_width = 0; - int nbit_sdram_width = 0; - - if ((spd->density_banks & 0xf) < 7) - nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; - if ((spd->bus_width & 0x7) < 4) - nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; - if ((spd->organization & 0x7) < 4) - nbit_sdram_width = (spd->organization & 0x7) + 2; - - bsize = 1ULL << (nbit_sdram_cap_bsize - 3 - + nbit_primary_bus_width - nbit_sdram_width); - - debug("DDR: DDR III rank density = 0x%16llx\n", bsize); - - return bsize; -} - -/* - * ddr3_compute_dimm_parameters for DDR3 SPD - * - * Compute DIMM parameters based upon the SPD information in spd. - * Writes the results to the struct dimm_params structure pointed by pdimm. - * - */ -unsigned int ddr3_compute_dimm_parameters(struct fsl_ddr_controller *c, - const struct ddr3_spd_eeprom *spd, - struct dimm_params *pdimm) -{ - int ret; - unsigned int mtb_ps; - int ftb_10th_ps; - int i; - - ret = ddr3_spd_check(spd); - if (ret) { - printf("DIMM: failed checksum\n"); - return 2; - } - - /* - * The part name in ASCII in the SPD EEPROM is not null terminated. - * Guarantee null termination here by presetting all bytes to 0 - * and copying the part name in ASCII from the SPD onto it - */ - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - if ((spd->info_size_crc & 0xF) > 1) - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); - - /* DIMM organization parameters */ - pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; - pdimm->rank_density = compute_ranksize(spd); - pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; - pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); - if ((spd->bus_width >> 3) & 0x3) - pdimm->ec_sdram_width = 8; - else - pdimm->ec_sdram_width = 0; - pdimm->data_width = pdimm->primary_sdram_width - + pdimm->ec_sdram_width; - pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); - - /* These are the types defined by the JEDEC DDR3 SPD spec */ - pdimm->mirrored_dimm = 0; - pdimm->registered_dimm = 0; - switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { - case DDR3_SPD_MODULETYPE_RDIMM: - case DDR3_SPD_MODULETYPE_MINI_RDIMM: - case DDR3_SPD_MODULETYPE_72B_SO_RDIMM: - /* Registered/buffered DIMMs */ - pdimm->registered_dimm = 1; - for (i = 0; i < 16; i += 2) { - u8 rcw = spd->mod_section.registered.rcw[i/2]; - pdimm->rcw[i] = (rcw >> 0) & 0x0F; - pdimm->rcw[i+1] = (rcw >> 4) & 0x0F; - } - break; - - case DDR3_SPD_MODULETYPE_UDIMM: - case DDR3_SPD_MODULETYPE_SO_DIMM: - case DDR3_SPD_MODULETYPE_MICRO_DIMM: - case DDR3_SPD_MODULETYPE_MINI_UDIMM: - case DDR3_SPD_MODULETYPE_MINI_CDIMM: - case DDR3_SPD_MODULETYPE_72B_SO_UDIMM: - case DDR3_SPD_MODULETYPE_72B_SO_CDIMM: - case DDR3_SPD_MODULETYPE_LRDIMM: - case DDR3_SPD_MODULETYPE_16B_SO_DIMM: - case DDR3_SPD_MODULETYPE_32B_SO_DIMM: - /* Unbuffered DIMMs */ - if (spd->mod_section.unbuffered.addr_mapping & 0x1) - pdimm->mirrored_dimm = 1; - break; - - default: - printf("unknown module_type 0x%02X\n", spd->module_type); - return 1; - } - - /* SDRAM device parameters */ - pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; - pdimm->n_col_addr = (spd->addressing & 0x7) + 9; - pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7); - - /* - * The SPD spec has not the ECC bit, - * We consider the DIMM as ECC capability - * when the extension bus exist - */ - if (pdimm->ec_sdram_width) - pdimm->edc_config = 0x02; - else - pdimm->edc_config = 0x00; - - /* - * The SPD spec has not the burst length byte - * but DDR3 spec has nature BL8 and BC4, - * BL8 -bit3, BC4 -bit2 - */ - pdimm->burst_lengths_bitmask = 0x0c; - - /* MTB - medium timebase - * The unit in the SPD spec is ns, - * We convert it to ps. - * eg: MTB = 0.125ns (125ps) - */ - mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor; - pdimm->mtb_ps = mtb_ps; - - /* - * FTB - fine timebase - * use 1/10th of ps as our unit to avoid floating point - * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps - */ - ftb_10th_ps = - ((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f); - pdimm->ftb_10th_ps = ftb_10th_ps; - /* - * sdram minimum cycle time - * we assume the MTB is 0.125ns - * eg: - * tck_min=15 MTB (1.875ns) ->DDR3-1066 - * =12 MTB (1.5ns) ->DDR3-1333 - * =10 MTB (1.25ns) ->DDR3-1600 - */ - pdimm->tckmin_x_ps = spd->tck_min * mtb_ps + - (spd->fine_tck_min * ftb_10th_ps) / 10; - - /* - * CAS latency supported - * bit4 - CL4 - * bit5 - CL5 - * bit18 - CL18 - */ - pdimm->caslat_x = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4; - - /* - * min CAS latency time - * eg: taa_min = - * DDR3-800D 100 MTB (12.5ns) - * DDR3-1066F 105 MTB (13.125ns) - * DDR3-1333H 108 MTB (13.5ns) - * DDR3-1600H 90 MTB (11.25ns) - */ - pdimm->taa_ps = spd->taa_min * mtb_ps + - (spd->fine_taa_min * ftb_10th_ps) / 10; - - /* - * min write recovery time - * eg: - * twr_min = 120 MTB (15ns) -> all speed grades. - */ - pdimm->twr_ps = spd->twr_min * mtb_ps; - - /* - * min RAS to CAS delay time - * eg: trcd_min = - * DDR3-800 100 MTB (12.5ns) - * DDR3-1066F 105 MTB (13.125ns) - * DDR3-1333H 108 MTB (13.5ns) - * DDR3-1600H 90 MTB (11.25) - */ - pdimm->trcd_ps = spd->trcd_min * mtb_ps + - (spd->fine_trcd_min * ftb_10th_ps) / 10; - - /* - * min row active to row active delay time - * eg: trrd_min = - * DDR3-800(1KB page) 80 MTB (10ns) - * DDR3-1333(1KB page) 48 MTB (6ns) - */ - pdimm->trrd_ps = spd->trrd_min * mtb_ps; - - /* - * min row precharge delay time - * eg: trp_min = - * DDR3-800D 100 MTB (12.5ns) - * DDR3-1066F 105 MTB (13.125ns) - * DDR3-1333H 108 MTB (13.5ns) - * DDR3-1600H 90 MTB (11.25ns) - */ - pdimm->trp_ps = spd->trp_min * mtb_ps + - (spd->fine_trp_min * ftb_10th_ps) / 10; - - /* min active to precharge delay time - * eg: tRAS_min = - * DDR3-800D 300 MTB (37.5ns) - * DDR3-1066F 300 MTB (37.5ns) - * DDR3-1333H 288 MTB (36ns) - * DDR3-1600H 280 MTB (35ns) - */ - pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb) - * mtb_ps; - /* - * min active to actice/refresh delay time - * eg: tRC_min = - * DDR3-800D 400 MTB (50ns) - * DDR3-1066F 405 MTB (50.625ns) - * DDR3-1333H 396 MTB (49.5ns) - * DDR3-1600H 370 MTB (46.25ns) - */ - pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb) - * mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10; - /* - * min refresh recovery delay time - * eg: tRFC_min = - * 512Mb 720 MTB (90ns) - * 1Gb 880 MTB (110ns) - * 2Gb 1280 MTB (160ns) - */ - pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb) - * mtb_ps; - /* - * min internal write to read command delay time - * eg: twtr_min = 40 MTB (7.5ns) - all speed bins. - * tWRT is at least 4 mclk independent of operating freq. - */ - pdimm->twtr_ps = spd->twtr_min * mtb_ps; - - /* - * min internal read to precharge command delay time - * eg: trtp_min = 40 MTB (7.5ns) - all speed bins. - * tRTP is at least 4 mclk independent of operating freq. - */ - pdimm->trtp_ps = spd->trtp_min * mtb_ps; - - /* - * Average periodic refresh interval - * tREFI = 7.8 us at normal temperature range - * = 3.9 us at ext temperature range - */ - pdimm->refresh_rate_ps = 7800000; - if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) { - pdimm->refresh_rate_ps = 3900000; - pdimm->extended_op_srt = 1; - } - - /* - * min four active window delay time - * eg: tfaw_min = - * DDR3-800(1KB page) 320 MTB (40ns) - * DDR3-1066(1KB page) 300 MTB (37.5ns) - * DDR3-1333(1KB page) 240 MTB (30ns) - * DDR3-1600(1KB page) 240 MTB (30ns) - */ - pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) - * mtb_ps; - - return 0; -} diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c deleted file mode 100644 index f39b6e2853..0000000000 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ /dev/null @@ -1,352 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP Semiconductor - * - * calculate the organization and timing parameter - * from ddr3 spd, please refer to the spec - * JEDEC standard No.21-C 4_01_02_12R23A.pdf - * - * - */ - -#include <common.h> -#include <soc/fsl/fsl_ddr_sdram.h> -#include "fsl_ddr.h" - -/* - * Calculate the Density of each Physical Rank. - * Returned size is in bytes. - * - * Total DIMM size = - * sdram capacity(bit) / 8 * primary bus width / sdram width - * * Logical Ranks per DIMM - * - * where: sdram capacity = spd byte4[3:0] - * primary bus width = spd byte13[2:0] - * sdram width = spd byte12[2:0] - * Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP - * spd byte12{5:3] * spd byte6[6:4] for 3DS - * - * To simplify each rank size = total DIMM size / Number of Package Ranks - * where Number of Package Ranks = spd byte12[5:3] - * - * SPD byte4 - sdram density and banks - * bit[3:0] size(bit) size(byte) - * 0000 256Mb 32MB - * 0001 512Mb 64MB - * 0010 1Gb 128MB - * 0011 2Gb 256MB - * 0100 4Gb 512MB - * 0101 8Gb 1GB - * 0110 16Gb 2GB - * 0111 32Gb 4GB - * - * SPD byte13 - module memory bus width - * bit[2:0] primary bus width - * 000 8bits - * 001 16bits - * 010 32bits - * 011 64bits - * - * SPD byte12 - module organization - * bit[2:0] sdram device width - * 000 4bits - * 001 8bits - * 010 16bits - * 011 32bits - * - * SPD byte12 - module organization - * bit[5:3] number of package ranks per DIMM - * 000 1 - * 001 2 - * 010 3 - * 011 4 - * - * SPD byte6 - SDRAM package type - * bit[6:4] Die count - * 000 1 - * 001 2 - * 010 3 - * 011 4 - * 100 5 - * 101 6 - * 110 7 - * 111 8 - * - * SPD byte6 - SRAM package type - * bit[1:0] Signal loading - * 00 Not specified - * 01 Multi load stack - * 10 Sigle load stack (3DS) - * 11 Reserved - */ -static unsigned long long -compute_ranksize(const struct ddr4_spd_eeprom *spd) -{ - unsigned long long bsize; - - int nbit_sdram_cap_bsize = 0; - int nbit_primary_bus_width = 0; - int nbit_sdram_width = 0; - int die_count = 0; - bool package_3ds; - - if ((spd->density_banks & 0xf) <= 7) - nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; - if ((spd->bus_width & 0x7) < 4) - nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; - if ((spd->organization & 0x7) < 4) - nbit_sdram_width = (spd->organization & 0x7) + 2; - package_3ds = (spd->package_type & 0x3) == 0x2; - if ((spd->package_type & 0x80) && !package_3ds) { /* other than 3DS */ - printf("Warning: not supported SDRAM package type\n"); - return 0; - } - if (package_3ds) - die_count = (spd->package_type >> 4) & 0x7; - - bsize = 1ULL << (nbit_sdram_cap_bsize - 3 + - nbit_primary_bus_width - nbit_sdram_width + - die_count); - - debug("DDR: DDR rank density = 0x%16llx\n", bsize); - - return bsize; -} - -#define spd_to_ps(mtb, ftb) \ - (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10) -/* - * ddr4_compute_dimm_parameters for DDR4 SPD - * - * Compute DIMM parameters based upon the SPD information in spd. - * Writes the results to the struct dimm_params structure pointed by pdimm. - * - */ -unsigned int ddr4_compute_dimm_parameters(struct fsl_ddr_controller *c, - const struct ddr4_spd_eeprom *spd, - struct dimm_params *pdimm) -{ - int ret; - int i; - const u8 udimm_rc_e_dq[18] = { - 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15, - 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36 - }; - int spd_error = 0; - u8 *ptr; - u8 val; - - ret = ddr4_spd_check(spd); - if (ret) { - printf("DIMM: failed checksum\n"); - return 2; - } - - /* - * The part name in ASCII in the SPD EEPROM is not null terminated. - * Guarantee null termination here by presetting all bytes to 0 - * and copying the part name in ASCII from the SPD onto it - */ - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - if ((spd->info_size_crc & 0xF) > 2) - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); - - /* DIMM organization parameters */ - pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; - pdimm->rank_density = compute_ranksize(spd); - pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; - pdimm->die_density = spd->density_banks & 0xf; - pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); - if ((spd->bus_width >> 3) & 0x3) - pdimm->ec_sdram_width = 8; - else - pdimm->ec_sdram_width = 0; - pdimm->data_width = pdimm->primary_sdram_width - + pdimm->ec_sdram_width; - pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); - pdimm->package_3ds = (spd->package_type & 0x3) == 0x2 ? - (spd->package_type >> 4) & 0x7 : 0; - - /* These are the types defined by the JEDEC SPD spec */ - pdimm->mirrored_dimm = 0; - pdimm->registered_dimm = 0; - switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) { - case DDR4_SPD_MODULETYPE_RDIMM: - /* Registered/buffered DIMMs */ - pdimm->registered_dimm = 1; - if (spd->mod_section.registered.reg_map & 0x1) - pdimm->mirrored_dimm = 1; - val = spd->mod_section.registered.ca_stren; - pdimm->rcw[3] = val >> 4; - pdimm->rcw[4] = ((val & 0x3) << 2) | ((val & 0xc) >> 2); - val = spd->mod_section.registered.clk_stren; - pdimm->rcw[5] = ((val & 0x3) << 2) | ((val & 0xc) >> 2); - /* Not all in SPD. For convience only. Boards may overwrite. */ - pdimm->rcw[6] = 0xf; - /* - * A17 only used for 16Gb and above devices. - * C[2:0] only used for 3DS. - */ - pdimm->rcw[8] = pdimm->die_density >= 0x6 ? 0x0 : 0x8 | - (pdimm->package_3ds > 0x3 ? 0x0 : - (pdimm->package_3ds > 0x1 ? 0x1 : - (pdimm->package_3ds > 0 ? 0x2 : 0x3))); - if (pdimm->package_3ds || pdimm->n_ranks != 4) - pdimm->rcw[13] = 0xc; - else - pdimm->rcw[13] = 0xd; /* Fix encoded by board */ - - break; - - case DDR4_SPD_MODULETYPE_UDIMM: - case DDR4_SPD_MODULETYPE_SO_DIMM: - /* Unbuffered DIMMs */ - if (spd->mod_section.unbuffered.addr_mapping & 0x1) - pdimm->mirrored_dimm = 1; - if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 && - (spd->mod_section.unbuffered.ref_raw_card == 0x04)) { - /* Fix SPD error found on DIMMs with raw card E0 */ - for (i = 0; i < 18; i++) { - if (spd->mapping[i] == udimm_rc_e_dq[i]) - continue; - spd_error = 1; - debug("SPD byte %d: 0x%x, should be 0x%x\n", - 60 + i, spd->mapping[i], - udimm_rc_e_dq[i]); - ptr = (u8 *)&spd->mapping[i]; - *ptr = udimm_rc_e_dq[i]; - } - if (spd_error) - printf("SPD DQ mapping error fixed\n"); - } - break; - - default: - printf("unknown module_type 0x%02X\n", spd->module_type); - return 1; - } - - /* SDRAM device parameters */ - pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; - pdimm->n_col_addr = (spd->addressing & 0x7) + 9; - pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3; - pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3; - - /* - * The SPD spec has not the ECC bit, - * We consider the DIMM as ECC capability - * when the extension bus exist - */ - if (pdimm->ec_sdram_width) - pdimm->edc_config = 0x02; - else - pdimm->edc_config = 0x00; - - /* - * The SPD spec has not the burst length byte - * but DDR4 spec has nature BL8 and BC4, - * BL8 -bit3, BC4 -bit2 - */ - pdimm->burst_lengths_bitmask = 0x0c; - - /* MTB - medium timebase - * The MTB in the SPD spec is 125ps, - * - * FTB - fine timebase - * use 1/10th of ps as our unit to avoid floating point - * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps - */ - if ((spd->timebases & 0xf) == 0x0) { - pdimm->mtb_ps = 125; - pdimm->ftb_10th_ps = 10; - - } else { - printf("Unknown Timebases\n"); - } - - /* sdram minimum cycle time */ - pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min); - - /* sdram max cycle time */ - pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max); - - /* - * CAS latency supported - * bit0 - CL7 - * bit4 - CL11 - * bit8 - CL15 - * bit12- CL19 - * bit16- CL23 - */ - pdimm->caslat_x = (spd->caslat_b1 << 7) | - (spd->caslat_b2 << 15) | - (spd->caslat_b3 << 23); - - BUG_ON(spd->caslat_b4 != 0); - - /* - * min CAS latency time - */ - pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min); - - /* - * min RAS to CAS delay time - */ - pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min); - - /* - * Min Row Precharge Delay Time - */ - pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min); - - /* min active to precharge delay time */ - pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) + - spd->tras_min_lsb) * pdimm->mtb_ps; - - /* min active to actice/refresh delay time */ - pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) + - spd->trc_min_lsb), spd->fine_trc_min); - /* Min Refresh Recovery Delay Time */ - pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) * - pdimm->mtb_ps; - pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) * - pdimm->mtb_ps; - pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) * - pdimm->mtb_ps; - /* min four active window delay time */ - pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) * - pdimm->mtb_ps; - - /* min row active to row active delay time, different bank group */ - pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min); - /* min row active to row active delay time, same bank group */ - pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min); - /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */ - pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min); - - if (pdimm->package_3ds) { - if (pdimm->die_density <= 0x4) { - pdimm->trfc_slr_ps = 260000; - } else if (pdimm->die_density <= 0x5) { - pdimm->trfc_slr_ps = 350000; - } else { - printf("WARN: Unsupported logical rank density 0x%x\n", - pdimm->die_density); - } - } - - /* - * Average periodic refresh interval - * tREFI = 7.8 us at normal temperature range - */ - pdimm->refresh_rate_ps = 7800000; - - for (i = 0; i < 18; i++) - pdimm->dq_mapping[i] = spd->mapping[i]; - - pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0; - - return 0; -} diff --git a/drivers/ddr/fsl/fsl_ddr.h b/drivers/ddr/fsl/fsl_ddr.h index ab991a5bf4..0c1a30a236 100644 --- a/drivers/ddr/fsl/fsl_ddr.h +++ b/drivers/ddr/fsl/fsl_ddr.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright 2008-2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP Semiconductor @@ -189,7 +189,6 @@ static inline int is_ddr3_4(const memctl_options_t *popts) struct fsl_ddr_info; -phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo); u32 fsl_ddr_get_intl3r(void); void board_mem_sleep_setup(void); @@ -204,18 +203,6 @@ struct fsl_ddr_controller; u32 fsl_ddr_get_version(struct fsl_ddr_controller *c); -unsigned int ddr1_compute_dimm_parameters(struct fsl_ddr_controller *c, - const struct ddr1_spd_eeprom *spd, - struct dimm_params *pdimm); -unsigned int ddr2_compute_dimm_parameters(struct fsl_ddr_controller *c, - const struct ddr2_spd_eeprom *spd, - struct dimm_params *pdimm); -unsigned int ddr3_compute_dimm_parameters(struct fsl_ddr_controller *c, - const struct ddr3_spd_eeprom *spd, - struct dimm_params *pdimm); -unsigned int ddr4_compute_dimm_parameters(struct fsl_ddr_controller *c, - const struct ddr4_spd_eeprom *spd, - struct dimm_params *pdimm); void fsl_ddr_set_intl3r(const unsigned int granule_size); unsigned int compute_fsl_memctl_config_regs(struct fsl_ddr_controller *c); diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index ac68e4ff03..19aa4f22a9 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -36,7 +36,7 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) * Dividing the initialization to two steps to deassert DDR reset signal * to comply with JEDEC specs for RDIMMs. */ -void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step) +void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step, bool little_endian) { struct ccsr_ddr __iomem *ddr = c->base; const fsl_ddr_cfg_regs_t *regs = &c->fsl_ddr_config_reg; @@ -53,6 +53,11 @@ void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step) u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK; + if (little_endian) + ddr_endianess = DDR_ENDIANESS_LE; + else + ddr_endianess = DDR_ENDIANESS_BE; + if (step == 2) goto step2; diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index 2de4cca9cc..0ed6b6e347 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2008-2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP Semiconductor diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index b0df34c933..c8217a86dd 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2008-2014 Freescale Semiconductor, Inc. */ @@ -13,6 +13,8 @@ #include <linux/log2.h> #include "fsl_ddr.h" +enum ddr_endianess ddr_endianess; + /* * ASSUMPTIONS: * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller @@ -95,7 +97,7 @@ static unsigned long long step_assign_addresses_linear(struct fsl_ddr_info *pinf static unsigned long long step_assign_addresses_interleaved(struct fsl_ddr_info *pinfo, unsigned long long current_mem_base) { - unsigned long long total_mem, total_ctlr_mem; + unsigned long long total_mem = 0, total_ctlr_mem; unsigned long long rank_density, ctlr_density = 0; int i; @@ -238,19 +240,20 @@ static int compute_dimm_parameters(struct fsl_ddr_controller *c, struct spd_eeprom *spd, struct dimm_params *pdimm) { + unsigned int mclk_ps = get_memory_clk_period_ps(c); const memctl_options_t *popts = &c->memctl_opts; int ret = -EINVAL; memset(pdimm, 0, sizeof(*pdimm)); if (is_ddr1(popts)) - ret = ddr1_compute_dimm_parameters(c, (void *)spd, pdimm); + ret = ddr1_compute_dimm_parameters(mclk_ps, (void *)spd, pdimm); else if (is_ddr2(popts)) - ret = ddr2_compute_dimm_parameters(c, (void *)spd, pdimm); + ret = ddr2_compute_dimm_parameters(mclk_ps, (void *)spd, pdimm); else if (is_ddr3(popts)) - ret = ddr3_compute_dimm_parameters(c, (void *)spd, pdimm); + ret = ddr3_compute_dimm_parameters((void *)spd, pdimm); else if (is_ddr4(popts)) - ret = ddr4_compute_dimm_parameters(c, (void *)spd, pdimm); + ret = ddr4_compute_dimm_parameters((void *)spd, pdimm); return ret; } @@ -377,12 +380,17 @@ static unsigned long long fsl_ddr_compute(struct fsl_ddr_info *pinfo) return total_mem; } -phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo) +phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo, bool little_endian) { unsigned int i; unsigned long long total_memory; int deassert_reset = 0; + if (little_endian) + ddr_endianess = DDR_ENDIANESS_LE; + else + ddr_endianess = DDR_ENDIANESS_BE; + total_memory = fsl_ddr_compute(pinfo); /* setup 3-way interleaving before enabling DDRC */ @@ -427,14 +435,14 @@ phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo) * The following call with step = 1 returns before enabling * the controller. It has to finish with step = 2 later. */ - fsl_ddr_set_memctl_regs(c, deassert_reset ? 1 : 0); + fsl_ddr_set_memctl_regs(c, deassert_reset ? 1 : 0, little_endian); } if (deassert_reset) { for (i = 0; i < pinfo->num_ctrls; i++) { struct fsl_ddr_controller *c = &pinfo->c[i]; /* Call with step = 2 to continue initialization */ - fsl_ddr_set_memctl_regs(c, 2); + fsl_ddr_set_memctl_regs(c, 2, little_endian); } } diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 73e9ab044e..5bfeeab495 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2008, 2010-2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP Semiconductor diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 977d22dcaa..ca7bf3e81b 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2008-2014 Freescale Semiconductor, Inc. */ @@ -8,7 +8,7 @@ #include <soc/fsl/fsl_immap.h> #include <io.h> #include <soc/fsl/immap_lsch2.h> -#include <asm-generic/div64.h> +#include <linux/math64.h> #include "fsl_ddr.h" /* To avoid 64-bit full-divides, we factor this here */ diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig new file mode 100644 index 0000000000..71d4144e85 --- /dev/null +++ b/drivers/ddr/imx/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "i.MX DDR controllers" + depends on ARCH_IMX8MQ || ARCH_IMX8MM || ARCH_IMX8MN || ARCH_IMX8MP || ARCH_IMX93 + +config IMX_DRAM + bool + +config IMX8M_DRAM + select IMX_DRAM + bool "imx8m dram controller support" + +config IMX9_DRAM + select IMX_DRAM + bool "imx9 dram controller support" + +endmenu diff --git a/drivers/ddr/imx/Makefile b/drivers/ddr/imx/Makefile new file mode 100644 index 0000000000..1d24522bbb --- /dev/null +++ b/drivers/ddr/imx/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# +pbl-$(CONFIG_IMX_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o +pbl-$(CONFIG_IMX8M_DRAM) += imx8m_ddr_init.o +pbl-$(CONFIG_IMX9_DRAM) += imx9_ddr_init.o diff --git a/drivers/ddr/imx8m/ddrphy_csr.c b/drivers/ddr/imx/ddrphy_csr.c index 98ac5db3c0..744e140879 100644 --- a/drivers/ddr/imx8m/ddrphy_csr.c +++ b/drivers/ddr/imx/ddrphy_csr.c @@ -1,8 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2018 NXP */ +#define pr_fmt(fmt) "imx-ddr: " fmt + #include <linux/kernel.h> #include <soc/imx8m/ddr.h> diff --git a/drivers/ddr/imx/ddrphy_train.c b/drivers/ddr/imx/ddrphy_train.c new file mode 100644 index 0000000000..d599445e6f --- /dev/null +++ b/drivers/ddr/imx/ddrphy_train.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2018 NXP + */ + +#define pr_fmt(fmt) "imx-ddr: " fmt + +#include <common.h> +#include <linux/kernel.h> +#include <soc/imx8m/ddr.h> +#include <firmware.h> + +static const u16 *lpddr4_imem_1d; +static size_t lpddr4_imem_1d_size; +static const u16 *lpddr4_dmem_1d; +static size_t lpddr4_dmem_1d_size; +static const u16 *lpddr4_imem_2d; +static size_t lpddr4_imem_2d_size; +static const u16 *lpddr4_dmem_2d; +static size_t lpddr4_dmem_2d_size; + +void ddr_get_firmware_lpddr4(void) +{ + get_builtin_firmware(lpddr4_pmu_train_1d_imem_bin, &lpddr4_imem_1d, + &lpddr4_imem_1d_size); + get_builtin_firmware(lpddr4_pmu_train_1d_dmem_bin, &lpddr4_dmem_1d, + &lpddr4_dmem_1d_size); + get_builtin_firmware(lpddr4_pmu_train_2d_imem_bin, &lpddr4_imem_2d, + &lpddr4_imem_2d_size); + get_builtin_firmware(lpddr4_pmu_train_2d_dmem_bin, &lpddr4_dmem_2d, + &lpddr4_dmem_2d_size); +} + +static const u16 *ddr4_imem_1d; +static size_t ddr4_imem_1d_size; +static const u16 *ddr4_dmem_1d; +static size_t ddr4_dmem_1d_size; +static const u16 *ddr4_imem_2d; +static size_t ddr4_imem_2d_size; +static const u16 *ddr4_dmem_2d; +static size_t ddr4_dmem_2d_size; + +void ddr_get_firmware_ddr(void) +{ + get_builtin_firmware(ddr4_imem_1d_bin, &ddr4_imem_1d, + &ddr4_imem_1d_size); + get_builtin_firmware(ddr4_dmem_1d_bin, &ddr4_dmem_1d, + &ddr4_dmem_1d_size); + get_builtin_firmware(ddr4_imem_2d_bin, &ddr4_imem_2d, + &ddr4_imem_2d_size); + get_builtin_firmware(ddr4_dmem_2d_bin, &ddr4_dmem_2d, + &ddr4_dmem_2d_size); +} + +void ddr_load_train_code(struct dram_controller *dram, enum dram_type dram_type, + enum fw_type fw_type) +{ + const u16 *imem, *dmem; + size_t isize, dsize; + + if (dram_is_lpddr4(dram_type)) { + if (fw_type == FW_1D_IMAGE) { + imem = lpddr4_imem_1d; + isize = lpddr4_imem_1d_size; + dmem = lpddr4_dmem_1d; + dsize = lpddr4_dmem_1d_size; + } else { + imem = lpddr4_imem_2d; + isize = lpddr4_imem_2d_size; + dmem = lpddr4_dmem_2d; + dsize = lpddr4_dmem_2d_size; + } + } else if (dram_is_ddr4(dram_type)) { + if (fw_type == FW_1D_IMAGE) { + imem = ddr4_imem_1d; + isize = ddr4_imem_1d_size; + dmem = ddr4_dmem_1d; + dsize = ddr4_dmem_1d_size; + } else { + imem = ddr4_imem_2d; + isize = ddr4_imem_2d_size; + dmem = ddr4_dmem_2d; + dsize = ddr4_dmem_2d_size; + } + } else { + panic("No matching DDR PHY firmware found"); + } + + ddrc_phy_load_firmware(dram, DDRC_PHY_IMEM, imem, isize); + + ddrc_phy_load_firmware(dram, DDRC_PHY_DMEM, dmem, dsize); +} + +int ddr_cfg_phy(struct dram_controller *dram, struct dram_timing_info *dram_timing) +{ + struct dram_cfg_param *dram_cfg; + struct dram_fsp_msg *fsp_msg; + unsigned int num; + int i = 0; + int j = 0; + int ret; + + /* initialize PHY configuration */ + dram_cfg = dram_timing->ddrphy_cfg; + num = dram_timing->ddrphy_cfg_num; + for (i = 0; i < num; i++) { + /* config phy reg */ + dwc_ddrphy_apb_wr(dram, dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* load the frequency setpoint message block config */ + fsp_msg = dram_timing->fsp_msg; + for (i = 0; i < dram_timing->fsp_msg_num; i++) { + pr_debug("DRAM PHY training for %dMTS\n", fsp_msg->drate); + /* set dram PHY input clocks to desired frequency */ + dram->set_dfi_clk(dram, fsp_msg->drate); + + /* load the dram training firmware image */ + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x0); + ddr_load_train_code(dram, dram->dram_type, fsp_msg->fw_type); + + /* load the frequency set point message block parameter */ + dram_cfg = fsp_msg->fsp_cfg; + num = fsp_msg->fsp_cfg_num; + for (j = 0; j < num; j++) { + dwc_ddrphy_apb_wr(dram, dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* + * -------------------- excute the firmware -------------------- + * Running the firmware is a simply process to taking the + * PMU out of reset and stall, then the firwmare will be run + * 1. reset the PMU; + * 2. begin the excution; + * 3. wait for the training done; + * 4. read the message block result. + * ------------------------------------------------------------- + */ + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x1); + dwc_ddrphy_apb_wr(dram, 0xd0099, 0x9); + dwc_ddrphy_apb_wr(dram, 0xd0099, 0x1); + dwc_ddrphy_apb_wr(dram, 0xd0099, 0x0); + + /* Wait for the training firmware to complete */ + ret = wait_ddrphy_training_complete(dram); + if (ret) + return ret; + + /* Halt the microcontroller. */ + dwc_ddrphy_apb_wr(dram, 0xd0099, 0x1); + + /* Read the Message Block results */ + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x0); + + if (fsp_msg->fw_type != FW_2D_IMAGE) + dram->get_trained_CDD(dram, i); + + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x1); + + fsp_msg++; + } + + /* Load PHY Init Engine Image */ + dram_cfg = dram_timing->ddrphy_pie; + num = dram_timing->ddrphy_pie_num; + for (i = 0; i < num; i++) { + dwc_ddrphy_apb_wr(dram, dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* save the ddr PHY trained CSR in memory for low power use */ + ddrphy_trained_csr_save(dram, ddrphy_trained_csr, ddrphy_trained_csr_num); + + return 0; +} diff --git a/drivers/ddr/imx/ddrphy_utils.c b/drivers/ddr/imx/ddrphy_utils.c new file mode 100644 index 0000000000..4925fc39d4 --- /dev/null +++ b/drivers/ddr/imx/ddrphy_utils.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* +* Copyright 2018 NXP +*/ + +#define pr_fmt(fmt) "imx-ddr: " fmt + +#include <common.h> +#include <errno.h> +#include <io.h> +#include <linux/iopoll.h> +#include <soc/imx8m/ddr.h> + +void ddrc_phy_load_firmware(struct dram_controller *dram, + enum ddrc_phy_firmware_offset offset, + const u16 *blob, size_t size) +{ + while (size) { + writew(*blob++, dwc_ddrphy_apb_addr(dram, offset)); + offset++; + size -= sizeof(*blob); + } +} + +enum pmc_constants { + PMC_MESSAGE_ID, + PMC_MESSAGE_STREAM, + + PMC_TRAIN_SUCCESS = 0x07, + PMC_TRAIN_STREAM_START = 0x08, + PMC_TRAIN_FAIL = 0xff, +}; + +static u32 ddrc_phy_get_message(struct dram_controller *dram, int type) +{ + u32 message; + + /* + * When BIT0 set to 0, the PMU has a message for the user + * Wait for it indefinitely. + */ + while (dwc_ddrphy_apb_rd(dram, 0xd0004) & BIT(0)); + + switch (type) { + case PMC_MESSAGE_ID: + /* + * Get the major message ID + */ + message = dwc_ddrphy_apb_rd(dram, 0xd0032); + break; + case PMC_MESSAGE_STREAM: + message = dwc_ddrphy_apb_rd(dram, 0xd0034); + message <<= 16; + message |= dwc_ddrphy_apb_rd(dram, 0xd0032); + break; + } + + /* + * By setting this register to 0, the user acknowledges the + * receipt of the message. + */ + dwc_ddrphy_apb_wr(dram, 0xd0031, 0x00000000); + /* + * When BIT0 set to 0, the PMU has a message for the user + */ + while (!(dwc_ddrphy_apb_rd(dram, 0xd0004) & BIT(0))); + + dwc_ddrphy_apb_wr(dram, 0xd0031, 0x00000001); + + return message; +} + +static void ddrc_phy_fetch_streaming_message(struct dram_controller *dram) +{ + const u16 index = ddrc_phy_get_message(dram, PMC_MESSAGE_STREAM); + u16 i; + + for (i = 0; i < index; i++) + ddrc_phy_get_message(dram, PMC_MESSAGE_STREAM); +} + +int wait_ddrphy_training_complete(struct dram_controller *dram) +{ + for (;;) { + const u32 m = ddrc_phy_get_message(dram, PMC_MESSAGE_ID); + + switch (m) { + case PMC_TRAIN_STREAM_START: + ddrc_phy_fetch_streaming_message(dram); + break; + case PMC_TRAIN_SUCCESS: + return 0; + case PMC_TRAIN_FAIL: + hang(); + } + } +} diff --git a/drivers/ddr/imx8m/helper.c b/drivers/ddr/imx/helper.c index 9e32ef9376..f9c25f7180 100644 --- a/drivers/ddr/imx8m/helper.c +++ b/drivers/ddr/imx/helper.c @@ -1,39 +1,40 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2018 NXP */ +#define pr_fmt(fmt) "imx-ddr: " fmt + #include <common.h> #include <io.h> #include <errno.h> #include <soc/imx8m/ddr.h> -#define IMEM_LEN 32768 /* byte */ -#define DMEM_LEN 16384 /* byte */ -#define IMEM_2D_OFFSET 49152 - -#define IMEM_OFFSET_ADDR 0x00050000 -#define DMEM_OFFSET_ADDR 0x00054000 -#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) +/* + * We deprecate ddrphy_trained_csr(_num) for board code, so we can set it + * ourselves here + */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wdeprecated-declarations" -void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, +void ddrphy_trained_csr_save(struct dram_controller *dram, struct dram_cfg_param *ddrphy_csr, unsigned int num) { int i = 0; /* enable the ddrphy apb */ - dwc_ddrphy_apb_wr(0xd0000, 0x0); - dwc_ddrphy_apb_wr(0xc0080, 0x3); + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x0); + dwc_ddrphy_apb_wr(dram, 0xc0080, 0x3); for (i = 0; i < num; i++) { - ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg); + ddrphy_csr->val = dwc_ddrphy_apb_rd(dram, ddrphy_csr->reg); ddrphy_csr++; } /* disable the ddrphy apb */ - dwc_ddrphy_apb_wr(0xc0080, 0x2); - dwc_ddrphy_apb_wr(0xd0000, 0x1); + dwc_ddrphy_apb_wr(dram, 0xc0080, 0x2); + dwc_ddrphy_apb_wr(dram, 0xd0000, 0x1); } -void dram_config_save(struct dram_timing_info *timing_info, +void *dram_config_save(struct dram_controller *dram, struct dram_timing_info *timing_info, unsigned long saved_timing_base) { int i = 0; @@ -60,6 +61,12 @@ void dram_config_save(struct dram_timing_info *timing_info, cfg++; } + if (dram->imx8m_ddr_old_spreadsheet) { + cfg->reg = DDRC_ADDRMAP7(0); + cfg->val = 0xf0f; + cfg++; + } + /* save ddrphy config */ saved_timing->ddrphy_cfg = cfg; for (i = 0; i < timing_info->ddrphy_cfg_num; i++) { @@ -83,4 +90,6 @@ void dram_config_save(struct dram_timing_info *timing_info, cfg->val = timing_info->ddrphy_pie[i].val; cfg++; } + + return cfg; } diff --git a/drivers/ddr/imx/imx8m_ddr_init.c b/drivers/ddr/imx/imx8m_ddr_init.c new file mode 100644 index 0000000000..d9a5d589f2 --- /dev/null +++ b/drivers/ddr/imx/imx8m_ddr_init.c @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2018-2019 NXP + */ + +#define pr_fmt(fmt) "imx8m-ddr: " fmt + +#include <common.h> +#include <errno.h> +#include <io.h> +#include <soc/imx8m/ddr.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8m-regs.h> +#include <mach/imx/imx8m-ccm-regs.h> + +struct dram_controller imx8m_dram_controller = { + .phy_base = IOMEM(IP2APB_DDRPHY_IPS_BASE_ADDR(0)), +}; + +static void ddr_cfg_umctl2(struct dram_controller *dram, struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + dram->imx8m_ddr_old_spreadsheet = true; + + for (i = 0; i < num; i++) { + if (ddrc_cfg->reg == DDRC_ADDRMAP7(0)) + dram->imx8m_ddr_old_spreadsheet = false; + reg32_write((unsigned long)ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } + + /* + * Older NXP DDR configuration spreadsheets don't initialize ADDRMAP7, + * which falsifies the memory size read back from the controller + * in barebox proper. + */ + if (dram->imx8m_ddr_old_spreadsheet) { + pr_warn("Working around old spreadsheet. Please regenerate\n"); + /* + * Alternatively, stick { DDRC_ADDRMAP7(0), 0xf0f } into + * struct dram_timing_info::ddrc_cfg of your old timing file + */ + reg32_write(DDRC_ADDRMAP7(0), 0xf0f); + } +} + +static unsigned int g_cdd_rr_max[4]; +static unsigned int g_cdd_rw_max[4]; +static unsigned int g_cdd_wr_max[4]; +static unsigned int g_cdd_ww_max[4]; + +static unsigned int look_for_max(unsigned int data[], unsigned int addr_start, + unsigned int addr_end) +{ + unsigned int i, imax = 0; + + for (i = addr_start; i <= addr_end; i++) { + if (((data[i] >> 7) == 0) && (data[i] > imax)) + imax = data[i]; + } + + return imax; +} + +static void get_trained_CDD(struct dram_controller *dram, u32 fsp) +{ + unsigned int i, ddr_type, tmp; + unsigned int cdd_cha[12], cdd_chb[12]; + unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max; + unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max; + + ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; + if (ddr_type == 0x20) { + for (i = 0; i < 6; i++) { + tmp = dwc_ddrphy_apb_rd(dram, 0x54013UL + i); + cdd_cha[i * 2] = tmp & 0xff; + cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff; + } + + for (i = 0; i < 7; i++) { + tmp = dwc_ddrphy_apb_rd(dram, 0x5402cUL + i); + if (i == 0) { + cdd_cha[0] = (tmp >> 8) & 0xff; + } else if (i == 6) { + cdd_cha[11] = tmp & 0xff; + } else { + cdd_chb[ i * 2 - 1] = tmp & 0xff; + cdd_chb[i * 2] = (tmp >> 8) & 0xff; + } + } + + cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1); + cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5); + cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9); + cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11); + cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1); + cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5); + cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9); + cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11); + g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max; + g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max; + g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max; + g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; + } else { + unsigned int ddr4_cdd[64]; + + for( i = 0; i < 29; i++) { + tmp = dwc_ddrphy_apb_rd(dram, 0x54012UL + i); + ddr4_cdd[i * 2] = tmp & 0xff; + ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff; + } + + g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12); + g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24); + g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40); + g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56); + } +} + +static void update_umctl2_rank_space_setting(unsigned int pstat_num, + enum ddrc_type type) +{ + unsigned int i,ddr_type; + unsigned int rdata, tmp, tmp_t; + unsigned int ddrc_w2r,ddrc_r2w,ddrc_wr_gap,ddrc_rd_gap; + unsigned long addr_slot; + + ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; + for (i = 0; i < pstat_num; i++) { + addr_slot = i ? (i + 1) * 0x1000 : 0; + if (ddr_type == 0x20) { + /* update r2w:[13:8], w2r:[5:0] */ + rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); + ddrc_w2r = rdata & 0x3f; + if (type == DDRC_TYPE_MP) + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); + else + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1; + ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp; + + ddrc_r2w = (rdata >> 8) & 0x3f; + if (type == DDRC_TYPE_MP) + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1); + else + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1; + ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp; + + tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r; + reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t); + } else { + /* update w2r:[5:0] */ + rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot); + ddrc_w2r = rdata & 0x3f; + if (type == DDRC_TYPE_MP) + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); + else + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1; + ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp; + tmp_t = (rdata & 0xffffffc0) | ddrc_w2r; + reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t); + + /* update r2w:[13:8] */ + rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); + ddrc_r2w = (rdata >> 8) & 0x3f; + if (type == DDRC_TYPE_MP) + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1); + else + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1; + ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp; + + tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8); + reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t); + } + + if (type != DDRC_TYPE_MQ) { + /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */ + rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot); + ddrc_wr_gap = (rdata >> 8) & 0xf; + if (type == DDRC_TYPE_MP) + tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1); + else + tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1; + ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp; + + ddrc_rd_gap = (rdata >> 4) & 0xf; + if (type == DDRC_TYPE_MP) + tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1); + else + tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1; + ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp; + + tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4); + reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t); + } + } + + if (type == DDRC_TYPE_MQ) { + /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */ + rdata = reg32_read(DDRC_RANKCTL(0)); + ddrc_wr_gap = (rdata >> 8) & 0xf; + tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1; + ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp; + + ddrc_rd_gap = (rdata >> 4) & 0xf; + tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1; + ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp; + + tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4); + reg32_write(DDRC_RANKCTL(0), tmp_t); + } +} + + +/* DDR Transfer rate, bus clock is transfer rate / 2, and the DDRC runs at bus + * clock / 2, which is therefor transfer rate / 4. */ +enum ddr_rate { + DDR_4000, + DDR_3720, + DDR_3200, + DDR_3000, + DDR_2600, + DDR_2400, + DDR_2376, + DDR_1600, + DDR_1000, /* Unused */ + DDR_1066, + DDR_667, + DDR_400, + DDR_250, /* Unused */ + DDR_100, + DDR_NUM_RATES +}; + +/* PLL config for IMX8MM type DRAM PLL. This PLL type isn't documented, but + * it looks like it is a basically a fractional PLL: + * Frequency = Ref (24 MHz) / P * M / 2^S + * Note: Divider is equal to register value + */ +#define MDIV(x) ((x) << 12) +#define PDIV(x) ((x) << 4) +#define SDIV(x) ((x) << 0) + +#define LOCK_STATUS BIT(31) +#define LOCK_SEL_MASK BIT(29) +#define CLKE_MASK BIT(11) +#define RST_MASK BIT(9) +#define BYPASS_MASK BIT(4) + +static const struct imx8mm_fracpll_config { + uint32_t r1, r2; + bool valid; +} imx8mm_fracpll_table[DDR_NUM_RATES] = { + [DDR_4000] = { .valid = true, .r1 = MDIV(250) | PDIV(3) | SDIV(1), .r2 = 0 }, + [DDR_3720] = { .valid = true, .r1 = MDIV(310) | PDIV(2) | SDIV(2), .r2 = 0 }, + [DDR_3200] = { .valid = true, .r1 = MDIV(300) | PDIV(9) | SDIV(0), .r2 = 0 }, + [DDR_3000] = { .valid = true, .r1 = MDIV(250) | PDIV(8) | SDIV(0), .r2 = 0 }, + [DDR_2600] = { .valid = true, .r1 = MDIV(325) | PDIV(3) | SDIV(2), .r2 = 0 }, + [DDR_2400] = { .valid = true, .r1 = MDIV(300) | PDIV(3) | SDIV(2), .r2 = 0 }, + [DDR_2376] = { .valid = true, .r1 = MDIV( 99) | PDIV(1) | SDIV(2), .r2 = 0 }, + [DDR_1600] = { .valid = true, .r1 = MDIV(300) | PDIV(9) | SDIV(1), .r2 = 0 }, + [DDR_1066] = { .valid = true, .r1 = MDIV(400) | PDIV(9) | SDIV(2), .r2 = 0 }, + [DDR_667] = { .valid = true, .r1 = MDIV(334) | PDIV(3) | SDIV(4), .r2 = 0 }, + [DDR_400] = { .valid = true, .r1 = MDIV(300) | PDIV(9) | SDIV(3), .r2 = 0 }, +}; + +/* PLL config for IMX8MQ type DRAM PLL. This is SSCG_PLL: + * Frequency = Ref (25 MHz) / divr1 * (2*divf1) / divr2 * divf2 / divq + * Note: IMX8MQ RM, §5.1.5.4.4 Fig. 5-8 shows ÷2 on divf2, but this is not true. + * Note: divider is register value + 1 + */ +#define SSCG_PLL_LOCK BIT(31) +#define SSCG_PLL_DRAM_PLL_CLKE BIT(9) +#define SSCG_PLL_PD BIT(7) +#define SSCG_PLL_BYPASS1 BIT(5) +#define SSCG_PLL_BYPASS2 BIT(4) + +#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19) +#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK) +#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13) +#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & SSCG_PLL_FEEDBACK_DIV_F1_MASK) +#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7) +#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & SSCG_PLL_FEEDBACK_DIV_F2_MASK) +#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1) +#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & SSCG_PLL_OUTPUT_DIV_VAL_MASK) + +#define SSCG_PLL_CFG2(divf1, divr2, divf2, divq) \ + (SSCG_PLL_FEEDBACK_DIV_F1_VAL(divf1) | SSCG_PLL_FEEDBACK_DIV_F2_VAL(divf2) | \ + SSCG_PLL_REF_DIVR2_VAL(divr2) | SSCG_PLL_OUTPUT_DIV_VAL(divq)) + +static const struct imx8mq_ssgcpll_config { + uint32_t val; + bool valid; +} imx8mq_ssgcpll_table[DDR_NUM_RATES] = { + [DDR_3200] = { .valid = true, .val = SSCG_PLL_CFG2(39, 29, 11, 0) }, + [DDR_2400] = { .valid = true, .val = SSCG_PLL_CFG2(39, 29, 17, 1) }, + [DDR_1600] = { .valid = true, .val = SSCG_PLL_CFG2(39, 29, 11, 1) }, + [DDR_667] = { .valid = true, .val = SSCG_PLL_CFG2(45, 30, 8, 3) }, /* ~166.935 MHz = 667.74 */ +}; + +/* IMX8M Bypass clock config. These configure dram_alt1_clk and the dram apb + * clock. For the bypass config, clock rate = DRAM tranfer rate, rather than + * clock = dram / 4 + */ + +/* prediv is actual divider, register will be set to divider - 1 */ +#define CCM_ROOT_CFG(mux, prediv) (IMX8M_CCM_TARGET_ROOTn_ENABLE | \ + IMX8M_CCM_TARGET_ROOTn_MUX(mux) | IMX8M_CCM_TARGET_ROOTn_PRE_DIV(prediv-1)) + +static const struct imx8m_bypass_config { + uint32_t alt_clk; + uint32_t apb_clk; + bool valid; +} imx8m_bypass_table[DDR_NUM_RATES] = { + [DDR_400] = { .valid = true, .alt_clk = CCM_ROOT_CFG(1, 2), .apb_clk = CCM_ROOT_CFG(3, 2) }, + [DDR_250] = { .valid = true, .alt_clk = CCM_ROOT_CFG(3, 2), .apb_clk = CCM_ROOT_CFG(2, 2) }, + [DDR_100] = { .valid = true, .alt_clk = CCM_ROOT_CFG(2, 1), .apb_clk = CCM_ROOT_CFG(2, 2) }, +}; + +static void dram_enable_bypass(enum ddr_rate drate) +{ + const struct imx8m_bypass_config *config = &imx8m_bypass_table[drate]; + + if (!config->valid) { + pr_warn("No matched freq table entry %u\n", drate); + return; + } + + imx8m_clock_set_target_val(IMX8M_DRAM_ALT_CLK_ROOT, config->alt_clk); + imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT, config->apb_clk); + imx8m_clock_set_target_val(IMX8M_DRAM_SEL_CFG, IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(1)); +} + +static void dram_disable_bypass(void) +{ + imx8m_clock_set_target_val(IMX8M_DRAM_SEL_CFG, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(0)); + imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT, + IMX8M_CCM_TARGET_ROOTn_ENABLE | + IMX8M_CCM_TARGET_ROOTn_MUX(4) | + IMX8M_CCM_TARGET_ROOTn_PRE_DIV(5 - 1)); +} + +static int dram_frac_pll_init(enum ddr_rate drate) +{ + volatile int i; + u32 tmp; + void *pll_base; + const struct imx8mm_fracpll_config *config = &imx8mm_fracpll_table[drate]; + + if (!config->valid) { + pr_warn("No matched freq table entry %u\n", drate); + return -EINVAL; + } + + setbits_le32(MX8M_GPC_BASE_ADDR + 0xec, 1 << 7); + setbits_le32(MX8M_GPC_BASE_ADDR + 0xf8, 1 << 5); + writel(0x8F000000UL, MX8M_SRC_BASE_ADDR + 0x1004); + + pll_base = IOMEM(MX8M_ANATOP_BASE_ADDR) + 0x50; + + /* Bypass clock and set lock to pll output lock */ + tmp = readl(pll_base); + tmp |= BYPASS_MASK; + writel(tmp, pll_base); + + /* Enable RST */ + tmp &= ~RST_MASK; + writel(tmp, pll_base); + + writel(config->r1, pll_base + 4); + writel(config->r2, pll_base + 8); + + for (i = 0; i < 1000; i++); + + /* Disable RST */ + tmp |= RST_MASK; + writel(tmp, pll_base); + + /* Wait Lock*/ + while (!(readl(pll_base) & LOCK_STATUS)); + + /* Bypass */ + tmp &= ~BYPASS_MASK; + writel(tmp, pll_base); + + return 0; +} + +static int dram_sscg_pll_init(enum ddr_rate drate) +{ + u32 val; + void __iomem *pll_base = IOMEM(MX8M_ANATOP_BASE_ADDR) + 0x60; + const struct imx8mq_ssgcpll_config *config = &imx8mq_ssgcpll_table[drate]; + + if (!config->valid) { + pr_warn("No matched freq table entry %u\n", drate); + return -EINVAL; + } + + /* Bypass */ + setbits_le32(pll_base, SSCG_PLL_BYPASS1 | SSCG_PLL_BYPASS2); + + val = readl(pll_base + 0x8); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | + SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | + SSCG_PLL_REF_DIVR2_MASK); + val |= config->val; + writel(val, pll_base + 0x8); + + /* Clear power down bit */ + clrbits_le32(pll_base, SSCG_PLL_PD); + /* Enable PLL */ + setbits_le32(pll_base, SSCG_PLL_DRAM_PLL_CLKE); + + /* Clear bypass */ + clrbits_le32(pll_base, SSCG_PLL_BYPASS1); + udelay(100); + clrbits_le32(pll_base, SSCG_PLL_BYPASS2); + /* Wait lock */ + while (!(readl(pll_base) & SSCG_PLL_LOCK)) + ; + + return 0; +} + +static int dram_pll_init(enum ddr_rate drate, enum ddrc_type type) +{ + switch (type) { + case DDRC_TYPE_MQ: + return dram_sscg_pll_init(drate); + case DDRC_TYPE_MM: + case DDRC_TYPE_MN: + case DDRC_TYPE_MP: + return dram_frac_pll_init(drate); + default: + return -ENODEV; + } +} + +static void ddrphy_init_set_dfi_clk(struct dram_controller *dram, unsigned int drate_mhz) +{ + enum ddr_rate drate; + + switch (drate_mhz) { + case 4000: drate = DDR_4000; break; + case 3720: drate = DDR_3720; break; + case 3200: drate = DDR_3200; break; + case 3000: drate = DDR_3000; break; + case 2600: drate = DDR_2600; break; + case 2400: drate = DDR_2400; break; + case 2376: drate = DDR_2376; break; + case 1600: drate = DDR_1600; break; + case 1066: drate = DDR_1066; break; + case 667: drate = DDR_667; break; + case 400: drate = DDR_400; break; + case 100: drate = DDR_100; break; + default: + pr_warn("Unsupported frequency %u\n", drate_mhz); + return; + } + + if (drate_mhz > 400) { + dram_pll_init(drate, dram->ddrc_type); + dram_disable_bypass(); + } else { + dram_enable_bypass(drate); + } +} + +/* + * We store the timing parameters here. the TF-A will pick these up. + * Note that the timing used we leave the driver with is a PLL bypass 25MHz + * mode. So if your board runs horribly slow you'll likely have to provide a + * TF-A binary. + */ +#define IMX8M_SAVED_DRAM_TIMING_BASE 0x180000 + +int imx8m_ddr_init(struct dram_controller *dram, struct dram_timing_info *dram_timing) +{ + unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR; + unsigned int tmp, initial_drate, target_freq; + int ret; + + pr_debug("start DRAM init\n"); + + dram->get_trained_CDD = get_trained_CDD; + dram->set_dfi_clk = ddrphy_init_set_dfi_clk; + + /* Step1: Follow the power up procedure */ + switch (dram->ddrc_type) { + case DDRC_TYPE_MQ: + reg32_write(src_ddrc_rcr + 0x04, 0x8f00000f); + reg32_write(src_ddrc_rcr, 0x8f00000f); + reg32_write(src_ddrc_rcr + 0x04, 0x8f000000); + break; + case DDRC_TYPE_MM: + case DDRC_TYPE_MN: + case DDRC_TYPE_MP: + reg32_write(src_ddrc_rcr, 0x8f00001f); + reg32_write(src_ddrc_rcr, 0x8f00000f); + break; + } + + pr_debug("cfg clk\n"); + + /* disable iso */ + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + + initial_drate = dram_timing->fsp_msg[0].drate; + /* default to the frequency point 0 clock */ + dram->set_dfi_clk(dram, initial_drate); + + /* D-aasert the presetn */ + reg32_write(src_ddrc_rcr, 0x8F000006); + + /* Step2: Program the dwc_ddr_umctl2 registers */ + pr_debug("ddrc config start\n"); + ddr_cfg_umctl2(dram, dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + pr_debug("ddrc config done\n"); + + /* Step3: De-assert reset signal(core_ddrc_rstn & aresetn_n) */ + reg32_write(src_ddrc_rcr, 0x8F000004); + reg32_write(src_ddrc_rcr, 0x8F000000); + + /* + * Step4: Disable auto-refreshes, self-refresh, powerdown, and + * assertion of dfi_dram_clk_disable by setting RFSHCTL3.dis_auto_refresh = 1, + * PWRCTL.powerdown_en = 0, and PWRCTL.selfref_en = 0, + * PWRCTL.en_dfi_dram_clk_disable = 0 + */ + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_RFSHCTL3(0), 0x0000001); + reg32_write(DDRC_PWRCTL(0), 0xa0); + + pr_debug("checking ddr type\n"); + /* + * below is first read, so if boot hangs here, imx8m*_early_clock_init() + * might not have been called + */ + tmp = reg32_read(DDRC_MSTR(0)); + if (tmp & (0x1 << 5) && dram->ddrc_type != DDRC_TYPE_MN) + reg32_write(MX8M_DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ + + /* determine the initial boot frequency */ + target_freq = reg32_read(DDRC_MSTR2(0)) & 0x3; + target_freq = (tmp & (0x1 << 29)) ? target_freq : 0x0; + + /* Step5: Set SWCT.sw_done to 0 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* Set the default boot frequency point */ + clrsetbits_le32(DDRC_DFIMISC(0), (0x1f << 8), target_freq << 8); + /* Step6: Set DFIMISC.dfi_init_complete_en to 0 */ + clrbits_le32(DDRC_DFIMISC(0), 0x1); + + /* Step7: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* + * Step8 ~ Step13: Start PHY initialization and training by + * accessing relevant PUB registers + */ + pr_debug("ddrphy config start\n"); + + ret = ddr_cfg_phy(dram, dram_timing); + if (ret) + return ret; + + pr_debug("ddrphy config done\n"); + + /* + * step14 CalBusy.0 =1, indicates the calibrator is actively + * calibrating. Wait Calibrating done. + */ + do { + tmp = reg32_read(DDRPHY_CalBusy(0)); + } while ((tmp & 0x1)); + + pr_debug("ddrphy calibration done\n"); + + /* Step15: Set SWCTL.sw_done to 0 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* Apply rank-to-rank workaround */ + update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1, dram->ddrc_type); + + /* Step16: Set DFIMISC.dfi_init_start to 1 */ + setbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); + + /* Step17: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* Step18: Polling DFISTAT.dfi_init_complete = 1 */ + do { + tmp = reg32_read(DDRC_DFISTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* Step19: Set SWCTL.sw_done to 0 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* Step20: Set DFIMISC.dfi_init_start to 0 */ + clrbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); + + /* Step21: optional */ + + /* Step22: Set DFIMISC.dfi_init_complete_en to 1 */ + setbits_le32(DDRC_DFIMISC(0), 0x1); + + /* Step23: Set PWRCTL.selfref_sw to 0 */ + clrbits_le32(DDRC_PWRCTL(0), (0x1 << 5)); + + /* Step24: Set SWCTL.sw_done to 1; need polling SWSTAT.sw_done_ack */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* Step25: Wait for dwc_ddr_umctl2 to move to normal operating mode by monitoring + * STAT.operating_mode signal */ + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x3) != 0x1); + + /* Step26: Set back register in Step4 to the original values if desired */ + reg32_write(DDRC_RFSHCTL3(0), 0x0000000); + /* enable selfref_en by default */ + setbits_le32(DDRC_PWRCTL(0), 0x1); + + /* enable port 0 */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + pr_debug("ddrmix config done\n"); + + /* save the dram timing config into memory */ + dram_config_save(dram, dram_timing, IMX8M_SAVED_DRAM_TIMING_BASE); + + return 0; +} diff --git a/drivers/ddr/imx/imx9_ddr_init.c b/drivers/ddr/imx/imx9_ddr_init.c new file mode 100644 index 0000000000..cdee18e4ad --- /dev/null +++ b/drivers/ddr/imx/imx9_ddr_init.c @@ -0,0 +1,698 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#define pr_fmt(fmt) "imx9-ddr: " fmt + +#include <common.h> +#include <errno.h> +#include <io.h> +#include <soc/imx9/ddr.h> +#include <mach/imx/generic.h> +#include <linux/iopoll.h> +#include <soc/imx/clk-fracn-gppll.h> +#include <mach/imx/imx9-regs.h> + +#define MX9_SRC_DPHY_BASE_ADDR (MX9_SRC_BASE_ADDR + 0x1400) +#define REG_DDR_SDRAM_MD_CNTL (MX9_DDR_CTL_BASE + 0x120) +#define REG_DDR_CS0_BNDS (MX9_DDR_CTL_BASE + 0x0) +#define REG_DDR_CS1_BNDS (MX9_DDR_CTL_BASE + 0x8) +#define REG_DDRDSR_2 (MX9_DDR_CTL_BASE + 0xB24) +#define REG_DDR_TIMING_CFG_0 (MX9_DDR_CTL_BASE + 0x104) +#define REG_DDR_SDRAM_CFG (MX9_DDR_CTL_BASE + 0x110) +#define REG_DDR_TIMING_CFG_4 (MX9_DDR_CTL_BASE + 0x160) +#define REG_DDR_DEBUG_19 (MX9_DDR_CTL_BASE + 0xF48) +#define REG_DDR_SDRAM_CFG_3 (MX9_DDR_CTL_BASE + 0x260) +#define REG_DDR_SDRAM_CFG_4 (MX9_DDR_CTL_BASE + 0x264) +#define REG_DDR_SDRAM_MD_CNTL_2 (MX9_DDR_CTL_BASE + 0x270) +#define REG_DDR_SDRAM_MPR4 (MX9_DDR_CTL_BASE + 0x28C) +#define REG_DDR_SDRAM_MPR5 (MX9_DDR_CTL_BASE + 0x290) + +#define REG_DDR_ERR_EN (MX9_DDR_CTL_BASE + 0x1000) +#define REG_SRC_DPHY_SW_CTRL (MX9_SRC_DPHY_BASE_ADDR + 0x20) +#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (MX9_SRC_DPHY_BASE_ADDR + 0x24) + +#define IMX9_SAVED_DRAM_TIMING_BASE 0x2051C000 + +static unsigned int g_cdd_rr_max[4]; +static unsigned int g_cdd_rw_max[4]; +static unsigned int g_cdd_wr_max[4]; +static unsigned int g_cdd_ww_max[4]; + +static void ddrphy_coldreset(void) +{ + /* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */ + /* dramphy_reset_n default 0 , assert -> 0, de_assert -> 1 */ + /* dramphy_PwrOKIn default 0 , assert -> 1, de_assert -> 0 */ + + /* src_gen_dphy_apb_sw_rst_de_assert */ + clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0)); + /* src_gen_dphy_sw_rst_de_assert */ + clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2)); + /* src_gen_dphy_PwrOKIn_sw_rst_de_assert() */ + setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0)); + mdelay(10); + + /* src_gen_dphy_apb_sw_rst_assert */ + setbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0)); + /* src_gen_dphy_sw_rst_assert */ + setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2)); + mdelay(10); + /* src_gen_dphy_PwrOKIn_sw_rst_assert */ + clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0)); + mdelay(10); + + /* src_gen_dphy_apb_sw_rst_de_assert */ + clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0)); + /* src_gen_dphy_sw_rst_de_assert() */ + clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2)); +} + +static void check_ddrc_idle(void) +{ + u32 regval; + + readl_poll_timeout(REG_DDRDSR_2, regval, regval & BIT(31), 0); +} + +static void check_dfi_init_complete(void) +{ + u32 regval; + + readl_poll_timeout(REG_DDRDSR_2, regval, regval & BIT(2), 0); + + setbits_le32(REG_DDRDSR_2, BIT(2)); +} + +static void ddrc_config(struct dram_timing_info *dram_timing) +{ + u32 num = dram_timing->ddrc_cfg_num; + struct dram_cfg_param *ddrc_config; + int i = 0; + + ddrc_config = dram_timing->ddrc_cfg; + for (i = 0; i < num; i++) { + writel(ddrc_config->val, (ulong)ddrc_config->reg); + ddrc_config++; + } + + if (dram_timing->fsp_cfg) { + ddrc_config = dram_timing->fsp_cfg[0].ddrc_cfg; + while (ddrc_config->reg != 0) { + writel(ddrc_config->val, (ulong)ddrc_config->reg); + ddrc_config++; + } + } +} + +static unsigned int look_for_max(unsigned int data[], unsigned int addr_start, + unsigned int addr_end) +{ + unsigned int i, imax = 0; + + for (i = addr_start; i <= addr_end; i++) { + if (((data[i] >> 7) == 0) && data[i] > imax) + imax = data[i]; + } + + return imax; +} + +static void get_trained_CDD(struct dram_controller *dram, u32 fsp) +{ + unsigned int i, tmp; + unsigned int cdd_cha[12], cdd_chb[12]; + unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max; + unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max; + + for (i = 0; i < 6; i++) { + tmp = dwc_ddrphy_apb_rd(dram, 0x54013 + i); + cdd_cha[i * 2] = tmp & 0xff; + cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff; + } + + for (i = 0; i < 7; i++) { + tmp = dwc_ddrphy_apb_rd(dram, 0x5402c + i); + + if (i == 0) { + cdd_chb[0] = (tmp >> 8) & 0xff; + } else if (i == 6) { + cdd_chb[11] = tmp & 0xff; + } else { + cdd_chb[i * 2 - 1] = tmp & 0xff; + cdd_chb[i * 2] = (tmp >> 8) & 0xff; + } + } + + cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1); + cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5); + cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9); + cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11); + cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1); + cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5); + cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9); + cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11); + g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max; + g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max; + g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max; + g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; +} + +static u32 ddrc_get_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, unsigned int cfg_num, u32 reg) +{ + unsigned int i; + + for (i = 0; i < cfg_num; i++) { + if (reg == ddrc_cfg[i].reg) + return ddrc_cfg[i].val; + } + + return 0; +} + +static void ddrc_update_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, int cfg_num, + u32 reg, u32 val) +{ + unsigned int i; + + for (i = 0; i < cfg_num; i++) { + if (reg == ddrc_cfg[i].reg) { + ddrc_cfg[i].val = val; + return; + } + } +} + +static void update_umctl2_rank_space_setting(struct dram_timing_info *dram_timing, + unsigned int pstat_num) +{ + u32 tmp, tmp_t; + u32 wwt, rrt, wrt, rwt; + u32 ext_wwt, ext_rrt, ext_wrt, ext_rwt; + u32 max_wwt, max_rrt, max_wrt, max_rwt; + u32 i; + + for (i = 0; i < pstat_num; i++) { + /* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */ + if (!dram_timing->fsp_cfg_num) { + tmp = ddrc_get_fsp_reg_setting(dram_timing->ddrc_cfg, + dram_timing->ddrc_cfg_num, + REG_DDR_TIMING_CFG_0); + } else { + tmp = ddrc_get_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg, + ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg), + REG_DDR_TIMING_CFG_0); + } + wwt = (tmp >> 24) & 0x3; + rrt = (tmp >> 26) & 0x3; + wrt = (tmp >> 28) & 0x3; + rwt = (tmp >> 30) & 0x3; + + /* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */ + if (!dram_timing->fsp_cfg_num) { + tmp_t = ddrc_get_fsp_reg_setting(dram_timing->ddrc_cfg, + dram_timing->ddrc_cfg_num, + REG_DDR_TIMING_CFG_4); + } else { + tmp_t = ddrc_get_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg, + ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg), + REG_DDR_TIMING_CFG_4); + } + ext_wwt = (tmp_t >> 8) & 0x3; + ext_rrt = (tmp_t >> 10) & 0x3; + ext_wrt = (tmp_t >> 12) & 0x3; + ext_rwt = (tmp_t >> 14) & 0x3; + + wwt = (ext_wwt << 2) | wwt; + rrt = (ext_rrt << 2) | rrt; + wrt = (ext_wrt << 2) | wrt; + rwt = (ext_rwt << 2) | rwt; + + max_wwt = max(g_cdd_ww_max[0], wwt); + max_rrt = max(g_cdd_rr_max[0], rrt); + max_wrt = max(g_cdd_wr_max[0], wrt); + max_rwt = max(g_cdd_rw_max[0], rwt); + /* verify values to see if are bigger then 15 (4 bits) */ + if (max_wwt > 15) + max_wwt = 15; + if (max_rrt > 15) + max_rrt = 15; + if (max_wrt > 15) + max_wrt = 15; + if (max_rwt > 15) + max_rwt = 15; + + /* recalculate timings for controller registers */ + wwt = max_wwt & 0x3; + rrt = max_rrt & 0x3; + wrt = max_wrt & 0x3; + rwt = max_rwt & 0x3; + + ext_wwt = (max_wwt & 0xC) >> 2; + ext_rrt = (max_rrt & 0xC) >> 2; + ext_wrt = (max_wrt & 0xC) >> 2; + ext_rwt = (max_rwt & 0xC) >> 2; + + /* update timing_cfg_0 and timing_cfg_4 */ + tmp = (tmp & 0x00ffffff) | (rwt << 30) | (wrt << 28) | + (rrt << 26) | (wwt << 24); + tmp_t = (tmp_t & 0xFFFF00FF) | (ext_rwt << 14) | + (ext_wrt << 12) | (ext_rrt << 10) | (ext_wwt << 8); + + if (!dram_timing->fsp_cfg_num) { + ddrc_update_fsp_reg_setting(dram_timing->ddrc_cfg, + dram_timing->ddrc_cfg_num, + REG_DDR_TIMING_CFG_0, tmp); + ddrc_update_fsp_reg_setting(dram_timing->ddrc_cfg, + dram_timing->ddrc_cfg_num, + REG_DDR_TIMING_CFG_4, tmp_t); + } else { + ddrc_update_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg, + ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg), + REG_DDR_TIMING_CFG_0, tmp); + ddrc_update_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg, + ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg), + REG_DDR_TIMING_CFG_4, tmp_t); + } + } +} + +static u32 ddrc_mrr(u32 chip_select, u32 mode_reg_num, u32 *mode_reg_val) +{ + u32 temp; + + writel(0x80000000, REG_DDR_SDRAM_MD_CNTL_2); + temp = 0x80000000 | (chip_select << 28) | (mode_reg_num << 0); + writel(temp, REG_DDR_SDRAM_MD_CNTL); + while ((readl(REG_DDR_SDRAM_MD_CNTL) & 0x80000000) == 0x80000000) + ; + while (!(readl(REG_DDR_SDRAM_MPR5))) + ; + *mode_reg_val = (readl(REG_DDR_SDRAM_MPR4) & 0xFF0000) >> 16; + writel(0x0, REG_DDR_SDRAM_MPR5); + while ((readl(REG_DDR_SDRAM_MPR5))) + ; + writel(0x0, REG_DDR_SDRAM_MPR4); + writel(0x0, REG_DDR_SDRAM_MD_CNTL_2); + + return 0; +} + +static void ddrc_mrs(u32 cs_sel, u32 opcode, u32 mr) +{ + u32 regval; + + regval = (cs_sel << 28) | (opcode << 6) | (mr); + writel(regval, REG_DDR_SDRAM_MD_CNTL); + setbits_le32(REG_DDR_SDRAM_MD_CNTL, BIT(31)); + check_ddrc_idle(); +} + +static u32 lpddr4_mr_read(u32 mr_rank, u32 mr_addr) +{ + u32 chip_select, regval; + + if (mr_rank == 1) + chip_select = 0; /* CS0 */ + else if (mr_rank == 2) + chip_select = 1; /* CS1 */ + else + chip_select = 4; /* CS0 & CS1 */ + + ddrc_mrr(chip_select, mr_addr, ®val); + + return regval; +} + +static void update_mr_fsp_op0(struct dram_cfg_param *cfg, unsigned int num) +{ + int i; + + ddrc_mrs(0x4, 0x88, 13); /* FSP-OP->1, FSP-WR->0, VRCG=1, DMD=0 */ + for (i = 0; i < num; i++) { + if (cfg[i].reg) + ddrc_mrs(0x4, cfg[i].val, cfg[i].reg); + } + ddrc_mrs(0x4, 0xc0, 13); /* FSP-OP->1, FSP-WR->1, VRCG=0, DMD=0 */ +} + +static void save_trained_mr12_14(struct dram_cfg_param *cfg, u32 cfg_num, u32 mr12, u32 mr14) +{ + int i; + + for (i = 0; i < cfg_num; i++) { + if (cfg->reg == 12) + cfg->val = mr12; + else if (cfg->reg == 14) + cfg->val = mr14; + cfg++; + } +} + +#define MHZ(x) ((x) * 1000000UL) + +#define SHARED_GPR_DRAM_CLK 2 +#define SHARED_GPR_DRAM_CLK_SEL_PLL 0 +#define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0) + +static struct imx_fracn_gppll_rate_table imx9_fracpll_tbl[] = { + { .rate = 1000000000U, .rdiv = 1, .mfi = 166, .odiv = 4, .mfn = 2, .mfd = 3 }, /* 1000MHz */ + { .rate = 933000000U, .rdiv = 1, .mfi = 155, .odiv = 4, .mfn = 1, .mfd = 2 }, /* 933MHz */ + { .rate = 700000000U, .rdiv = 1, .mfi = 145, .odiv = 5, .mfn = 5, .mfd = 6 }, /* 700MHz */ + { .rate = 484000000U, .rdiv = 1, .mfi = 121, .odiv = 6, .mfn = 0, .mfd = 1 }, /* 480MHz */ + { .rate = 445333333U, .rdiv = 1, .mfi = 167, .odiv = 9, .mfn = 0, .mfd = 1 }, + { .rate = 466000000U, .rdiv = 1, .mfi = 155, .odiv = 8, .mfn = 1, .mfd = 3 }, /* 466MHz */ + { .rate = 400000000U, .rdiv = 1, .mfi = 200, .odiv = 12, .mfn = 0, .mfd = 1 }, /* 400MHz */ + { .rate = 300000000U, .rdiv = 1, .mfi = 150, .odiv = 12, .mfn = 0, .mfd = 1 }, +}; + +static int dram_pll_init(u32 freq) +{ + return fracn_gppll_set_rate(IOMEM(MX9_ANATOP_DRAM_PLL_BASE_ADDR), + CLK_FRACN_GPPLL_FRACN, imx9_fracpll_tbl, + ARRAY_SIZE(imx9_fracpll_tbl), freq); +} + +static void ccm_shared_gpr_set(u32 gpr, u32 val) +{ + writel(val, IOMEM(MX9_CCM_BASE_ADDR + 0x4800)); +} + +#define DRAM_ALT_CLK_ROOT 76 +#define DRAM_APB_CLK_ROOT 77 + +#define CLK_ROOT_MUX GENMASK(9, 8) +#define CLK_ROOT_DIV GENMASK(9, 0) + +static void ccm_clk_root_cfg(u32 clk_root_id, int mux, u32 div) +{ + void __iomem *base = IOMEM(MX9_CCM_BASE_ADDR) + clk_root_id * 0x80; + + writel(FIELD_PREP(CLK_ROOT_MUX, mux) | FIELD_PREP(CLK_ROOT_DIV, div - 1), base); +}; + +static void dram_enable_bypass(ulong clk_val) +{ + switch (clk_val) { + case MHZ(625): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, 3, 1); + break; + case MHZ(400): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, 2, 2); + break; + case MHZ(333): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, 1, 3); + break; + case MHZ(200): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, 2, 4); + break; + case MHZ(100): + ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, 2, 8); + break; + default: + printf("No matched freq table %lu\n", clk_val); + return; + } + + /* Set DRAM APB to 133Mhz */ + ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, 2, 3); + /* Switch from DRAM clock root from PLL to CCM */ + ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM); +} + +static void dram_disable_bypass(void) +{ + /* Set DRAM APB to 133Mhz */ + ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, 2, 3); + /* Switch from DRAM clock root from CCM to PLL */ + ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL); +} + +static void ddrphy_init_set_dfi_clk(struct dram_controller *dram, unsigned int drate_mhz) +{ + switch (drate_mhz) { + case 4000: + dram_pll_init(MHZ(1000)); + dram_disable_bypass(); + break; + case 3733: + case 3732: + dram_pll_init(MHZ(933)); + dram_disable_bypass(); + break; + case 3200: + dram_pll_init(MHZ(800)); + dram_disable_bypass(); + break; + case 3000: + dram_pll_init(MHZ(750)); + dram_disable_bypass(); + break; + case 2800: + dram_pll_init(MHZ(700)); + dram_disable_bypass(); + break; + case 2400: + dram_pll_init(MHZ(600)); + dram_disable_bypass(); + break; + case 1866: + dram_pll_init(MHZ(466)); + dram_disable_bypass(); + break; + case 1600: + dram_pll_init(MHZ(400)); + dram_disable_bypass(); + break; + case 1066: + dram_pll_init(MHZ(266)); + dram_disable_bypass(); + break; + case 667: + dram_pll_init(MHZ(167)); + dram_disable_bypass(); + break; + case 625: + dram_enable_bypass(MHZ(625)); + break; + case 400: + dram_enable_bypass(MHZ(400)); + break; + case 333: + dram_enable_bypass(MHZ(333)); + break; + case 200: + dram_enable_bypass(MHZ(200)); + break; + case 100: + dram_enable_bypass(MHZ(100)); + break; + default: + return; + } +} + +static u32 ddrphy_addr_remap(u32 paddr_apb_from_ctlr) +{ + u32 paddr_apb_qual; + u32 paddr_apb_unqual_dec_22_13; + u32 paddr_apb_unqual_dec_19_13; + u32 paddr_apb_unqual_dec_12_1; + u32 paddr_apb_unqual; + u32 paddr_apb_phy; + + paddr_apb_qual = (paddr_apb_from_ctlr << 1); + paddr_apb_unqual_dec_22_13 = ((paddr_apb_qual & 0x7fe000) >> 13); + paddr_apb_unqual_dec_12_1 = ((paddr_apb_qual & 0x1ffe) >> 1); + + switch (paddr_apb_unqual_dec_22_13) { + case 0x000 ... 0x00b: + paddr_apb_unqual_dec_19_13 = paddr_apb_unqual_dec_22_13; + break; + case 0x100 ... 0x10b: + paddr_apb_unqual_dec_19_13 = paddr_apb_unqual_dec_22_13 - 0x100 + 0xc; + break; + case 0x200 ... 0x20b: + paddr_apb_unqual_dec_19_13 = paddr_apb_unqual_dec_22_13 - 0x200 + 0x18; + break; + case 0x300 ... 0x30b: + paddr_apb_unqual_dec_19_13 = paddr_apb_unqual_dec_22_13 - 0x300 + 0x24; + break; + case 0x010 ... 0x019: + paddr_apb_unqual_dec_19_13 = paddr_apb_unqual_dec_22_13 - 0x10 + 0x30; + break; + case 0x110 ... 0x119: + paddr_apb_unqual_dec_19_13 = paddr_apb_unqual_dec_22_13 - 0x110 + 0x3a; + break; + case 0x210 ... 0x219: + paddr_apb_unqual_dec_19_13 = paddr_apb_unqual_dec_22_13 - 0x210 + 0x44; + break; + case 0x310 ... 0x319: + paddr_apb_unqual_dec_19_13 = paddr_apb_unqual_dec_22_13 - 0x310 + 0x4e; + break; + case 0x020: + paddr_apb_unqual_dec_19_13 = 0x58; + break; + case 0x120: + paddr_apb_unqual_dec_19_13 = 0x59; + break; + case 0x220: + paddr_apb_unqual_dec_19_13 = 0x5a; + break; + case 0x320: + paddr_apb_unqual_dec_19_13 = 0x5b; + break; + case 0x040: + paddr_apb_unqual_dec_19_13 = 0x5c; + break; + case 0x140: + paddr_apb_unqual_dec_19_13 = 0x5d; + break; + case 0x240: + paddr_apb_unqual_dec_19_13 = 0x5e; + break; + case 0x340: + paddr_apb_unqual_dec_19_13 = 0x5f; + break; + case 0x050: + paddr_apb_unqual_dec_19_13 = 0x60; + break; + case 0x051: + paddr_apb_unqual_dec_19_13 = 0x61; + break; + case 0x052: + paddr_apb_unqual_dec_19_13 = 0x62; + break; + case 0x053: + paddr_apb_unqual_dec_19_13 = 0x63; + break; + case 0x054: + paddr_apb_unqual_dec_19_13 = 0x64; + break; + case 0x055: + paddr_apb_unqual_dec_19_13 = 0x65; + break; + case 0x056: + paddr_apb_unqual_dec_19_13 = 0x66; + break; + case 0x057: + paddr_apb_unqual_dec_19_13 = 0x67; + break; + case 0x070: + paddr_apb_unqual_dec_19_13 = 0x68; + break; + case 0x090: + paddr_apb_unqual_dec_19_13 = 0x69; + break; + case 0x190: + paddr_apb_unqual_dec_19_13 = 0x6a; + break; + case 0x290: + paddr_apb_unqual_dec_19_13 = 0x6b; + break; + case 0x390: + paddr_apb_unqual_dec_19_13 = 0x6c; + break; + case 0x0c0: + paddr_apb_unqual_dec_19_13 = 0x6d; + break; + case 0x0d0: + paddr_apb_unqual_dec_19_13 = 0x6e; + break; + default: + paddr_apb_unqual_dec_19_13 = 0x00; + break; + } + + paddr_apb_unqual = (paddr_apb_unqual_dec_19_13 << 13) | (paddr_apb_unqual_dec_12_1 << 1); + + paddr_apb_phy = paddr_apb_unqual << 1; + + return paddr_apb_phy; +} + +struct dram_controller imx9_dram_controller = { + .phy_base = IOMEM(MX9_DDR_PHY_BASE), + .phy_remap = ddrphy_addr_remap, + .get_trained_CDD = get_trained_CDD, + .set_dfi_clk = ddrphy_init_set_dfi_clk, +}; + +int imx9_ddr_init(struct dram_timing_info *dram_timing, enum dram_type dram_type) +{ + unsigned int initial_drate; + struct dram_timing_info *saved_timing; + void *fsp; + int ret; + u32 mr12, mr14; + u32 regval; + struct dram_controller *dram = &imx9_dram_controller; + + debug("DDRINFO: start DRAM init\n"); + + dram->dram_type = dram_type; + + /* reset ddrphy */ + ddrphy_coldreset(); + + debug("DDRINFO: cfg clk\n"); + + initial_drate = dram_timing->fsp_msg[0].drate; + /* default to the frequency point 0 clock */ + ddrphy_init_set_dfi_clk(dram, initial_drate); + + /* + * Start PHY initialization and training by + * accessing relevant PUB registers + */ + debug("DDRINFO:ddrphy config start\n"); + + ret = ddr_cfg_phy(dram, dram_timing); + if (ret) + return ret; + + debug("DDRINFO: ddrphy config done\n"); + + update_umctl2_rank_space_setting(dram_timing, dram_timing->fsp_msg_num - 1); + + /* rogram the ddrc registers */ + debug("DDRINFO: ddrc config start\n"); + ddrc_config(dram_timing); + debug("DDRINFO: ddrc config done\n"); + + writel(0x200000, REG_DDR_DEBUG_19); + + check_dfi_init_complete(); + + regval = readl(REG_DDR_SDRAM_CFG); + writel((regval | 0x80000000), REG_DDR_SDRAM_CFG); + + check_ddrc_idle(); + + mr12 = lpddr4_mr_read(1, 12); + mr14 = lpddr4_mr_read(1, 14); + + /* save the dram timing config into memory */ + fsp = dram_config_save(dram, dram_timing, IMX9_SAVED_DRAM_TIMING_BASE); + + saved_timing = (struct dram_timing_info *)IMX9_SAVED_DRAM_TIMING_BASE; + saved_timing->fsp_cfg = fsp; + saved_timing->fsp_cfg_num = dram_timing->fsp_cfg_num; + if (saved_timing->fsp_cfg_num) { + memcpy(saved_timing->fsp_cfg, dram_timing->fsp_cfg, + dram_timing->fsp_cfg_num * sizeof(struct dram_fsp_cfg)); + + save_trained_mr12_14(saved_timing->fsp_cfg[0].mr_cfg, + ARRAY_SIZE(saved_timing->fsp_cfg[0].mr_cfg), mr12, mr14); + /* + * Configure mode registers in fsp1 to mode register 0 because DDRC + * doesn't automatically set. + */ + if (saved_timing->fsp_cfg_num > 1) + update_mr_fsp_op0(saved_timing->fsp_cfg[1].mr_cfg, + ARRAY_SIZE(saved_timing->fsp_cfg[1].mr_cfg)); + } + + return 0; +} diff --git a/drivers/ddr/imx8m/Kconfig b/drivers/ddr/imx8m/Kconfig deleted file mode 100644 index e8bce8c49d..0000000000 --- a/drivers/ddr/imx8m/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -menu "i.MX8M DDR controllers" - depends on ARCH_IMX8MQ || ARCH_IMX8MM - -config IMX8M_DRAM - bool "imx8m dram controller support" - -endmenu diff --git a/drivers/ddr/imx8m/Makefile b/drivers/ddr/imx8m/Makefile deleted file mode 100644 index 2be313900f..0000000000 --- a/drivers/ddr/imx8m/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2018 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -pbl-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o ddr_init.o diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c deleted file mode 100644 index 374601b786..0000000000 --- a/drivers/ddr/imx8m/ddr_init.c +++ /dev/null @@ -1,211 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018-2019 NXP - */ -#define DEBUG -#include <common.h> -#include <errno.h> -#include <io.h> -#include <soc/imx8m/ddr.h> -#include <mach/generic.h> -#include <mach/imx8m-regs.h> -#include <mach/imx8m-ccm-regs.h> - -#define SRC_DDRC_RCR_ADDR MX8MQ_SRC_DDRC_RCR_ADDR - -static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) -{ - int i = 0; - - for (i = 0; i < num; i++) { - reg32_write((unsigned long)ddrc_cfg->reg, ddrc_cfg->val); - ddrc_cfg++; - } -} - -static int imx8m_ddr_init(unsigned long src_ddrc_rcr, - struct dram_timing_info *dram_timing) -{ - unsigned int tmp, initial_drate, target_freq; - int ret; - - debug("DDRINFO: start DRAM init\n"); - - debug("DDRINFO: cfg clk\n"); - - /* disable iso */ - reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ - reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ - - initial_drate = dram_timing->fsp_msg[0].drate; - /* default to the frequency point 0 clock */ - ddrphy_init_set_dfi_clk(initial_drate); - - /* D-aasert the presetn */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); - - /* Step2: Program the dwc_ddr_umctl2 registers */ - debug("DDRINFO: ddrc config start\n"); - ddr_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); - debug("DDRINFO: ddrc config done\n"); - - /* Step3: De-assert reset signal(core_ddrc_rstn & aresetn_n) */ - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); - - /* - * Step4: Disable auto-refreshes, self-refresh, powerdown, and - * assertion of dfi_dram_clk_disable by setting RFSHCTL3.dis_auto_refresh = 1, - * PWRCTL.powerdown_en = 0, and PWRCTL.selfref_en = 0, - * PWRCTL.en_dfi_dram_clk_disable = 0 - */ - reg32_write(DDRC_DBG1(0), 0x00000000); - reg32_write(DDRC_RFSHCTL3(0), 0x0000001); - reg32_write(DDRC_PWRCTL(0), 0xa0); - - /* if ddr type is LPDDR4, do it */ - tmp = reg32_read(DDRC_MSTR(0)); - if (tmp & (0x1 << 5)) - reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ - - /* determine the initial boot frequency */ - target_freq = reg32_read(DDRC_MSTR2(0)) & 0x3; - target_freq = (tmp & (0x1 << 29)) ? target_freq : 0x0; - - /* Step5: Set SWCT.sw_done to 0 */ - reg32_write(DDRC_SWCTL(0), 0x00000000); - - /* Set the default boot frequency point */ - clrsetbits_le32(DDRC_DFIMISC(0), (0x1f << 8), target_freq << 8); - /* Step6: Set DFIMISC.dfi_init_complete_en to 0 */ - clrbits_le32(DDRC_DFIMISC(0), 0x1); - - /* Step7: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */ - reg32_write(DDRC_SWCTL(0), 0x00000001); - do { - tmp = reg32_read(DDRC_SWSTAT(0)); - } while ((tmp & 0x1) == 0x0); - - /* - * Step8 ~ Step13: Start PHY initialization and training by - * accessing relevant PUB registers - */ - debug("DDRINFO:ddrphy config start\n"); - - ret = ddr_cfg_phy(dram_timing); - if (ret) - return ret; - - debug("DDRINFO: ddrphy config done\n"); - - /* - * step14 CalBusy.0 =1, indicates the calibrator is actively - * calibrating. Wait Calibrating done. - */ - do { - tmp = reg32_read(DDRPHY_CalBusy(0)); - } while ((tmp & 0x1)); - - debug("DDRINFO:ddrphy calibration done\n"); - - /* Step15: Set SWCTL.sw_done to 0 */ - reg32_write(DDRC_SWCTL(0), 0x00000000); - - /* Step16: Set DFIMISC.dfi_init_start to 1 */ - setbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); - - /* Step17: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */ - reg32_write(DDRC_SWCTL(0), 0x00000001); - do { - tmp = reg32_read(DDRC_SWSTAT(0)); - } while ((tmp & 0x1) == 0x0); - - /* Step18: Polling DFISTAT.dfi_init_complete = 1 */ - do { - tmp = reg32_read(DDRC_DFISTAT(0)); - } while ((tmp & 0x1) == 0x0); - - /* Step19: Set SWCTL.sw_done to 0 */ - reg32_write(DDRC_SWCTL(0), 0x00000000); - - /* Step20: Set DFIMISC.dfi_init_start to 0 */ - clrbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); - - /* Step21: optional */ - - /* Step22: Set DFIMISC.dfi_init_complete_en to 1 */ - setbits_le32(DDRC_DFIMISC(0), 0x1); - - /* Step23: Set PWRCTL.selfref_sw to 0 */ - clrbits_le32(DDRC_PWRCTL(0), (0x1 << 5)); - - /* Step24: Set SWCTL.sw_done to 1; need polling SWSTAT.sw_done_ack */ - reg32_write(DDRC_SWCTL(0), 0x00000001); - do { - tmp = reg32_read(DDRC_SWSTAT(0)); - } while ((tmp & 0x1) == 0x0); - - /* Step25: Wait for dwc_ddr_umctl2 to move to normal operating mode by monitoring - * STAT.operating_mode signal */ - do { - tmp = reg32_read(DDRC_STAT(0)); - } while ((tmp & 0x3) != 0x1); - - /* Step26: Set back register in Step4 to the original values if desired */ - reg32_write(DDRC_RFSHCTL3(0), 0x0000000); - /* enable selfref_en by default */ - setbits_le32(DDRC_PWRCTL(0), 0x1 << 3); - - /* enable port 0 */ - reg32_write(DDRC_PCTRL_0(0), 0x00000001); - debug("DDRINFO: ddrmix config done\n"); - - return 0; -} - -/* - * We store the timing parameters here. the TF-A will pick these up. - * Note that the timing used we leave the driver with is a PLL bypass 25MHz - * mode. So if your board runs horribly slow you'll likely have to provide a - * TF-A binary. - */ -#define IMX8M_SAVED_DRAM_TIMING_BASE 0x180000 - -int imx8mm_ddr_init(struct dram_timing_info *dram_timing) -{ - unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR; - int ret; - - /* Step1: Follow the power up procedure */ - reg32_write(src_ddrc_rcr, 0x8f00001f); - reg32_write(src_ddrc_rcr, 0x8f00000f); - - ret = imx8m_ddr_init(src_ddrc_rcr, dram_timing); - if (ret) - return ret; - - /* save the dram timing config into memory */ - dram_config_save(dram_timing, IMX8M_SAVED_DRAM_TIMING_BASE); - - return 0; -} - -int imx8mq_ddr_init(struct dram_timing_info *dram_timing) -{ - unsigned long src_ddrc_rcr = MX8MQ_SRC_DDRC_RCR_ADDR; - int ret; - - /* Step1: Follow the power up procedure */ - reg32_write(src_ddrc_rcr + 0x04, 0x8f00000f); - reg32_write(src_ddrc_rcr, 0x8f00000f); - reg32_write(src_ddrc_rcr + 0x04, 0x8f000000); - - ret = imx8m_ddr_init(src_ddrc_rcr, dram_timing); - if (ret) - return ret; - - /* save the dram timing config into memory */ - dram_config_save(dram_timing, IMX8M_SAVED_DRAM_TIMING_BASE); - - return 0; -} diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c deleted file mode 100644 index c2238cc66b..0000000000 --- a/drivers/ddr/imx8m/ddrphy_train.c +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ -#define DEBUG -#include <common.h> -#include <linux/kernel.h> -#include <soc/imx8m/ddr.h> -#include <firmware.h> -#include <mach/imx8m-regs.h> - -void ddr_load_train_code(enum fw_type type) -{ - const u16 *imem, *dmem; - size_t isize, dsize; - - if (type == FW_1D_IMAGE) { - get_builtin_firmware(lpddr4_pmu_train_1d_imem_bin, &imem, &isize); - get_builtin_firmware(lpddr4_pmu_train_1d_dmem_bin, &dmem, &dsize); - } else { - get_builtin_firmware(lpddr4_pmu_train_2d_imem_bin, &imem, &isize); - get_builtin_firmware(lpddr4_pmu_train_2d_dmem_bin, &dmem, &dsize); - } - - ddrc_phy_load_firmware(IOMEM(MX8M_DDRC_PHY_BASE_ADDR), - DDRC_PHY_IMEM, imem, isize); - - ddrc_phy_load_firmware(IOMEM(MX8M_DDRC_PHY_BASE_ADDR), - DDRC_PHY_DMEM, dmem, dsize); -} - -int ddr_cfg_phy(struct dram_timing_info *dram_timing) -{ - struct dram_cfg_param *dram_cfg; - struct dram_fsp_msg *fsp_msg; - unsigned int num; - int i = 0; - int j = 0; - int ret; - - /* initialize PHY configuration */ - dram_cfg = dram_timing->ddrphy_cfg; - num = dram_timing->ddrphy_cfg_num; - for (i = 0; i < num; i++) { - /* config phy reg */ - dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); - dram_cfg++; - } - - /* load the frequency setpoint message block config */ - fsp_msg = dram_timing->fsp_msg; - for (i = 0; i < dram_timing->fsp_msg_num; i++) { - debug("DRAM PHY training for %dMTS\n", fsp_msg->drate); - /* set dram PHY input clocks to desired frequency */ - ddrphy_init_set_dfi_clk(fsp_msg->drate); - - /* load the dram training firmware image */ - dwc_ddrphy_apb_wr(0xd0000, 0x0); - ddr_load_train_code(fsp_msg->fw_type); - - /* load the frequency set point message block parameter */ - dram_cfg = fsp_msg->fsp_cfg; - num = fsp_msg->fsp_cfg_num; - for (j = 0; j < num; j++) { - dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); - dram_cfg++; - } - - /* - * -------------------- excute the firmware -------------------- - * Running the firmware is a simply process to taking the - * PMU out of reset and stall, then the firwmare will be run - * 1. reset the PMU; - * 2. begin the excution; - * 3. wait for the training done; - * 4. read the message block result. - * ------------------------------------------------------------- - */ - dwc_ddrphy_apb_wr(0xd0000, 0x1); - dwc_ddrphy_apb_wr(0xd0099, 0x9); - dwc_ddrphy_apb_wr(0xd0099, 0x1); - dwc_ddrphy_apb_wr(0xd0099, 0x0); - - /* Wait for the training firmware to complete */ - ret = wait_ddrphy_training_complete(); - if (ret) - return ret; - - /* Halt the microcontroller. */ - dwc_ddrphy_apb_wr(0xd0099, 0x1); - - /* Read the Message Block results */ - dwc_ddrphy_apb_wr(0xd0000, 0x0); - ddrphy_init_read_msg_block(fsp_msg->fw_type); - dwc_ddrphy_apb_wr(0xd0000, 0x1); - - fsp_msg++; - } - - /* Load PHY Init Engine Image */ - dram_cfg = dram_timing->ddrphy_pie; - num = dram_timing->ddrphy_pie_num; - for (i = 0; i < num; i++) { - dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); - dram_cfg++; - } - - /* save the ddr PHY trained CSR in memory for low power use */ - ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num); - - return 0; -} diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c deleted file mode 100644 index 651bb4b698..0000000000 --- a/drivers/ddr/imx8m/ddrphy_utils.c +++ /dev/null @@ -1,306 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* -* Copyright 2018 NXP -*/ - -#include <common.h> -#include <errno.h> -#include <io.h> -#include <linux/iopoll.h> -#include <soc/imx8m/ddr.h> -#include <mach/imx8m-regs.h> -#include <mach/imx8m-ccm-regs.h> - -void ddrc_phy_load_firmware(void __iomem *phy, - enum ddrc_phy_firmware_offset offset, - const u16 *blob, size_t size) -{ - while (size) { - writew(*blob++, phy + DDRC_PHY_REG(offset)); - offset++; - size -= sizeof(*blob); - } -} - -enum pmc_constants { - PMC_MESSAGE_ID, - PMC_MESSAGE_STREAM, - - PMC_TRAIN_SUCCESS = 0x07, - PMC_TRAIN_STREAM_START = 0x08, - PMC_TRAIN_FAIL = 0xff, -}; - -static u32 ddrc_phy_get_message(void __iomem *phy, int type) -{ - u32 r, message; - - /* - * When BIT0 set to 0, the PMU has a message for the user - * Wait for it indefinitely. - */ - readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004), - r, !(r & BIT(0)), 0); - - switch (type) { - case PMC_MESSAGE_ID: - /* - * Get the major message ID - */ - message = readl(phy + DDRC_PHY_REG(0xd0032)); - break; - case PMC_MESSAGE_STREAM: - message = readl(phy + DDRC_PHY_REG(0xd0034)); - message <<= 16; - message |= readl(phy + DDRC_PHY_REG(0xd0032)); - break; - } - - /* - * By setting this register to 0, the user acknowledges the - * receipt of the message. - */ - writel(0x00000000, phy + DDRC_PHY_REG(0xd0031)); - /* - * When BIT0 set to 0, the PMU has a message for the user - */ - readl_poll_timeout(phy + DDRC_PHY_REG(0xd0004), - r, r & BIT(0), 0); - - writel(0x00000001, phy + DDRC_PHY_REG(0xd0031)); - - return message; -} - -static void ddrc_phy_fetch_streaming_message(void __iomem *phy) -{ - const u16 index = ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM); - u16 i; - - for (i = 0; i < index; i++) - ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM); -} - -int wait_ddrphy_training_complete(void) -{ - void __iomem *phy = IOMEM(MX8M_DDRC_PHY_BASE_ADDR); - - for (;;) { - const u32 m = ddrc_phy_get_message(phy, PMC_MESSAGE_ID); - - switch (m) { - case PMC_TRAIN_STREAM_START: - ddrc_phy_fetch_streaming_message(phy); - break; - case PMC_TRAIN_SUCCESS: - return 0; - case PMC_TRAIN_FAIL: - hang(); - } - } -} - -struct dram_bypass_clk_setting { - ulong clk; - int alt_root_sel; - int alt_pre_div; - int apb_root_sel; - int apb_pre_div; -}; - -#define MHZ(x) (1000000UL * (x)) - -static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = { - { - .clk = MHZ(100), - .alt_root_sel = 2, - .alt_pre_div = 1 - 1, - .apb_root_sel = 2, - .apb_pre_div = 2 - 1, - } , { - .clk = MHZ(250), - .alt_root_sel = 3, - .alt_pre_div = 2 - 1, - .apb_root_sel = 2, - .apb_pre_div = 2 - 1, - }, { - .clk = MHZ(400), - .alt_root_sel = 1, - .alt_pre_div = 2 - 1, - .apb_root_sel = 3, - .apb_pre_div = 2 - 1, - }, -}; - -static void dram_enable_bypass(ulong clk_val) -{ - int i; - struct dram_bypass_clk_setting *config; - - for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) { - if (clk_val == imx8mq_dram_bypass_tbl[i].clk) - break; - } - - if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) { - printf("No matched freq table %lu\n", clk_val); - return; - } - - config = &imx8mq_dram_bypass_tbl[i]; - - imx8m_clock_set_target_val(IMX8M_DRAM_ALT_CLK_ROOT, - IMX8M_CCM_TARGET_ROOTn_ENABLE | - IMX8M_CCM_TARGET_ROOTn_MUX(config->alt_root_sel) | - IMX8M_CCM_TARGET_ROOTn_PRE_DIV(config->alt_pre_div)); - imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT, - IMX8M_CCM_TARGET_ROOTn_ENABLE | - IMX8M_CCM_TARGET_ROOTn_MUX(config->apb_root_sel) | - IMX8M_CCM_TARGET_ROOTn_PRE_DIV(config->apb_pre_div)); - imx8m_clock_set_target_val(IMX8M_DRAM_SEL_CFG, IMX8M_CCM_TARGET_ROOTn_ENABLE | - IMX8M_CCM_TARGET_ROOTn_MUX(1)); -} - -static void dram_disable_bypass(void) -{ - imx8m_clock_set_target_val(IMX8M_DRAM_SEL_CFG, - IMX8M_CCM_TARGET_ROOTn_ENABLE | - IMX8M_CCM_TARGET_ROOTn_MUX(0)); - imx8m_clock_set_target_val(IMX8M_DRAM_APB_CLK_ROOT, - IMX8M_CCM_TARGET_ROOTn_ENABLE | - IMX8M_CCM_TARGET_ROOTn_MUX(4) | - IMX8M_CCM_TARGET_ROOTn_PRE_DIV(5 - 1)); -} - -struct imx_int_pll_rate_table { - u32 rate; - u32 r1; - u32 r2; -}; - -#define MDIV(x) ((x) << 12) -#define PDIV(x) ((x) << 4) -#define SDIV(x) ((x) << 0) - -#define LOCK_STATUS BIT(31) -#define LOCK_SEL_MASK BIT(29) -#define CLKE_MASK BIT(11) -#define RST_MASK BIT(9) -#define BYPASS_MASK BIT(4) - -static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { - { .rate = 1000000000U, .r1 = MDIV(250) | PDIV(3) | SDIV(1), .r2 = 0 }, - { .rate = 800000000U, .r1 = MDIV(300) | PDIV(9) | SDIV(0), .r2 = 0 }, - { .rate = 750000000U, .r1 = MDIV(250) | PDIV(8) | SDIV(0), .r2 = 0 }, - { .rate = 650000000U, .r1 = MDIV(325) | PDIV(3) | SDIV(2), .r2 = 0 }, - { .rate = 600000000U, .r1 = MDIV(300) | PDIV(3) | SDIV(2), .r2 = 0 }, - { .rate = 594000000U, .r1 = MDIV( 99) | PDIV(1) | SDIV(2), .r2 = 0 }, - { .rate = 400000000U, .r1 = MDIV(300) | PDIV(9) | SDIV(1), .r2 = 0 }, - { .rate = 266666667U, .r1 = MDIV(400) | PDIV(9) | SDIV(2), .r2 = 0 }, - { .rate = 167000000U, .r1 = MDIV(334) | PDIV(3) | SDIV(4), .r2 = 0 }, - { .rate = 100000000U, .r1 = MDIV(300) | PDIV(9) | SDIV(3), .r2 = 0 }, -}; - -static struct imx_int_pll_rate_table *fracpll(u32 freq) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) - if (freq == imx8mm_fracpll_tbl[i].rate) - return &imx8mm_fracpll_tbl[i]; - - return NULL; -} - -static int dram_pll_init(u32 freq) -{ - volatile int i; - u32 tmp; - void *pll_base; - struct imx_int_pll_rate_table *rate; - - rate = fracpll(freq); - if (!rate) { - printf("No matched freq table %u\n", freq); - return -EINVAL; - } - - setbits_le32(MX8M_GPC_BASE_ADDR + 0xec, 1 << 7); - setbits_le32(MX8M_GPC_BASE_ADDR + 0xf8, 1 << 5); - writel(0x8F000000UL, MX8M_SRC_BASE_ADDR + 0x1004); - - pll_base = IOMEM(MX8M_ANATOP_BASE_ADDR) + 0x50; - - /* Bypass clock and set lock to pll output lock */ - tmp = readl(pll_base); - tmp |= BYPASS_MASK; - writel(tmp, pll_base); - - /* Enable RST */ - tmp &= ~RST_MASK; - writel(tmp, pll_base); - - writel(rate->r1, pll_base + 4); - writel(rate->r2, pll_base + 8); - - for (i = 0; i < 1000; i++); - - /* Disable RST */ - tmp |= RST_MASK; - writel(tmp, pll_base); - - /* Wait Lock*/ - while (!(readl(pll_base) & LOCK_STATUS)); - - /* Bypass */ - tmp &= ~BYPASS_MASK; - writel(tmp, pll_base); - - return 0; -} - -void ddrphy_init_set_dfi_clk(unsigned int drate) -{ - switch (drate) { - case 4000: - dram_pll_init(MHZ(1000)); - dram_disable_bypass(); - break; - case 3200: - dram_pll_init(MHZ(800)); - dram_disable_bypass(); - break; - case 3000: - dram_pll_init(MHZ(750)); - dram_disable_bypass(); - break; - case 2400: - dram_pll_init(MHZ(600)); - dram_disable_bypass(); - break; - case 1600: - dram_pll_init(MHZ(400)); - dram_disable_bypass(); - break; - case 1066: - dram_pll_init(MHZ(266)); - dram_disable_bypass(); - break; - case 667: - dram_pll_init(MHZ(167)); - dram_disable_bypass(); - break; - case 400: - dram_enable_bypass(MHZ(400)); - break; - case 100: - dram_enable_bypass(MHZ(100)); - break; - default: - return; - } -} - -void ddrphy_init_read_msg_block(enum fw_type type) -{ -} |