diff options
Diffstat (limited to 'drivers/net/phy/dp83867.c')
| -rw-r--r-- | drivers/net/phy/dp83867.c | 49 |
1 files changed, 23 insertions, 26 deletions
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 8a14927071..e796498c4a 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -213,33 +213,7 @@ static int dp83867_config_init(struct phy_device *phydev) ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); if (ret) return ret; - } else if (phy_interface_is_sgmii(phydev)) { - phy_write(phydev, MII_BMCR, - BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000); - - cfg2 = phy_read(phydev, MII_DP83867_CFG2); - cfg2 &= MII_DP83867_CFG2_MASK; - cfg2 |= MII_DP83867_CFG2_SPEEDOPT_10EN | - MII_DP83867_CFG2_SGMII_AUTONEGEN | - MII_DP83867_CFG2_SPEEDOPT_ENH | - MII_DP83867_CFG2_SPEEDOPT_CNT | - MII_DP83867_CFG2_SPEEDOPT_INTLOW; - - phy_write(phydev, MII_DP83867_CFG2, cfg2); - - phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, - DP83867_DEVADDR, 0x0); - - val = DP83867_PHYCTRL_SGMIIEN | - DP83867_MDI_CROSSOVER_MDIX << DP83867_MDI_CROSSOVER | - dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT | - dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT; - - phy_write(phydev, MII_DP83867_PHYCTRL, val); - phy_write(phydev, MII_DP83867_BISCR, 0x0); - } - if (phy_interface_is_rgmii(phydev)) { val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, DP83867_DEVADDR); @@ -276,6 +250,29 @@ static int dp83867_config_init(struct phy_device *phydev) phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG, DP83867_DEVADDR, val); } + } else if (phy_interface_is_sgmii(phydev)) { + phy_write(phydev, MII_BMCR, + BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000); + + cfg2 = phy_read(phydev, MII_DP83867_CFG2); + cfg2 &= MII_DP83867_CFG2_MASK; + cfg2 |= MII_DP83867_CFG2_SPEEDOPT_10EN | + MII_DP83867_CFG2_SGMII_AUTONEGEN | + MII_DP83867_CFG2_SPEEDOPT_ENH | + MII_DP83867_CFG2_SPEEDOPT_CNT | + MII_DP83867_CFG2_SPEEDOPT_INTLOW; + phy_write(phydev, MII_DP83867_CFG2, cfg2); + + phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, 0x0); + + val = DP83867_PHYCTRL_SGMIIEN | + DP83867_MDI_CROSSOVER_MDIX << DP83867_MDI_CROSSOVER | + dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT | + dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT; + + phy_write(phydev, MII_DP83867_PHYCTRL, val); + phy_write(phydev, MII_DP83867_BISCR, 0x0); } if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) |