diff options
Diffstat (limited to 'dts/Bindings/arm/mediatek')
21 files changed, 618 insertions, 242 deletions
diff --git a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt deleted file mode 100644 index 3fa7558665..0000000000 --- a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt +++ /dev/null @@ -1,35 +0,0 @@ -Mediatek apmixedsys controller -============================== - -The Mediatek apmixedsys controller provides the PLLs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-apmixedsys" - - "mediatek,mt2712-apmixedsys", "syscon" - - "mediatek,mt6765-apmixedsys", "syscon" - - "mediatek,mt6779-apmixedsys", "syscon" - - "mediatek,mt6797-apmixedsys" - - "mediatek,mt7622-apmixedsys" - - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" - - "mediatek,mt7629-apmixedsys" - - "mediatek,mt7986-apmixedsys" - - "mediatek,mt8135-apmixedsys" - - "mediatek,mt8167-apmixedsys", "syscon" - - "mediatek,mt8173-apmixedsys" - - "mediatek,mt8183-apmixedsys", "syscon" - - "mediatek,mt8516-apmixedsys" -- #clock-cells: Must be 1 - -The apmixedsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -apmixedsys: clock-controller@10209000 { - compatible = "mediatek,mt8173-apmixedsys"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/dts/Bindings/arm/mediatek/mediatek,audsys.txt b/dts/Bindings/arm/mediatek/mediatek,audsys.txt deleted file mode 100644 index 699776be1d..0000000000 --- a/dts/Bindings/arm/mediatek/mediatek,audsys.txt +++ /dev/null @@ -1,39 +0,0 @@ -MediaTek AUDSYS controller -============================ - -The MediaTek AUDSYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-audsys", "syscon" - - "mediatek,mt6765-audsys", "syscon" - - "mediatek,mt6779-audio", "syscon" - - "mediatek,mt7622-audsys", "syscon" - - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" - - "mediatek,mt8167-audiosys", "syscon" - - "mediatek,mt8183-audiosys", "syscon" - - "mediatek,mt8192-audsys", "syscon" - - "mediatek,mt8516-audsys", "syscon" -- #clock-cells: Must be 1 - -The AUDSYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Required sub-nodes: -------- -For common binding part and usage, refer to -../sonud/mt2701-afe-pcm.txt. - -Example: - - audsys: clock-controller@11220000 { - compatible = "mediatek,mt7622-audsys", "syscon"; - reg = <0 0x11220000 0 0x2000>; - #clock-cells = <1>; - - afe: audio-controller { - ... - }; - }; diff --git a/dts/Bindings/arm/mediatek/mediatek,audsys.yaml b/dts/Bindings/arm/mediatek/mediatek,audsys.yaml new file mode 100644 index 0000000000..45d4a66200 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,audsys.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek AUDSYS controller + +maintainers: + - Eugen Hristev <eugen.hristev@collabora.com> + +description: + The MediaTek AUDSYS controller provides various clocks to the system. + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-audsys + - mediatek,mt6765-audsys + - mediatek,mt6779-audsys + - mediatek,mt7622-audsys + - mediatek,mt8167-audsys + - mediatek,mt8173-audsys + - mediatek,mt8183-audsys + - mediatek,mt8186-audsys + - mediatek,mt8192-audsys + - mediatek,mt8516-audsys + - const: syscon + - items: + # Special case for mt7623 for backward compatibility + - const: mediatek,mt7623-audsys + - const: mediatek,mt2701-audsys + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + audio-controller: + $ref: /schemas/sound/mediatek,mt2701-audio.yaml# + type: object + +required: + - compatible + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mt2701-power.h> + #include <dt-bindings/clock/mt2701-clk.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + audsys: clock-controller@11220000 { + compatible = "mediatek,mt7622-audsys", "syscon"; + reg = <0 0x11220000 0 0x2000>; + #clock-cells = <1>; + + afe: audio-controller { + compatible = "mediatek,mt2701-audio"; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "afe", "asys"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_48K_TIMING>, + <&topckgen CLK_TOP_AUD_44K_TIMING>, + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, + <&topckgen CLK_TOP_AUD_I2S1_MCLK>, + <&topckgen CLK_TOP_AUD_I2S2_MCLK>, + <&topckgen CLK_TOP_AUD_I2S3_MCLK>, + <&topckgen CLK_TOP_AUD_I2S4_MCLK>, + <&audsys CLK_AUD_I2SO1>, + <&audsys CLK_AUD_I2SO2>, + <&audsys CLK_AUD_I2SO3>, + <&audsys CLK_AUD_I2SO4>, + <&audsys CLK_AUD_I2SIN1>, + <&audsys CLK_AUD_I2SIN2>, + <&audsys CLK_AUD_I2SIN3>, + <&audsys CLK_AUD_I2SIN4>, + <&audsys CLK_AUD_ASRCO1>, + <&audsys CLK_AUD_ASRCO2>, + <&audsys CLK_AUD_ASRCO3>, + <&audsys CLK_AUD_ASRCO4>, + <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_AFE_CONN>, + <&audsys CLK_AUD_A1SYS>, + <&audsys CLK_AUD_A2SYS>, + <&audsys CLK_AUD_AFE_MRGIF>; + + clock-names = "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_a1sys_hp", + "top_audio_a2sys_hp", + "i2s0_src_sel", + "i2s1_src_sel", + "i2s2_src_sel", + "i2s3_src_sel", + "i2s0_src_div", + "i2s1_src_div", + "i2s2_src_div", + "i2s3_src_div", + "i2s0_mclk_en", + "i2s1_mclk_en", + "i2s2_mclk_en", + "i2s3_mclk_en", + "i2so0_hop_ck", + "i2so1_hop_ck", + "i2so2_hop_ck", + "i2so3_hop_ck", + "i2si0_hop_ck", + "i2si1_hop_ck", + "i2si2_hop_ck", + "i2si3_hop_ck", + "asrc0_out_ck", + "asrc1_out_ck", + "asrc2_out_ck", + "asrc3_out_ck", + "audio_afe_pd", + "audio_afe_conn_pd", + "audio_a1sys_pd", + "audio_a2sys_pd", + "audio_mrgif_pd"; + + assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_MUX1_DIV>, + <&topckgen CLK_TOP_AUD_MUX2_DIV>; + assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, + <&topckgen CLK_TOP_AUD2PLL_90M>; + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; + }; + }; + }; diff --git a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt b/dts/Bindings/arm/mediatek/mediatek,ethsys.txt deleted file mode 100644 index 0502db7368..0000000000 --- a/dts/Bindings/arm/mediatek/mediatek,ethsys.txt +++ /dev/null @@ -1,28 +0,0 @@ -Mediatek ethsys controller -============================ - -The Mediatek ethsys controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2701-ethsys", "syscon" - - "mediatek,mt7622-ethsys", "syscon" - - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" - - "mediatek,mt7629-ethsys", "syscon" - - "mediatek,mt7986-ethsys", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The ethsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -ethsys: clock-controller@1b000000 { - compatible = "mediatek,mt2701-ethsys", "syscon"; - reg = <0 0x1b000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt deleted file mode 100644 index f66bd72057..0000000000 --- a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt +++ /dev/null @@ -1,42 +0,0 @@ -Mediatek infracfg controller -============================ - -The Mediatek infracfg controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt2712-infracfg", "syscon" - - "mediatek,mt6765-infracfg", "syscon" - - "mediatek,mt6779-infracfg_ao", "syscon" - - "mediatek,mt6797-infracfg", "syscon" - - "mediatek,mt7622-infracfg", "syscon" - - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt7629-infracfg", "syscon" - - "mediatek,mt7986-infracfg", "syscon" - - "mediatek,mt8135-infracfg", "syscon" - - "mediatek,mt8167-infracfg", "syscon" - - "mediatek,mt8173-infracfg", "syscon" - - "mediatek,mt8183-infracfg", "syscon" - - "mediatek,mt8516-infracfg", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The infracfg controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. -Also it uses the common reset controller binding from -Documentation/devicetree/bindings/reset/reset.txt. -The available reset outputs are defined in -dt-bindings/reset/mt*-resets.h - -Example: - -infracfg: power-controller@10001000 { - compatible = "mediatek,mt8173-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/dts/Bindings/arm/mediatek/mediatek,infracfg.yaml b/dts/Bindings/arm/mediatek/mediatek,infracfg.yaml new file mode 100644 index 0000000000..230b5188a8 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,infracfg.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Infrastructure System Configuration Controller + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +description: + The Mediatek infracfg controller provides various clocks and reset outputs + to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>, + and reset values in <dt-bindings/reset/mt*-reset.h> and + <dt-bindings/reset/mt*-resets.h>. + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-infracfg + - mediatek,mt2712-infracfg + - mediatek,mt6765-infracfg + - mediatek,mt6795-infracfg + - mediatek,mt6779-infracfg_ao + - mediatek,mt6797-infracfg + - mediatek,mt7622-infracfg + - mediatek,mt7629-infracfg + - mediatek,mt7981-infracfg + - mediatek,mt7986-infracfg + - mediatek,mt7988-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8167-infracfg + - mediatek,mt8173-infracfg + - mediatek,mt8183-infracfg + - mediatek,mt8516-infracfg + - const: syscon + - items: + - const: mediatek,mt7623-infracfg + - const: mediatek,mt2701-infracfg + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-infracfg + - mediatek,mt2712-infracfg + - mediatek,mt6795-infracfg + - mediatek,mt7622-infracfg + - mediatek,mt7986-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8173-infracfg + - mediatek,mt8183-infracfg +then: + required: + - '#reset-cells' + +additionalProperties: false + +examples: + - | + infracfg: clock-controller@10001000 { + compatible = "mediatek,mt8173-infracfg", "syscon"; + reg = <0x10001000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/dts/Bindings/arm/mediatek/mediatek,mipi0a.txt b/dts/Bindings/arm/mediatek/mediatek,mipi0a.txt index 8be5978f38..1c671943ce 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mipi0a.txt +++ b/dts/Bindings/arm/mediatek/mediatek,mipi0a.txt @@ -16,7 +16,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h. The mipi0a controller also uses the common power domain from Documentation/devicetree/bindings/soc/mediatek/scpsys.txt -The available power doamins are defined in dt-bindings/power/mt*-power.h. +The available power domains are defined in dt-bindings/power/mt*-power.h. Example: diff --git a/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml b/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml index b31d90dc9e..b3c6888c14 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek mmsys controller @@ -25,22 +25,68 @@ properties: - mediatek,mt2712-mmsys - mediatek,mt6765-mmsys - mediatek,mt6779-mmsys + - mediatek,mt6795-mmsys - mediatek,mt6797-mmsys - mediatek,mt8167-mmsys - mediatek,mt8173-mmsys - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys + - mediatek,mt8188-vdosys0 + - mediatek,mt8188-vdosys1 + - mediatek,mt8188-vppsys0 + - mediatek,mt8188-vppsys1 - mediatek,mt8192-mmsys + - mediatek,mt8195-vdosys1 + - mediatek,mt8195-vppsys0 + - mediatek,mt8195-vppsys1 - mediatek,mt8365-mmsys - const: syscon + + - description: vdosys0 and vdosys1 are 2 display HW pipelines, + so mt8195 binding should be deprecated. + deprecated: true + items: + - const: mediatek,mt8195-mmsys + - const: syscon + - items: - const: mediatek,mt7623-mmsys - const: mediatek,mt2701-mmsys - const: syscon + - items: + - const: mediatek,mt8195-vdosys0 + - const: mediatek,mt8195-mmsys + - const: syscon + reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier as defined by bindings + of the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + + mboxes: + description: + Using mailbox to communicate with GCE, it should have this + property and list of phandle, mailbox specifiers. See + Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml + for details. + $ref: /schemas/types.yaml#/definitions/phandle-array + + mediatek,gce-client-reg: + description: + The register of client driver can be configured by gce with 4 arguments + defined in this property, such as phandle of gce, subsys id, + register offset and size. + Each subsys id is mapping to a base address of display function blocks + register which is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + "#clock-cells": const: 1 @@ -56,9 +102,16 @@ additionalProperties: false examples: - | + #include <dt-bindings/power/mt8173-power.h> + #include <dt-bindings/gce/mt8173-gce.h> + mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0x14000000 0x1000>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; #clock-cells = <1>; #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; diff --git a/dts/Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml b/dts/Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml new file mode 100644 index 0000000000..d89848a8f4 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIE Mirror Controller for MT7622 + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + - Felix Fietkau <nbd@nbd.name> + +description: + The mediatek PCIE mirror provides a configuration interface for PCIE + controller on MT7622 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7622-pcie-mirror + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_mirror: pcie-mirror@10000400 { + compatible = "mediatek,mt7622-pcie-mirror", "syscon"; + reg = <0 0x10000400 0 0x10>; + }; + }; diff --git a/dts/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml b/dts/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml new file mode 100644 index 0000000000..e7720caf31 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Wireless Ethernet Dispatch Controller for MT7622 + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + - Felix Fietkau <nbd@nbd.name> + +description: + The mediatek wireless ethernet dispatch controller can be configured to + intercept and handle access to the WLAN DMA queues and PCIe interrupts + and implement hardware flow offloading from ethernet to WLAN. + +properties: + compatible: + items: + - enum: + - mediatek,mt7622-wed + - mediatek,mt7981-wed + - mediatek,mt7986-wed + - mediatek,mt7988-wed + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + memory-region: + items: + - description: firmware EMI region + - description: firmware ILM region + - description: firmware DLM region + - description: firmware CPU DATA region + - description: firmware BOOT region + + memory-region-names: + items: + - const: wo-emi + - const: wo-ilm + - const: wo-dlm + - const: wo-data + - const: wo-boot + + mediatek,wo-ccif: + $ref: /schemas/types.yaml#/definitions/phandle + description: mediatek wed-wo controller interface. + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt7622-wed + then: + properties: + memory-region-names: false + memory-region: false + mediatek,wo-ccif: false + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + wed0: wed@1020a000 { + compatible = "mediatek,mt7622-wed","syscon"; + reg = <0 0x1020a000 0 0x1000>; + interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + wed@15010000 { + compatible = "mediatek,mt7986-wed", "syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + + memory-region = <&wo_emi>, <&wo_ilm>, <&wo_dlm>, + <&wo_data>, <&wo_boot>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", + "wo-data", "wo-boot"; + mediatek,wo-ccif = <&wo_ccif0>; + }; + }; diff --git a/dts/Bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml b/dts/Bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml new file mode 100644 index 0000000000..82f64469a6 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIE WED Controller for MT7986 + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + - Felix Fietkau <nbd@nbd.name> + +description: + The mediatek WED PCIE provides a configuration interface for PCIE + controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7986-wed-pcie + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + wed_pcie: wed-pcie@10003000 { + compatible = "mediatek,mt7986-wed-pcie", + "syscon"; + reg = <0 0x10003000 0 0x10>; + }; + }; diff --git a/dts/Bindings/arm/mediatek/mediatek,mt8186-clock.yaml b/dts/Bindings/arm/mediatek/mediatek,mt8186-clock.yaml new file mode 100644 index 0000000000..7cd14b163a --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,mt8186-clock.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Functional Clock Controller for MT8186 + +maintainers: + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The devices provide clock gate control in different IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt8186-imp_iic_wrap + - mediatek,mt8186-mfgsys + - mediatek,mt8186-wpesys + - mediatek,mt8186-imgsys1 + - mediatek,mt8186-imgsys2 + - mediatek,mt8186-vdecsys + - mediatek,mt8186-vencsys + - mediatek,mt8186-camsys + - mediatek,mt8186-camsys_rawa + - mediatek,mt8186-camsys_rawb + - mediatek,mt8186-mdpsys + - mediatek,mt8186-ipesys + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + imp_iic_wrap: clock-controller@11017000 { + compatible = "mediatek,mt8186-imp_iic_wrap"; + reg = <0x11017000 0x1000>; + #clock-cells = <1>; + }; diff --git a/dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml new file mode 100644 index 0000000000..64c7694166 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Clock Controller for MT8186 + +maintainers: + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The apmixedsys provides most of PLLs which generated from SoC 26m. + The topckgen provides dividers and muxes which provide the clock source to other IP blocks. + The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks. + The mcusys provides mux control to select the clock source in AP MCU. + The device nodes also provide the system control capacity for configuration. + +properties: + compatible: + items: + - enum: + - mediatek,mt8186-mcusys + - mediatek,mt8186-topckgen + - mediatek,mt8186-infracfg_ao + - mediatek,mt8186-apmixedsys + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + topckgen: syscon@10000000 { + compatible = "mediatek,mt8186-topckgen", "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; diff --git a/dts/Bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/dts/Bindings/arm/mediatek/mediatek,mt8192-clock.yaml index c8c67c033f..dff4c8e8fd 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mt8192-clock.yaml +++ b/dts/Bindings/arm/mediatek/mediatek,mt8192-clock.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek Functional Clock Controller for MT8192 @@ -24,7 +24,6 @@ properties: - mediatek,mt8192-imp_iic_wrap_w - mediatek,mt8192-imp_iic_wrap_n - mediatek,mt8192-msdc_top - - mediatek,mt8192-msdc - mediatek,mt8192-mfgcfg - mediatek,mt8192-imgsys - mediatek,mt8192-imgsys2 @@ -108,13 +107,6 @@ examples: }; - | - msdc: clock-controller@11f60000 { - compatible = "mediatek,mt8192-msdc"; - reg = <0x11f60000 0x1000>; - #clock-cells = <1>; - }; - - - | mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt8192-mfgcfg"; reg = <0x13fbf000 0x1000>; diff --git a/dts/Bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/dts/Bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml index 5705bcf1fe..8d608fddf3 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml +++ b/dts/Bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek System Clock Controller for MT8192 @@ -29,6 +29,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg diff --git a/dts/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/dts/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml index 17fcbb45d1..d17164b0b1 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml +++ b/dts/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek Functional Clock Controller for MT8195 @@ -28,11 +28,9 @@ properties: - mediatek,mt8195-imp_iic_wrap_s - mediatek,mt8195-imp_iic_wrap_w - mediatek,mt8195-mfgcfg - - mediatek,mt8195-vppsys0 - mediatek,mt8195-wpesys - mediatek,mt8195-wpesys_vpp0 - mediatek,mt8195-wpesys_vpp1 - - mediatek,mt8195-vppsys1 - mediatek,mt8195-imgsys - mediatek,mt8195-imgsys1_dip_top - mediatek,mt8195-imgsys1_dip_nr @@ -93,13 +91,6 @@ examples: }; - | - vppsys0: clock-controller@14000000 { - compatible = "mediatek,mt8195-vppsys0"; - reg = <0x14000000 0x1000>; - #clock-cells = <1>; - }; - - - | wpesys: clock-controller@14e00000 { compatible = "mediatek,mt8195-wpesys"; reg = <0x14e00000 0x1000>; @@ -121,13 +112,6 @@ examples: }; - | - vppsys1: clock-controller@14f00000 { - compatible = "mediatek,mt8195-vppsys1"; - reg = <0x14f00000 0x1000>; - #clock-cells = <1>; - }; - - - | imgsys: clock-controller@15000000 { compatible = "mediatek,mt8195-imgsys"; reg = <0x15000000 0x1000>; diff --git a/dts/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/dts/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml index 57a1503d95..066c9b3d6a 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml +++ b/dts/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek System Clock Controller for MT8195 @@ -37,6 +37,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg diff --git a/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml b/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml index 8723dfe34b..33c94c4918 100644 --- a/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek Peripheral Configuration Controller @@ -21,11 +21,15 @@ properties: - mediatek,mt2701-pericfg - mediatek,mt2712-pericfg - mediatek,mt6765-pericfg + - mediatek,mt6795-pericfg - mediatek,mt7622-pericfg - mediatek,mt7629-pericfg - mediatek,mt8135-pericfg - mediatek,mt8173-pericfg - mediatek,mt8183-pericfg + - mediatek,mt8186-pericfg + - mediatek,mt8188-pericfg + - mediatek,mt8195-pericfg - mediatek,mt8516-pericfg - const: syscon - items: diff --git a/dts/Bindings/arm/mediatek/mediatek,sgmiisys.txt b/dts/Bindings/arm/mediatek/mediatek,sgmiisys.txt deleted file mode 100644 index 29ca7a10b3..0000000000 --- a/dts/Bindings/arm/mediatek/mediatek,sgmiisys.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek SGMIISYS controller -============================ - -The MediaTek SGMIISYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt7622-sgmiisys", "syscon" - - "mediatek,mt7629-sgmiisys", "syscon" - - "mediatek,mt7986-sgmiisys_0", "syscon" - - "mediatek,mt7986-sgmiisys_1", "syscon" -- #clock-cells: Must be 1 - -The SGMIISYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -sgmiisys: sgmiisys@1b128000 { - compatible = "mediatek,mt7622-sgmiisys", "syscon"; - reg = <0 0x1b128000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt deleted file mode 100644 index b82422bb71..0000000000 --- a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt +++ /dev/null @@ -1,35 +0,0 @@ -Mediatek topckgen controller -============================ - -The Mediatek topckgen controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-topckgen" - - "mediatek,mt2712-topckgen", "syscon" - - "mediatek,mt6765-topckgen", "syscon" - - "mediatek,mt6779-topckgen", "syscon" - - "mediatek,mt6797-topckgen" - - "mediatek,mt7622-topckgen" - - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" - - "mediatek,mt7629-topckgen" - - "mediatek,mt7986-topckgen", "syscon" - - "mediatek,mt8135-topckgen" - - "mediatek,mt8167-topckgen", "syscon" - - "mediatek,mt8173-topckgen" - - "mediatek,mt8183-topckgen", "syscon" - - "mediatek,mt8516-topckgen" -- #clock-cells: Must be 1 - -The topckgen controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -topckgen: power-controller@10000000 { - compatible = "mediatek,mt8173-topckgen"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; -}; diff --git a/dts/Bindings/arm/mediatek/mediatek,vcodecsys.txt b/dts/Bindings/arm/mediatek/mediatek,vcodecsys.txt index c877bcc1a5..f090147b7f 100644 --- a/dts/Bindings/arm/mediatek/mediatek,vcodecsys.txt +++ b/dts/Bindings/arm/mediatek/mediatek,vcodecsys.txt @@ -15,7 +15,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h. The vcodecsys controller also uses the common power domain from Documentation/devicetree/bindings/soc/mediatek/scpsys.txt -The available power doamins are defined in dt-bindings/power/mt*-power.h. +The available power domains are defined in dt-bindings/power/mt*-power.h. Example: |