diff options
Diffstat (limited to 'dts/Bindings/bus')
| -rw-r--r-- | dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml | 8 | ||||
| -rw-r--r-- | dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml | 3 | ||||
| -rw-r--r-- | dts/Bindings/bus/aspeed,ast2600-ahbc.yaml | 37 | ||||
| -rw-r--r-- | dts/Bindings/bus/brcm,gisb-arb.txt | 34 | ||||
| -rw-r--r-- | dts/Bindings/bus/brcm,gisb-arb.yaml | 67 | ||||
| -rw-r--r-- | dts/Bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 229 | ||||
| -rw-r--r-- | dts/Bindings/bus/fsl,spba-bus.yaml | 68 | ||||
| -rw-r--r-- | dts/Bindings/bus/imx-weim.txt | 112 | ||||
| -rw-r--r-- | dts/Bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml | 168 | ||||
| -rw-r--r-- | dts/Bindings/bus/microsoft,vmbus.yaml | 54 | ||||
| -rw-r--r-- | dts/Bindings/bus/nvidia,tegra210-aconnect.yaml | 9 | ||||
| -rw-r--r-- | dts/Bindings/bus/palmbus.yaml | 80 | ||||
| -rw-r--r-- | dts/Bindings/bus/qcom,ssbi.yaml | 63 | ||||
| -rw-r--r-- | dts/Bindings/bus/qcom,ssc-block-bus.yaml | 144 | ||||
| -rw-r--r-- | dts/Bindings/bus/ti-sysc.txt | 139 | ||||
| -rw-r--r-- | dts/Bindings/bus/ti-sysc.yaml | 215 | ||||
| -rw-r--r-- | dts/Bindings/bus/xlnx,versal-net-cdx.yaml | 82 |
17 files changed, 1052 insertions, 460 deletions
diff --git a/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml b/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml index 863a287ebc..9845a187bd 100644 --- a/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml +++ b/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/bus/allwinner,sun50i-a64-de2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A64 Display Engine Bus Device Tree Bindings +title: Allwinner A64 Display Engine Bus maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -35,7 +35,10 @@ properties: The SRAM that needs to be claimed to access the display engine bus. $ref: /schemas/types.yaml#/definitions/phandle-array - maxItems: 1 + items: + - items: + - description: phandle to SRAM + - description: register value for device ranges: true @@ -43,6 +46,7 @@ patternProperties: # All other properties should be child nodes with unit-address and 'reg' "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+$": type: object + additionalProperties: true properties: reg: maxItems: 1 diff --git a/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml b/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml index 3d719f468a..24c939f590 100644 --- a/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml +++ b/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/bus/allwinner,sun8i-a23-rsb.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A23 RSB Device Tree Bindings +title: Allwinner A23 RSB maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -45,6 +45,7 @@ properties: patternProperties: "^.*@[0-9a-fA-F]+$": type: object + additionalProperties: true properties: reg: maxItems: 1 diff --git a/dts/Bindings/bus/aspeed,ast2600-ahbc.yaml b/dts/Bindings/bus/aspeed,ast2600-ahbc.yaml new file mode 100644 index 0000000000..2894256c97 --- /dev/null +++ b/dts/Bindings/bus/aspeed,ast2600-ahbc.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/aspeed,ast2600-ahbc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED Advanced High-Performance Bus Controller (AHBC) + +maintainers: + - Neal Liu <neal_liu@aspeedtech.com> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com> + +description: | + Advanced High-performance Bus Controller (AHBC) supports plenty of mechanisms + including a priority arbiter, an address decoder and a data multiplexer + to control the overall operations of Advanced High-performance Bus (AHB). + +properties: + compatible: + enum: + - aspeed,ast2600-ahbc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + ahbc@1e600000 { + compatible = "aspeed,ast2600-ahbc"; + reg = <0x1e600000 0x100>; + }; diff --git a/dts/Bindings/bus/brcm,gisb-arb.txt b/dts/Bindings/bus/brcm,gisb-arb.txt deleted file mode 100644 index 10f6d0a815..0000000000 --- a/dts/Bindings/bus/brcm,gisb-arb.txt +++ /dev/null @@ -1,34 +0,0 @@ -Broadcom GISB bus Arbiter controller - -Required properties: - -- compatible: - "brcm,bcm7278-gisb-arb" for V7 28nm chips - "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips - "brcm,bcm7435-gisb-arb" for newer 40nm chips - "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips - "brcm,bcm7038-gisb-arb" for 130nm chips -- reg: specifies the base physical address and size of the registers -- interrupts: specifies the two interrupts (timeout and TEA) to be used from - the parent interrupt controller. A third optional interrupt may be specified - for breakpoints. - -Optional properties: - -- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB - masters are valid at the system level -- brcm,gisb-arb-master-names: string list of the litteral name of the GISB - masters. Should match the number of bits set in brcm,gisb-master-mask and - the order in which they appear - -Example: - -gisb-arb@f0400000 { - compatible = "brcm,gisb-arb"; - reg = <0xf0400000 0x800>; - interrupts = <0>, <2>; - interrupt-parent = <&sun_l2_intc>; - - brcm,gisb-arb-master-mask = <0x7>; - brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; -}; diff --git a/dts/Bindings/bus/brcm,gisb-arb.yaml b/dts/Bindings/bus/brcm,gisb-arb.yaml new file mode 100644 index 0000000000..9017c5a3f3 --- /dev/null +++ b/dts/Bindings/bus/brcm,gisb-arb.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom GISB bus Arbiter controller + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,bcm7445-gisb-arb # for other 28nm chips + - const: brcm,gisb-arb + - items: + - enum: + - brcm,bcm74165-gisb-arb # for V7 new style 16nm chips + - brcm,bcm7278-gisb-arb # for V7 28nm chips + - brcm,bcm7435-gisb-arb # for newer 40nm chips + - brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips + - brcm,bcm7038-gisb-arb # for 130nm chips + - brcm,gisb-arb # fallback compatible + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + items: + - description: timeout interrupt line + - description: target abort interrupt line + - description: breakpoint interrupt line + + brcm,gisb-arb-master-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + 32-bits wide bitmask used to specify which GISB masters are valid at the + system level + + brcm,gisb-arb-master-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: > + String list of the literal name of the GISB masters. Should match the + number of bits set in brcm,gisb-master-mask and the order in which they + appear from MSB to LSB. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + gisb-arb@f0400000 { + compatible = "brcm,gisb-arb"; + reg = <0xf0400000 0x800>; + interrupts = <0>, <2>; + interrupt-parent = <&sun_l2_intc>; + brcm,gisb-arb-master-mask = <0x7>; + brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; + }; diff --git a/dts/Bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/dts/Bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml new file mode 100644 index 0000000000..7e1ffc5510 --- /dev/null +++ b/dts/Bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml @@ -0,0 +1,229 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus + +maintainers: + - Liu Ying <victor.liu@nxp.com> + +description: | + i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os + sitting together with the PHYs. It is not the same as the MSI bus coming + from i.MX8 System Controller Unit (SCU) which is used to control power, + clock and reset through the i.MX8 Distributed Slave System Controller (DSC). + + i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks, + that is, MSI clock and AHB clock, need to be enabled so that peripherals + connected to the bus can be accessed. Also, the bus is part of a power + domain. The power domain needs to be enabled before the peripherals can + be accessed. + + Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems, + like I2C controller, PWM controller, MIPI DSI controller and Control and + Status Registers (CSR) module, are accessed through the bus. + + The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp + pixel link MSI bus controller and does not allow SCFW user to control it. + So, the controller's registers cannot be accessed by SCFW user. Hence, + the interrupts generated by the controller don't make any sense from SCFW + user's point of view. + +allOf: + - $ref: simple-pm-bus.yaml# + +# We need a select here so we don't match all nodes with 'simple-pm-bus'. +select: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + required: + - compatible + +properties: + compatible: + items: + - enum: + - fsl,imx8qxp-display-pixel-link-msi-bus + - fsl,imx8qm-display-pixel-link-msi-bus + - const: simple-pm-bus + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: master gated clock from system + - description: AHB clock + + clock-names: + items: + - const: msi + - const: ahb + +patternProperties: + "^.*@[0-9a-f]+$": + description: Devices attached to the bus + type: object + + required: + - reg + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + bus@56200000 { + compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus"; + reg = <0x56200000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <320>; + ranges; + clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>, + <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>; + clock-names = "msi", "ahb"; + power-domains = <&pd IMX_SC_R_DC_0>; + + syscon@56221000 { + compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd"; + reg = <0x56221000 0x1000>; + clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + + pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = <IMX_SC_R_MIPI_0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; + }; + }; + }; + }; + + ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + }; + }; + + clock-controller@56223004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223004 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_0_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>; + clock-output-names = "mipi_lvds_0_di_mipi_lvds_regs_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + phy@56228300 { + compatible = "fsl,imx8qxp-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + fsl,syscon = <&mipi_lvds_0_csr>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + }; diff --git a/dts/Bindings/bus/fsl,spba-bus.yaml b/dts/Bindings/bus/fsl,spba-bus.yaml new file mode 100644 index 0000000000..d42dbb0bbc --- /dev/null +++ b/dts/Bindings/bus/fsl,spba-bus.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Shared Peripherals Bus Interface + +maintainers: + - Shawn Guo <shawnguo@kernel.org> + +description: | + A simple bus enabling access to shared peripherals. + + The "spba-bus" follows the "simple-bus" set of properties, as + specified in the Devicetree Specification. It is an extension of + "simple-bus" because the SDMA controller uses this compatible flag to + determine which peripherals are available to it and the range over which + the SDMA can access. There are no special clocks for the bus, because + the SDMA controller itself has its interrupt and clock assignments. + +select: + properties: + compatible: + contains: + const: fsl,spba-bus + required: + - compatible + +properties: + $nodename: + pattern: "^spba-bus(@[0-9a-f]+)?$" + + compatible: + items: + - const: fsl,spba-bus + - const: simple-bus + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + reg: + maxItems: 1 + + ranges: true + +required: + - compatible + - '#address-cells' + - '#size-cells' + - reg + - ranges + +additionalProperties: + type: object + +examples: + - | + spba-bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + }; diff --git a/dts/Bindings/bus/imx-weim.txt b/dts/Bindings/bus/imx-weim.txt deleted file mode 100644 index 1b1d1c5c21..0000000000 --- a/dts/Bindings/bus/imx-weim.txt +++ /dev/null @@ -1,112 +0,0 @@ -Device tree bindings for i.MX Wireless External Interface Module (WEIM) - -The term "wireless" does not imply that the WEIM is literally an interface -without wires. It simply means that this module was originally designed for -wireless and mobile applications that use low-power technology. - -The actual devices are instantiated from the child nodes of a WEIM node. - -Required properties: - - - compatible: Should contain one of the following: - "fsl,imx1-weim" - "fsl,imx27-weim" - "fsl,imx51-weim" - "fsl,imx50-weim" - "fsl,imx6q-weim" - - reg: A resource specifier for the register space - (see the example below) - - clocks: the clock, see the example below. - - #address-cells: Must be set to 2 to allow memory address translation - - #size-cells: Must be set to 1 to allow CS address passing - - ranges: Must be set up to reflect the memory layout with four - integer values for each chip-select line in use: - - <cs-number> 0 <physical address of mapping> <size> - -Optional properties: - - - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of - devices, it should be the phandle to the system General - Purpose Register controller that contains WEIM CS GPR - register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0] - should be set up as one of the following 4 possible - values depending on the CS space configuration. - - IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3 - --------------------------------------------- - 05 128M 0M 0M 0M - 033 64M 64M 0M 0M - 0113 64M 32M 32M 0M - 01111 32M 32M 32M 32M - - In case that the property is absent, the reset value or - what bootloader sets up in IOMUXC_GPR1[11:0] will be - used. - - - fsl,burst-clk-enable For "fsl,imx50-weim" and "fsl,imx6q-weim" type of - devices, the presence of this property indicates that - the weim bus should operate in Burst Clock Mode. - -Timing property for child nodes. It is mandatory, not optional. - - - fsl,weim-cs-timing: The timing array, contains timing values for the - child node. We get the CS indexes from the address - ranges in the child node's "reg" property. - The number of registers depends on the selected chip: - For i.MX1, i.MX21 ("fsl,imx1-weim") there are two - registers: CSxU, CSxL. - For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim") - there are three registers: CSCRxU, CSCRxL, CSCRxA. - For i.MX50, i.MX53 ("fsl,imx50-weim"), - i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim") - there are six registers: CSxGCR1, CSxGCR2, CSxRCR1, - CSxRCR2, CSxWCR1, CSxWCR2. - -Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: - - weim: weim@21b8000 { - compatible = "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - clocks = <&clks 196>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x08000000>; - fsl,weim-cs-gpr = <&gpr>; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x02000000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 - 0x0000c000 0x1404a38e 0x00000000>; - }; - }; - -Example for an imx6q-based board, a multi-chipselect device connected to WEIM: - -In this case, both chip select 0 and 1 will be configured with the same timing -array values. - - weim: weim@21b8000 { - compatible = "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - clocks = <&clks 196>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x02000000 - 1 0 0x0a000000 0x02000000 - 2 0 0x0c000000 0x02000000 - 3 0 0x0e000000 0x02000000>; - fsl,weim-cs-gpr = <&gpr>; - - acme@0 { - compatible = "acme,whatever"; - reg = <0 0 0x100>, <0 0x400000 0x800>, - <1 0x400000 0x800>; - fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100 - 0x00000000 0xa0000240 0x00000000>; - }; - }; diff --git a/dts/Bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml b/dts/Bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml deleted file mode 100644 index 5fb4e7bfa4..0000000000 --- a/dts/Bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml +++ /dev/null @@ -1,168 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Intel IXP4xx Expansion Bus Controller - -description: | - The IXP4xx expansion bus controller handles access to devices on the - memory-mapped expansion bus on the Intel IXP4xx family of system on chips, - including IXP42x, IXP43x, IXP45x and IXP46x. - -maintainers: - - Linus Walleij <linus.walleij@linaro.org> - -properties: - $nodename: - pattern: '^bus@[0-9a-f]+$' - - compatible: - items: - - enum: - - intel,ixp42x-expansion-bus-controller - - intel,ixp43x-expansion-bus-controller - - intel,ixp45x-expansion-bus-controller - - intel,ixp46x-expansion-bus-controller - - const: syscon - - reg: - description: Control registers for the expansion bus, these are not - inside the memory range handled by the expansion bus. - maxItems: 1 - - native-endian: - $ref: /schemas/types.yaml#/definitions/flag - description: The IXP4xx has a peculiar MMIO access scheme, as it changes - the access pattern for words (swizzling) on the bus depending on whether - the SoC is running in big-endian or little-endian mode. Thus the - registers must always be accessed using native endianness. - - "#address-cells": - description: | - The first cell is the chip select number. - The second cell is the address offset within the bank. - const: 2 - - "#size-cells": - const: 1 - - ranges: true - dma-ranges: true - -patternProperties: - "^.*@[0-7],[0-9a-f]+$": - description: Devices attached to chip selects are represented as - subnodes. - type: object - - properties: - intel,ixp4xx-eb-t1: - description: Address timing, extend address phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 3 - - intel,ixp4xx-eb-t2: - description: Setup chip select timing, extend setup phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 3 - - intel,ixp4xx-eb-t3: - description: Strobe timing, extend strobe phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 15 - - intel,ixp4xx-eb-t4: - description: Hold timing, extend hold phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 3 - - intel,ixp4xx-eb-t5: - description: Recovery timing, extend recovery phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 15 - - intel,ixp4xx-eb-cycle-type: - description: The type of cycles to use on the expansion bus for this - chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2] - - intel,ixp4xx-eb-byte-access-on-halfword: - description: Allow byte read access on half word devices. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-hpi-hrdy-pol-high: - description: Set HPI HRDY polarity to active high when using HPI. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-mux-address-and-data: - description: Multiplex address and data on the data bus. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-ahb-split-transfers: - description: Enable AHB split transfers. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-write-enable: - description: Enable write cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-byte-access: - description: Expansion bus uses only 8 bits. The default is to use - 16 bits. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - -required: - - compatible - - reg - - native-endian - - "#address-cells" - - "#size-cells" - - ranges - - dma-ranges - -additionalProperties: false - -examples: - - | - #include <dt-bindings/interrupt-controller/irq.h> - bus@50000000 { - compatible = "intel,ixp42x-expansion-bus-controller", "syscon"; - reg = <0xc4000000 0x28>; - native-endian; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0x0 0x50000000 0x01000000>, - <1 0x0 0x51000000 0x01000000>; - dma-ranges = <0 0x0 0x50000000 0x01000000>, - <1 0x0 0x51000000 0x01000000>; - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - reg = <0 0x00000000 0x1000000>; - intel,ixp4xx-eb-t3 = <3>; - intel,ixp4xx-eb-cycle-type = <0>; - intel,ixp4xx-eb-byte-access-on-halfword = <1>; - intel,ixp4xx-eb-write-enable = <1>; - intel,ixp4xx-eb-byte-access = <0>; - }; - serial@1,0 { - compatible = "exar,xr16l2551", "ns8250"; - reg = <1 0x00000000 0x10>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - clock-frequency = <1843200>; - intel,ixp4xx-eb-t3 = <3>; - intel,ixp4xx-eb-cycle-type = <1>; - intel,ixp4xx-eb-write-enable = <1>; - intel,ixp4xx-eb-byte-access = <1>; - }; - }; diff --git a/dts/Bindings/bus/microsoft,vmbus.yaml b/dts/Bindings/bus/microsoft,vmbus.yaml new file mode 100644 index 0000000000..a8d40c766d --- /dev/null +++ b/dts/Bindings/bus/microsoft,vmbus.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/microsoft,vmbus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsoft Hyper-V VMBus + +maintainers: + - Saurabh Sengar <ssengar@linux.microsoft.com> + +description: + VMBus is a software bus that implement the protocols for communication + between the root or host OS and guest OSs (virtual machines). + +properties: + compatible: + const: microsoft,vmbus + + ranges: true + + '#address-cells': + const: 2 + + '#size-cells': + const: 1 + +required: + - compatible + - ranges + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <1>; + bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + vmbus@ff0000000 { + compatible = "microsoft,vmbus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0f 0xf0000000 0x0f 0xf0000000 0x10000000>; + }; + }; + }; diff --git a/dts/Bindings/bus/nvidia,tegra210-aconnect.yaml b/dts/Bindings/bus/nvidia,tegra210-aconnect.yaml index 7b1a08c62a..26362c9006 100644 --- a/dts/Bindings/bus/nvidia,tegra210-aconnect.yaml +++ b/dts/Bindings/bus/nvidia,tegra210-aconnect.yaml @@ -7,10 +7,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra ACONNECT Bus description: | - The Tegra ACONNECT bus is an AXI switch which is used to connnect various + The Tegra ACONNECT bus is an AXI switch which is used to connect various components inside the Audio Processing Engine (APE). All CPU accesses to the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All - devices accessed via the ACONNNECT are described by child-nodes. + devices accessed via the ACONNECT are described by child-nodes. maintainers: - Jon Hunter <jonathanh@nvidia.com> @@ -21,6 +21,7 @@ properties: - const: nvidia,tegra210-aconnect - items: - enum: + - nvidia,tegra234-aconnect - nvidia,tegra186-aconnect - nvidia,tegra194-aconnect - const: nvidia,tegra210-aconnect @@ -39,10 +40,10 @@ properties: maxItems: 1 "#address-cells": - const: 1 + enum: [ 1, 2 ] "#size-cells": - const: 1 + enum: [ 1, 2 ] ranges: true diff --git a/dts/Bindings/bus/palmbus.yaml b/dts/Bindings/bus/palmbus.yaml new file mode 100644 index 0000000000..c36c1e92a5 --- /dev/null +++ b/dts/Bindings/bus/palmbus.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/palmbus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink PalmBus + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + The ralink palmbus controller can be found in all ralink MIPS + SoCs. It provides an external bus for connecting multiple + external devices to the SoC. + +properties: + $nodename: + pattern: "^palmbus(@[0-9a-f]+)?$" + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + compatible: + const: palmbus + + reg: + maxItems: 1 + + ranges: true + +patternProperties: + # All other properties should be child nodes with unit-address and 'reg' + "@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + reg: + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + palmbus@1e000000 { + compatible = "palmbus"; + reg = <0x1e000000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000000 0x0fffff>; + + gpio@600 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "mediatek,mt7621-gpio"; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 95>; + interrupt-controller; + reg = <0x600 0x100>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + +... diff --git a/dts/Bindings/bus/qcom,ssbi.yaml b/dts/Bindings/bus/qcom,ssbi.yaml new file mode 100644 index 0000000000..693cfa9696 --- /dev/null +++ b/dts/Bindings/bus/qcom,ssbi.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/qcom,ssbi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Single-wire Serial Bus Interface (SSBI) + +description: + Some Qualcomm MSM devices contain a point-to-point serial bus used to + communicate with a limited range of devices (mostly power management + chips). + +maintainers: + - Andy Gross <agross@kernel.org> + - Bjorn Andersson <andersson@kernel.org> + +properties: + compatible: + const: qcom,ssbi + + reg: + maxItems: 1 + + qcom,controller-type: + description: + Indicates the SSBI bus variant the controller should use to talk + with the slave device. The type chosen is determined by the attached + slave. + enum: + - ssbi + - ssbi2 + - pmic-arbiter + + pmic: + $ref: /schemas/mfd/qcom-pm8xxx.yaml# + +required: + - compatible + - reg + - qcom,controller-type + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + ssbi@c00000 { + compatible = "qcom,ssbi"; + reg = <0x00c00000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + + pmic { + compatible = "qcom,pm8821"; + interrupt-parent = <&msmgpio>; + interrupts = <76 IRQ_TYPE_LEVEL_LOW>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +... diff --git a/dts/Bindings/bus/qcom,ssc-block-bus.yaml b/dts/Bindings/bus/qcom,ssc-block-bus.yaml new file mode 100644 index 0000000000..8e9e6ff35d --- /dev/null +++ b/dts/Bindings/bus/qcom,ssc-block-bus.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs + +maintainers: + - Michael Srba <Michael.Srba@seznam.cz> + +description: | + This binding describes the dependencies (clocks, resets, power domains) which + need to be turned on in a sequence before communication over the AHB bus + becomes possible. + + Additionally, the reg property is used to pass to the driver the location of + two sadly undocumented registers which need to be poked as part of the sequence. + + The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart + controllers, a hexagon core, and a clock controller which provides clocks for + the above. + +properties: + compatible: + items: + - const: qcom,msm8998-ssc-block-bus + - const: qcom,ssc-block-bus + + reg: + items: + - description: SSCAON_CONFIG0 registers + - description: SSCAON_CONFIG1 registers + + reg-names: + items: + - const: mpm_sscaon_config0 + - const: mpm_sscaon_config1 + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + ranges: true + + clocks: + maxItems: 6 + + clock-names: + items: + - const: xo + - const: aggre2 + - const: gcc_im_sleep + - const: aggre2_north + - const: ssc_xo + - const: ssc_ahbs + + power-domains: + items: + - description: CX power domain + - description: MX power domain + + power-domain-names: + items: + - const: ssc_cx + - const: ssc_mx + + resets: + items: + - description: Main reset + - description: + SSC Branch Control Register reset (associated with the ssc_xo and + ssc_ahbs clocks) + + reset-names: + items: + - const: ssc_reset + - const: ssc_bcr + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: describes how to locate the ssc AXI halt register + items: + - items: + - description: Phandle reference to a syscon representing TCSR + - description: offset for the ssc AXI halt register + +required: + - compatible + - reg + - reg-names + - '#address-cells' + - '#size-cells' + - ranges + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - qcom,halt-regs + +additionalProperties: + type: object + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8998.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <1>; + #size-cells = <1>; + + // devices under this node are physically located in the SSC block, connected to an ssc-internal bus; + ssc_ahb_slave: bus@10ac008 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus"; + reg = <0x10ac008 0x4>, <0x10ac010 0x4>; + reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1"; + + clocks = <&xo>, + <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&gcc GCC_IM_SLEEP>, + <&gcc AGGRE2_SNOC_NORTH_AXI>, + <&gcc SSC_XO>, + <&gcc SSC_CNOC_AHBS_CLK>; + clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs"; + + resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>; + reset-names = "ssc_reset", "ssc_bcr"; + + power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>; + power-domain-names = "ssc_cx", "ssc_mx"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x26000>; + }; + }; diff --git a/dts/Bindings/bus/ti-sysc.txt b/dts/Bindings/bus/ti-sysc.txt deleted file mode 100644 index c984143d08..0000000000 --- a/dts/Bindings/bus/ti-sysc.txt +++ /dev/null @@ -1,139 +0,0 @@ -Texas Instruments sysc interconnect target module wrapper binding - -Texas Instruments SoCs can have a generic interconnect target module -hardware for devices connected to various interconnects such as L3 -interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc -is mostly used for interaction between module and PRCM. It participates -in the OCP Disconnect Protocol but other than that is mostly independent -of the interconnect. - -Each interconnect target module can have one or more devices connected to -it. There is a set of control registers for managing interconnect target -module clocks, idle modes and interconnect level resets for the module. - -These control registers are sprinkled into the unused register address -space of the first child device IP block managed by the interconnect -target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. - -Required standard properties: - -- compatible shall be one of the following generic types: - - "ti,sysc" - "ti,sysc-omap2" - "ti,sysc-omap4" - "ti,sysc-omap4-simple" - - or one of the following derivative types for hardware - needing special workarounds: - - "ti,sysc-omap2-timer" - "ti,sysc-omap4-timer" - "ti,sysc-omap3430-sr" - "ti,sysc-omap3630-sr" - "ti,sysc-omap4-sr" - "ti,sysc-omap3-sham" - "ti,sysc-omap-aes" - "ti,sysc-mcasp" - "ti,sysc-dra7-mcasp" - "ti,sysc-usb-host-fs" - "ti,sysc-dra7-mcan" - "ti,sysc-pruss" - -- reg shall have register areas implemented for the interconnect - target module in question such as revision, sysc and syss - -- reg-names shall contain the register names implemented for the - interconnect target module in question such as - "rev, "sysc", and "syss" - -- ranges shall contain the interconnect target module IO range - available for one or more child device IP blocks managed - by the interconnect target module, the ranges may include - multiple ranges such as device L4 range for control and - parent L3 range for DMA access - -Optional properties: - -- ti,sysc-mask shall contain mask of supported register bits for the - SYSCONFIG register as documented in the Technical Reference - Manual (TRM) for the interconnect target module - -- ti,sysc-midle list of master idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register MIDLEMODE bits - -- ti,sysc-sidle list of slave idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register SIDLEMODE bits - -- ti,sysc-delay-us delay needed after OCP softreset before accssing - SYSCONFIG register again - -- ti,syss-mask optional mask of reset done status bits as described in the - TRM for SYSSTATUS registers, typically 1 with some devices - having separate reset done bits for children like OHCI and - EHCI - -- clocks clock specifier for each name in the clock-names as - specified in the binding documentation for ti-clkctrl, - typically available for all interconnect targets on TI SoCs - based on omap4 except if it's read-only register in hwauto - mode as for example omap4 L4_CFG_CLKCTRL - -- clock-names should contain at least "fck", and optionally also "ick" - depending on the SoC and the interconnect target module, - some interconnect target modules also need additional - optional clocks that can be specified as listed in TRM - for the related CLKCTRL register bits 8 to 15 such as - "dbclk" or "clk32k" depending on their role - -- ti,hwmods optional TI interconnect module name to use legacy - hwmod platform data - -- ti,no-reset-on-init interconnect target module should not be reset at init - -- ti,no-idle-on-init interconnect target module should not be idled at init - -- ti,no-idle interconnect target module should not be idled - -Example: Single instance of MUSB controller on omap4 using interconnect ranges -using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): - - target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ - compatible = "ti,sysc-omap2"; - ti,hwmods = "usb_otg_hs"; - reg = <0x2b400 0x4>, - <0x2b404 0x4>, - <0x2b408 0x4>; - reg-names = "rev", "sysc", "syss"; - clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; - clock-names = "fck"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2b000 0x1000>; - - usb_otg_hs: otg@0 { - compatible = "ti,omap4-musb"; - reg = <0x0 0x7ff>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - usb-phy = <&usb2_phy>; - ... - }; - }; - -Note that other SoCs, such as am335x can have multiple child devices. On am335x -there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA -instance as children of a single interconnect target module. diff --git a/dts/Bindings/bus/ti-sysc.yaml b/dts/Bindings/bus/ti-sysc.yaml new file mode 100644 index 0000000000..6d7bca6c13 --- /dev/null +++ b/dts/Bindings/bus/ti-sysc.yaml @@ -0,0 +1,215 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/ti-sysc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments interconnect target module + +maintainers: + - Tony Lindgren <tony@atomide.com> + +description: + Texas Instruments SoCs can have a generic interconnect target module + for devices connected to various interconnects such as L3 interconnect + using Arteris NoC, and L4 interconnect using Sonics s3220. This module + is mostly used for interaction between module and Power, Reset and Clock + Manager PRCM. It participates in the OCP Disconnect Protocol, but other + than that it is mostly independent of the interconnect. + + Each interconnect target module can have one or more devices connected to + it. There is a set of control registers for managing the interconnect target + module clocks, idle modes and interconnect level resets. + + The interconnect target module control registers are sprinkled into the + unused register address space of the first child device IP block managed by + the interconnect target module. Typically the register names are REVISION, + SYSCONFIG and SYSSTATUS. + +properties: + $nodename: + pattern: "^target-module(@[0-9a-f]+)?$" + + compatible: + oneOf: + - items: + - enum: + - ti,sysc-omap2 + - ti,sysc-omap4 + - ti,sysc-omap4-simple + - ti,sysc-omap2-timer + - ti,sysc-omap4-timer + - ti,sysc-omap3430-sr + - ti,sysc-omap3630-sr + - ti,sysc-omap4-sr + - ti,sysc-omap3-sham + - ti,sysc-omap-aes + - ti,sysc-mcasp + - ti,sysc-dra7-mcasp + - ti,sysc-usb-host-fs + - ti,sysc-dra7-mcan + - ti,sysc-pruss + - const: ti,sysc + - items: + - const: ti,sysc + + reg: + description: + Interconnect target module control registers consisting of + REVISION, SYSCONFIG and SYSSTATUS registers as defined in the + Technical Reference Manual for the SoC. + minItems: 1 + maxItems: 3 + + reg-names: + description: + Interconnect target module control register names consisting + of "rev", "sysc" and "syss". + oneOf: + - minItems: 1 + items: + - const: rev + - const: sysc + - const: syss + - items: + - const: rev + - const: syss + - enum: [ sysc, syss ] + + power-domains: + description: Target module power domain if available. + maxItems: 1 + + clocks: + description: + Target module clocks consisting of one functional clock, one + interface clock, and up to 8 module specific optional clocks. + Some modules may have only the functional clock, and some have + no configurable clocks. + minItems: 1 + maxItems: 4 + + clock-names: + description: + Target module clock names like "fck", "ick", "optck1", "optck2" + if the clocks are configurable. + oneOf: + - enum: [ ick, fck, sys_clk ] + - items: + - const: fck + - enum: [ ick, dbclk, osc, sys_clk, dss_clk, ahclkx ] + - items: + - const: fck + - const: phy-clk + - const: phy-clk-div + - items: + - const: fck + - const: hdmi_clk + - const: sys_clk + - const: tv_clk + - items: + - const: fck + - const: ahclkx + - const: ahclkr + + resets: + description: + Target module reset bit in the RSTCTRL register if wired for the module. + Note that the other reset bits should be mapped for the child device + driver to use. + maxItems: 1 + + reset-names: + description: + Target module reset names in the RSTCTRL register, typically named + "rstctrl" if only one reset bit is wired for the module. + items: + - const: rstctrl + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + ranges: true + + dma-ranges: true + + ti,sysc-mask: + description: Mask of supported register bits for the SYSCONFIG register + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,sysc-midle: + description: List of hardware supported idle modes + $ref: /schemas/types.yaml#/definitions/uint32-array + + ti,sysc-sidle: + description: List of hardware supported idle modes + $ref: /schemas/types.yaml#/definitions/uint32-array + + ti,syss-mask: + description: Mask of supported register bits for the SYSSTATUS register + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,sysc-delay-us: + description: Delay needed after OCP softreset before accessing SYCONFIG + default: 0 + minimum: 0 + maximum: 2 + + ti,no-reset-on-init: + description: Interconnect target module shall not be reset at init + type: boolean + + ti,no-idle-on-init: + description: Interconnect target module shall not be idled at init + type: boolean + + ti,no-idle: + description: Interconnect target module shall not be idled + type: boolean + + ti,hwmods: + description: Interconnect module name to use with legacy hwmod data + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - '#address-cells' + - '#size-cells' + - ranges + +additionalProperties: + type: object + +examples: + - | + #include <dt-bindings/bus/ti-sysc.h> + #include <dt-bindings/clock/omap4.h> + + target-module@2b000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "usb_otg_hs"; + reg = <0x2b400 0x4>, + <0x2b404 0x4>, + <0x2b408 0x4>; + reg-names = "rev", "sysc", "syss"; + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2b000 0x1000>; + }; diff --git a/dts/Bindings/bus/xlnx,versal-net-cdx.yaml b/dts/Bindings/bus/xlnx,versal-net-cdx.yaml new file mode 100644 index 0000000000..7f62ffbdc2 --- /dev/null +++ b/dts/Bindings/bus/xlnx,versal-net-cdx.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD CDX bus controller + +description: | + CDX bus controller for AMD devices is implemented to dynamically + detect CDX bus and devices using the firmware. + The CDX bus manages multiple FPGA based hardware devices, which + can support network, crypto or any other specialized type of + devices. These FPGA based devices can be added/modified dynamically + on run-time. + + All devices on the CDX bus will have a unique streamid (for IOMMU) + and a unique device ID (for MSI) corresponding to a requestor ID + (one to one associated with the device). The streamid and deviceid + are used to configure SMMU and GIC-ITS respectively. + + iommu-map property is used to define the set of stream ids + corresponding to each device and the associated IOMMU. + + The MSI writes are accompanied by sideband data (Device ID). + The msi-map property is used to associate the devices with the + device ID as well as the associated ITS controller. + + rproc property (xlnx,rproc) is used to identify the remote processor + with which APU (Application Processor Unit) interacts to find out + the bus and device configuration. + +maintainers: + - Nipun Gupta <nipun.gupta@amd.com> + - Nikhil Agarwal <nikhil.agarwal@amd.com> + +properties: + compatible: + const: xlnx,versal-net-cdx + + iommu-map: true + + msi-map: true + + xlnx,rproc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the remoteproc_r5 rproc node using which APU interacts + with remote processor. + + ranges: true + + "#address-cells": + enum: [1, 2] + + "#size-cells": + enum: [1, 2] + +required: + - compatible + - iommu-map + - msi-map + - xlnx,rproc + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + cdx { + compatible = "xlnx,versal-net-cdx"; + #address-cells = <1>; + #size-cells = <1>; + /* define map for RIDs 250-259 */ + iommu-map = <250 &smmu 250 10>; + /* define msi map for RIDs 250-259 */ + msi-map = <250 &its 250 10>; + xlnx,rproc = <&remoteproc_r5>; + ranges; + }; |