diff options
Diffstat (limited to 'dts/Bindings/clock/fsl,plldig.yaml')
| -rw-r--r-- | dts/Bindings/clock/fsl,plldig.yaml | 26 |
1 files changed, 15 insertions, 11 deletions
diff --git a/dts/Bindings/clock/fsl,plldig.yaml b/dts/Bindings/clock/fsl,plldig.yaml index c8350030b3..88dd9c18db 100644 --- a/dts/Bindings/clock/fsl,plldig.yaml +++ b/dts/Bindings/clock/fsl,plldig.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock maintainers: - Wen He <wen.he_1@nxp.com> @@ -21,19 +21,21 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + '#clock-cells': const: 0 fsl,vco-hz: - description: Optional for VCO frequency of the PLL in Hertz. - The VCO frequency of this PLL cannot be changed during runtime - only at startup. Therefore, the output frequencies are very - limited and might not even closely match the requested frequency. - To work around this restriction the user may specify its own - desired VCO frequency for the PLL. - minimum: 650000000 - maximum: 1300000000 - default: 1188000000 + description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency + of this PLL cannot be changed during runtime only at startup. Therefore, + the output frequencies are very limited and might not even closely match + the requested frequency. To work around this restriction the user may specify + its own desired VCO frequency for the PLL. + minimum: 650000000 + maximum: 1300000000 + default: 1188000000 required: - compatible @@ -41,12 +43,14 @@ required: - clocks - '#clock-cells' +additionalProperties: false + examples: # Display PIXEL Clock node: - | dpclk: clock-display@f1f0000 { compatible = "fsl,ls1028a-plldig"; - reg = <0x0 0xf1f0000 0x0 0xffff>; + reg = <0xf1f0000 0xffff>; #clock-cells = <0>; clocks = <&osc_27m>; }; |