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-rw-r--r--dts/Bindings/clock/rockchip,rk3568-cru.yaml13
1 files changed, 13 insertions, 0 deletions
diff --git a/dts/Bindings/clock/rockchip,rk3568-cru.yaml b/dts/Bindings/clock/rockchip,rk3568-cru.yaml
index b2c2609782..fc7546f521 100644
--- a/dts/Bindings/clock/rockchip,rk3568-cru.yaml
+++ b/dts/Bindings/clock/rockchip,rk3568-cru.yaml
@@ -34,6 +34,19 @@ properties:
"#reset-cells":
const: 1
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
required:
- compatible
- reg