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-rw-r--r--dts/Bindings/clock/ti/davinci/pll.txt2
-rw-r--r--dts/Bindings/clock/ti/dra7-atl.txt2
-rw-r--r--dts/Bindings/clock/ti/gate.txt2
-rw-r--r--dts/Bindings/clock/ti/interface.txt2
-rw-r--r--dts/Bindings/clock/ti/mux.txt2
-rw-r--r--dts/Bindings/clock/ti/ti,clksel.yaml2
6 files changed, 6 insertions, 6 deletions
diff --git a/dts/Bindings/clock/ti/davinci/pll.txt b/dts/Bindings/clock/ti/davinci/pll.txt
index 36998e1848..c989453831 100644
--- a/dts/Bindings/clock/ti/davinci/pll.txt
+++ b/dts/Bindings/clock/ti/davinci/pll.txt
@@ -15,7 +15,7 @@ Required properties:
- for "ti,da850-pll1", shall be "clksrc"
Optional properties:
-- ti,clkmode-square-wave: Indicates that the the board is supplying a square
+- ti,clkmode-square-wave: Indicates that the board is supplying a square
wave input on the OSCIN pin instead of using a crystal oscillator.
This property is only valid when compatible = "ti,da850-pll0".
diff --git a/dts/Bindings/clock/ti/dra7-atl.txt b/dts/Bindings/clock/ti/dra7-atl.txt
index 21c002d28b..68504079f9 100644
--- a/dts/Bindings/clock/ti/dra7-atl.txt
+++ b/dts/Bindings/clock/ti/dra7-atl.txt
@@ -6,7 +6,7 @@ functional clock but can be configured to provide different clocks.
ATL can maintain a clock averages to some desired frequency based on the bws/aws
signals - can compensate the drift between the two ws signal.
-In order to provide the support for ATL and it's output clocks (which can be used
+In order to provide the support for ATL and its output clocks (which can be used
internally within the SoC or external components) two sets of bindings is needed:
Clock tree binding:
diff --git a/dts/Bindings/clock/ti/gate.txt b/dts/Bindings/clock/ti/gate.txt
index b4820b1de4..4982615c01 100644
--- a/dts/Bindings/clock/ti/gate.txt
+++ b/dts/Bindings/clock/ti/gate.txt
@@ -10,7 +10,7 @@ will be controlled instead and the corresponding hw-ops for
that is used.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
+[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
Required properties:
diff --git a/dts/Bindings/clock/ti/interface.txt b/dts/Bindings/clock/ti/interface.txt
index 94ec77dc3c..d3eb5ca92a 100644
--- a/dts/Bindings/clock/ti/interface.txt
+++ b/dts/Bindings/clock/ti/interface.txt
@@ -9,7 +9,7 @@ companion clock finding (match corresponding functional gate
clock) and hardware autoidle enable / disable.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
+[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
Required properties:
- compatible : shall be one of:
diff --git a/dts/Bindings/clock/ti/mux.txt b/dts/Bindings/clock/ti/mux.txt
index e17425a586..b33f641f10 100644
--- a/dts/Bindings/clock/ti/mux.txt
+++ b/dts/Bindings/clock/ti/mux.txt
@@ -8,7 +8,7 @@ parents, one of which can be selected as output. This clock does not
gate or adjust the parent rate via a divider or multiplier.
By default the "clocks" property lists the parents in the same order
-as they are programmed into the regster. E.g:
+as they are programmed into the register. E.g:
clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
diff --git a/dts/Bindings/clock/ti/ti,clksel.yaml b/dts/Bindings/clock/ti/ti,clksel.yaml
index c56f911fff..d525f96cf2 100644
--- a/dts/Bindings/clock/ti/ti,clksel.yaml
+++ b/dts/Bindings/clock/ti/ti,clksel.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Binding for TI clksel clock
+title: TI clksel clock
maintainers:
- Tony Lindgren <tony@atomide.com>