diff options
Diffstat (limited to 'dts/Bindings/clock')
| -rw-r--r-- | dts/Bindings/clock/amlogic,gxbb-clkc.txt | 7 | ||||
| -rw-r--r-- | dts/Bindings/clock/exynos3250-clock.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/clock/exynos5260-clock.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/clock/exynos5410-clock.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/clock/exynos5433-clock.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/clock/hi3660-clock.txt | 6 | ||||
| -rw-r--r-- | dts/Bindings/clock/qcom,a53pll.txt | 22 | ||||
| -rw-r--r-- | dts/Bindings/clock/qcom,spmi-clkdiv.txt | 59 | ||||
| -rw-r--r-- | dts/Bindings/clock/qoriq-clock.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/clock/silabs,si5351.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/clock/sprd.txt | 63 | ||||
| -rw-r--r-- | dts/Bindings/clock/sun8i-de2.txt | 5 |
12 files changed, 164 insertions, 8 deletions
diff --git a/dts/Bindings/clock/amlogic,gxbb-clkc.txt b/dts/Bindings/clock/amlogic,gxbb-clkc.txt index 9240407691..e2b377ed6f 100644 --- a/dts/Bindings/clock/amlogic,gxbb-clkc.txt +++ b/dts/Bindings/clock/amlogic,gxbb-clkc.txt @@ -5,8 +5,11 @@ controllers within the SoC. Required Properties: -- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC, - or "amlogic,gxl-clkc" for GXL and GXM SoC. +- compatible: should be: + "amlogic,gxbb-clkc" for GXBB SoC, + "amlogic,gxl-clkc" for GXL and GXM SoC, + "amlogic,axg-clkc" for AXG SoC. + - reg: physical base address of the clock controller and length of memory mapped region. diff --git a/dts/Bindings/clock/exynos3250-clock.txt b/dts/Bindings/clock/exynos3250-clock.txt index f1738b88c2..7441ed519f 100644 --- a/dts/Bindings/clock/exynos3250-clock.txt +++ b/dts/Bindings/clock/exynos3250-clock.txt @@ -32,7 +32,7 @@ Example 1: Examples of clock controller nodes are listed below. #clock-cells = <1>; }; - cmu_dmc: clock-controller@105C0000 { + cmu_dmc: clock-controller@105c0000 { compatible = "samsung,exynos3250-cmu-dmc"; reg = <0x105C0000 0x2000>; #clock-cells = <1>; diff --git a/dts/Bindings/clock/exynos5260-clock.txt b/dts/Bindings/clock/exynos5260-clock.txt index 5496b2fac4..c79d31f7f6 100644 --- a/dts/Bindings/clock/exynos5260-clock.txt +++ b/dts/Bindings/clock/exynos5260-clock.txt @@ -180,7 +180,7 @@ Example 2: UART controller node that consumes the clock generated by the peri clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. - serial@12C00000 { + serial@12c00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; interrupts = <0 146 0>; diff --git a/dts/Bindings/clock/exynos5410-clock.txt b/dts/Bindings/clock/exynos5410-clock.txt index c68b0d29b3..217beb27c3 100644 --- a/dts/Bindings/clock/exynos5410-clock.txt +++ b/dts/Bindings/clock/exynos5410-clock.txt @@ -41,7 +41,7 @@ Example 2: UART controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. - serial@12C20000 { + serial@12c20000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; interrupts = <0 51 0>; diff --git a/dts/Bindings/clock/exynos5433-clock.txt b/dts/Bindings/clock/exynos5433-clock.txt index c473dd38dd..50d5897c98 100644 --- a/dts/Bindings/clock/exynos5433-clock.txt +++ b/dts/Bindings/clock/exynos5433-clock.txt @@ -472,7 +472,7 @@ Example 2: Examples of clock controller nodes are listed below. Example 3: UART controller node that consumes the clock generated by the clock controller. - serial_0: serial@14C10000 { + serial_0: serial@14c10000 { compatible = "samsung,exynos5433-uart"; reg = <0x14C10000 0x100>; interrupts = <0 421 0>; diff --git a/dts/Bindings/clock/hi3660-clock.txt b/dts/Bindings/clock/hi3660-clock.txt index 0035a7ecaf..946da7cee5 100644 --- a/dts/Bindings/clock/hi3660-clock.txt +++ b/dts/Bindings/clock/hi3660-clock.txt @@ -13,12 +13,18 @@ Required Properties: - "hisilicon,hi3660-pmuctrl" - "hisilicon,hi3660-sctrl" - "hisilicon,hi3660-iomcu" + - "hisilicon,hi3660-stub-clk" - reg: physical base address of the controller and length of memory mapped region. - #clock-cells: should be 1. +Optional Properties: + +- mboxes: Phandle to the mailbox for sending message to MCU. + (See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info) + Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. diff --git a/dts/Bindings/clock/qcom,a53pll.txt b/dts/Bindings/clock/qcom,a53pll.txt new file mode 100644 index 0000000000..e3fa8118ea --- /dev/null +++ b/dts/Bindings/clock/qcom,a53pll.txt @@ -0,0 +1,22 @@ +Qualcomm MSM8916 A53 PLL Binding +-------------------------------- +The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies +above 1GHz. + +Required properties : +- compatible : Shall contain only one of the following: + + "qcom,msm8916-a53pll" + +- reg : shall contain base register location and length + +- #clock-cells : must be set to <0> + +Example: + + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0xb016000 0x40>; + #clock-cells = <0>; + }; + diff --git a/dts/Bindings/clock/qcom,spmi-clkdiv.txt b/dts/Bindings/clock/qcom,spmi-clkdiv.txt new file mode 100644 index 0000000000..7474aba366 --- /dev/null +++ b/dts/Bindings/clock/qcom,spmi-clkdiv.txt @@ -0,0 +1,59 @@ +Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv) + +clkdiv configures the clock frequency of a set of outputs on the PMIC. +These clocks are typically wired through alternate functions on +gpio pins. + +======================= +Properties +======================= + +- compatible + Usage: required + Value type: <string> + Definition: must be "qcom,spmi-clkdiv". + +- reg + Usage: required + Value type: <prop-encoded-array> + Definition: base address of CLKDIV peripherals. + +- qcom,num-clkdivs + Usage: required + Value type: <u32> + Definition: number of CLKDIV peripherals. + +- clocks: + Usage: required + Value type: <prop-encoded-array> + Definition: reference to the xo clock. + +- clock-names: + Usage: required + Value type: <stringlist> + Definition: must be "xo". + +- #clock-cells: + Usage: required + Value type: <u32> + Definition: shall contain 1. + +======= +Example +======= + +pm8998_clk_divs: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <3>; + clocks = <&xo_board>; + clock-names = "xo"; + + assigned-clocks = <&pm8998_clk_divs 1>, + <&pm8998_clk_divs 2>, + <&pm8998_clk_divs 3>; + assigned-clock-rates = <9600000>, + <9600000>, + <9600000>; +}; diff --git a/dts/Bindings/clock/qoriq-clock.txt b/dts/Bindings/clock/qoriq-clock.txt index 6498e1fdbb..97f46adac8 100644 --- a/dts/Bindings/clock/qoriq-clock.txt +++ b/dts/Bindings/clock/qoriq-clock.txt @@ -78,6 +78,7 @@ second cell is the clock index for the specified type. 2 hwaccel index (n in CLKCGnHWACSR) 3 fman 0 for fm1, 1 for fm2 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 + 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8 5 coreclk must be 0 3. Example diff --git a/dts/Bindings/clock/silabs,si5351.txt b/dts/Bindings/clock/silabs,si5351.txt index a6c4ef343b..f00191cad8 100644 --- a/dts/Bindings/clock/silabs,si5351.txt +++ b/dts/Bindings/clock/silabs,si5351.txt @@ -49,6 +49,7 @@ Optional child node properties: - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth divider. - silabs,pll-master: boolean, multisynth can change pll frequency. +- silabs,pll-reset: boolean, clock output can reset its pll. - silabs,disable-state : clock output disable state, shall be 0 = clock output is driven LOW when disabled 1 = clock output is driven HIGH when disabled diff --git a/dts/Bindings/clock/sprd.txt b/dts/Bindings/clock/sprd.txt new file mode 100644 index 0000000000..e9d179e882 --- /dev/null +++ b/dts/Bindings/clock/sprd.txt @@ -0,0 +1,63 @@ +Spreadtrum Clock Binding +------------------------ + +Required properties: +- compatible: should contain the following compatible strings: + - "sprd,sc9860-pmu-gate" + - "sprd,sc9860-pll" + - "sprd,sc9860-ap-clk" + - "sprd,sc9860-aon-prediv" + - "sprd,sc9860-apahb-gate" + - "sprd,sc9860-aon-gate" + - "sprd,sc9860-aonsecure-clk" + - "sprd,sc9860-agcp-gate" + - "sprd,sc9860-gpu-clk" + - "sprd,sc9860-vsp-clk" + - "sprd,sc9860-vsp-gate" + - "sprd,sc9860-cam-clk" + - "sprd,sc9860-cam-gate" + - "sprd,sc9860-disp-clk" + - "sprd,sc9860-disp-gate" + - "sprd,sc9860-apapb-gate" + +- #clock-cells: must be 1 + +- clocks : Should be the input parent clock(s) phandle for the clock, this + property here just simply shows which clock group the clocks' + parents are in, since each clk node would represent many clocks + which are defined in the driver. The detailed dependency + relationship (i.e. how many parents and which are the parents) + are implemented in driver code. + +Optional properties: + +- reg: Contain the registers base address and length. It must be configured + only if no 'sprd,syscon' under the node. + +- sprd,syscon: phandle to the syscon which is in the same address area with + the clock, and so we can get regmap for the clocks from the + syscon device. + +Example: + + pmu_gate: pmu-gate { + compatible = "sprd,sc9860-pmu-gate"; + sprd,syscon = <&pmu_regs>; + clocks = <&ext_26m>; + #clock-cells = <1>; + }; + + pll: pll { + compatible = "sprd,sc9860-pll"; + sprd,syscon = <&ana_regs>; + clocks = <&pmu_gate 0>; + #clock-cells = <1>; + }; + + ap_clk: clock-controller@20000000 { + compatible = "sprd,sc9860-ap-clk"; + reg = <0 0x20000000 0 0x400>; + clocks = <&ext_26m>, <&pll 0>, + <&pmu_gate 0>; + #clock-cells = <1>; + }; diff --git a/dts/Bindings/clock/sun8i-de2.txt b/dts/Bindings/clock/sun8i-de2.txt index 631d27cd89..f2fa87c476 100644 --- a/dts/Bindings/clock/sun8i-de2.txt +++ b/dts/Bindings/clock/sun8i-de2.txt @@ -4,13 +4,14 @@ Allwinner Display Engine 2.0 Clock Control Binding Required properties : - compatible: must contain one of the following compatibles: - "allwinner,sun8i-a83t-de2-clk" + - "allwinner,sun8i-h3-de2-clk" - "allwinner,sun8i-v3s-de2-clk" - "allwinner,sun50i-h5-de2-clk" - reg: Must contain the registers base address and length - clocks: phandle to the clocks feeding the display engine subsystem. Three are needed: - - "mod": the display engine module clock + - "mod": the display engine module clock (on A83T it's the DE PLL) - "bus": the bus clock for the whole display engine subsystem - clock-names: Must contain the clock names described just above - resets: phandle to the reset control for the display engine subsystem. @@ -19,7 +20,7 @@ Required properties : Example: de2_clocks: clock@1000000 { - compatible = "allwinner,sun8i-a83t-de2-clk"; + compatible = "allwinner,sun8i-h3-de2-clk"; reg = <0x01000000 0x100000>; clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; |