summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/fpga/lattice-ice40-fpga-mgr.txt
diff options
context:
space:
mode:
Diffstat (limited to 'dts/Bindings/fpga/lattice-ice40-fpga-mgr.txt')
-rw-r--r--dts/Bindings/fpga/lattice-ice40-fpga-mgr.txt21
1 files changed, 21 insertions, 0 deletions
diff --git a/dts/Bindings/fpga/lattice-ice40-fpga-mgr.txt b/dts/Bindings/fpga/lattice-ice40-fpga-mgr.txt
new file mode 100644
index 0000000..4dc4124
--- /dev/null
+++ b/dts/Bindings/fpga/lattice-ice40-fpga-mgr.txt
@@ -0,0 +1,21 @@
+Lattice iCE40 FPGA Manager
+
+Required properties:
+- compatible: Should contain "lattice,ice40-fpga-mgr"
+- reg: SPI chip select
+- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
+- cdone-gpios: GPIO input connected to CDONE pin
+- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note
+ that unless the GPIO is held low during startup, the
+ FPGA will enter Master SPI mode and drive SCK with a
+ clock signal potentially jamming other devices on the
+ bus until the firmware is loaded.
+
+Example:
+ fpga: fpga@0 {
+ compatible = "lattice,ice40-fpga-mgr";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+ };