diff options
Diffstat (limited to 'dts/Bindings/interrupt-controller/arm,gic-v3.yaml')
-rw-r--r-- | dts/Bindings/interrupt-controller/arm,gic-v3.yaml | 42 |
1 files changed, 34 insertions, 8 deletions
diff --git a/dts/Bindings/interrupt-controller/arm,gic-v3.yaml b/dts/Bindings/interrupt-controller/arm,gic-v3.yaml index c84f9fe7f2..0f4a062c9d 100644 --- a/dts/Bindings/interrupt-controller/arm,gic-v3.yaml +++ b/dts/Bindings/interrupt-controller/arm,gic-v3.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Generic Interrupt Controller, version 3 maintainers: - - Marc Zyngier <marc.zyngier@arm.com> + - Marc Zyngier <maz@kernel.org> description: | AArch64 SMP cores are often associated with a GICv3, providing Private @@ -49,7 +49,7 @@ properties: The 2nd cell contains the interrupt number for the interrupt type. SPI interrupts are in the range [0-987]. PPI interrupts are in the - range [0-15]. Extented SPI interrupts are in the range [0-1023]. + range [0-15]. Extended SPI interrupts are in the range [0-1023]. Extended PPI interrupts are in the range [0-127]. The 3rd cell is the flags, encoded as follows: @@ -78,7 +78,11 @@ properties: - GIC Hypervisor interface (GICH) - GIC Virtual CPU interface (GICV) - GICC, GICH and GICV are optional. + GICC, GICH and GICV are optional, but must be described if the CPUs + support them. Examples of such CPUs are ARM's implementations of the + ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and + A73 (this list is not exhaustive). + minItems: 2 maxItems: 4096 # Should be enough? @@ -102,9 +106,15 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 4096 + dma-noncoherent: + description: + Present if the GIC redistributors permit programming shareability + and cacheability attributes but are connected to a non-coherent + downstream interconnect. + msi-controller: description: - Only present if the Message Based Interrupt functionnality is + Only present if the Message Based Interrupt functionality is being exposed by the HW, and the mbi-ranges property present. mbi-ranges: @@ -129,15 +139,19 @@ properties: ppi-partitions: type: object + additionalProperties: false description: PPI affinity can be expressed as a single "ppi-partitions" node, containing a set of sub-nodes. patternProperties: "^interrupt-partition-[0-9]+$": type: object + additionalProperties: false properties: affinity: $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 description: Should be a list of phandles to CPU nodes (as described in Documentation/devicetree/bindings/arm/cpus.yaml). @@ -158,13 +172,18 @@ properties: resets: maxItems: 1 + mediatek,broken-save-restore-fw: + type: boolean + description: + Asserts that the firmware on this device has issues saving and restoring + GICR registers when the GIC redistributors are powered off. + dependencies: mbi-ranges: [ msi-controller ] msi-controller: [ mbi-ranges ] required: - compatible - - interrupts - reg patternProperties: @@ -180,6 +199,12 @@ patternProperties: compatible: const: arm,gic-v3-its + dma-noncoherent: + description: + Present if the GIC ITS permits programming shareability and + cacheability attributes but is connected to a non-coherent + downstream interconnect. + msi-controller: true "#msi-cells": @@ -239,6 +264,7 @@ examples: }; }; + - | interrupt-controller@2c010000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; @@ -254,7 +280,7 @@ examples: <0x2c040000 0x2000>, // GICC <0x2c060000 0x2000>, // GICH <0x2c080000 0x2000>; // GICV - interrupts = <1 9 4>; + interrupts = <1 9 4 0>; msi-controller@2c200000 { compatible = "arm,gic-v3-its"; @@ -272,11 +298,11 @@ examples: ppi-partitions { part0: interrupt-partition-0 { - affinity = <&cpu0 &cpu2>; + affinity = <&cpu0>, <&cpu2>; }; part1: interrupt-partition-1 { - affinity = <&cpu1 &cpu3>; + affinity = <&cpu1>, <&cpu3>; }; }; }; |