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-rw-r--r--dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt1
1 files changed, 0 insertions, 1 deletions
diff --git a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
index b47a8a0..f5baecc 100644
--- a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
@@ -7,7 +7,6 @@ Required properties:
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
-- interrupt-parent : phandle of the CPU interrupt controller.
- interrupts : Specifies the CPU interrupt the controller is connected to.
Example: