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-rw-r--r--dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt1
1 files changed, 0 insertions, 1 deletions
diff --git a/dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt b/dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt
index 42bb796..ee3f9c3 100644
--- a/dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt
+++ b/dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt
@@ -46,7 +46,6 @@ C6X Interrupt Chips
- interrupt-controller
- #interrupt-cells: <1>
- reg: base address and size of register area
- - interrupt-parent: must be core interrupt controller
- interrupts: This should have four cells; one for each interrupt combiner.
The cells contain the core priority interrupt to which the
corresponding combiner output is wired.