diff options
Diffstat (limited to 'dts/Bindings/mailbox')
-rw-r--r-- | dts/Bindings/mailbox/arm,mhu.yaml | 135 | ||||
-rw-r--r-- | dts/Bindings/mailbox/arm-mhu.txt | 43 | ||||
-rw-r--r-- | dts/Bindings/mailbox/fsl,mu.yaml | 6 | ||||
-rw-r--r-- | dts/Bindings/mailbox/mtk-gce.txt | 2 | ||||
-rw-r--r-- | dts/Bindings/mailbox/omap-mailbox.txt | 2 | ||||
-rw-r--r-- | dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 |
6 files changed, 143 insertions, 46 deletions
diff --git a/dts/Bindings/mailbox/arm,mhu.yaml b/dts/Bindings/mailbox/arm,mhu.yaml new file mode 100644 index 0000000000..d43791a2dd --- /dev/null +++ b/dts/Bindings/mailbox/arm,mhu.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/arm,mhu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM MHU Mailbox Controller + +maintainers: + - Jassi Brar <jaswinder.singh@linaro.org> + +description: | + The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3 + independent channels/links to communicate with remote processor(s). MHU links + are hardwired on a platform. A link raises interrupt for any received data. + However, there is no specified way of knowing if the sent data has been read + by the remote. This driver assumes the sender polls STAT register and the + remote clears it after having read the data. The last channel is specified to + be a 'Secure' resource, hence can't be used by Linux running NS. + + The MHU hardware also allows operations in doorbell mode. The MHU drives the + interrupt signal using a 32-bit register, with all 32-bits logically ORed + together. It provides a set of registers to enable software to set, clear and + check the status of each of the bits of this register independently. The use + of 32 bits per interrupt line enables software to provide more information + about the source of the interrupt. For example, each bit of the register can + be associated with a type of event that can contribute to raising the + interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote + processor. + +# We need a select here so we don't match all nodes with 'arm,primecell' +select: + properties: + compatible: + contains: + enum: + - arm,mhu + - arm,mhu-doorbell + required: + - compatible + +properties: + compatible: + oneOf: + - description: Data transfer mode + items: + - const: arm,mhu + - const: arm,primecell + + - description: Doorbell mode + items: + - const: arm,mhu-doorbell + - const: arm,primecell + + + reg: + maxItems: 1 + + interrupts: + items: + - description: low-priority non-secure + - description: high-priority non-secure + - description: Secure + maxItems: 3 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + '#mbox-cells': + description: | + Set to 1 in data transfer mode and represents index of the channel. + Set to 2 in doorbell mode and represents index of the channel and doorbell + number. + enum: [ 1, 2 ] + +required: + - compatible + - reg + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + # Data transfer mode. + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mhuA: mailbox@2b1f0000 { + #mbox-cells = <1>; + compatible = "arm,mhu", "arm,primecell"; + reg = <0 0x2b1f0000 0 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + mhu_client_scb: scb@2e000000 { + compatible = "fujitsu,mb86s70-scb-1.0"; + reg = <0 0x2e000000 0 0x4000>; + mboxes = <&mhuA 1>; /* HP-NonSecure */ + }; + }; + + # Doorbell mode. + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mhuB: mailbox@2b2f0000 { + #mbox-cells = <2>; + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0 0x2b2f0000 0 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + mhu_client_scpi: scpi@2f000000 { + compatible = "arm,scpi"; + reg = <0 0x2f000000 0 0x200>; + mboxes = <&mhuB 1 4>; /* HP-NonSecure, 5th doorbell */ + }; + }; diff --git a/dts/Bindings/mailbox/arm-mhu.txt b/dts/Bindings/mailbox/arm-mhu.txt deleted file mode 100644 index 4971f03f0b..0000000000 --- a/dts/Bindings/mailbox/arm-mhu.txt +++ /dev/null @@ -1,43 +0,0 @@ -ARM MHU Mailbox Driver -====================== - -The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has -3 independent channels/links to communicate with remote processor(s). - MHU links are hardwired on a platform. A link raises interrupt for any -received data. However, there is no specified way of knowing if the sent -data has been read by the remote. This driver assumes the sender polls -STAT register and the remote clears it after having read the data. -The last channel is specified to be a 'Secure' resource, hence can't be -used by Linux running NS. - -Mailbox Device Node: -==================== - -Required properties: --------------------- -- compatible: Shall be "arm,mhu" & "arm,primecell" -- reg: Contains the mailbox register address range (base - address and length) -- #mbox-cells Shall be 1 - the index of the channel needed. -- interrupts: Contains the interrupt information corresponding to - each of the 3 links of MHU. - -Example: --------- - - mhu: mailbox@2b1f0000 { - #mbox-cells = <1>; - compatible = "arm,mhu", "arm,primecell"; - reg = <0 0x2b1f0000 0x1000>; - interrupts = <0 36 4>, /* LP-NonSecure */ - <0 35 4>, /* HP-NonSecure */ - <0 37 4>; /* Secure */ - clocks = <&clock 0 2 1>; - clock-names = "apb_pclk"; - }; - - mhu_client: scb@2e000000 { - compatible = "fujitsu,mb86s70-scb-1.0"; - reg = <0 0x2e000000 0x4000>; - mboxes = <&mhu 1>; /* HP-NonSecure */ - }; diff --git a/dts/Bindings/mailbox/fsl,mu.yaml b/dts/Bindings/mailbox/fsl,mu.yaml index 8a3470b64d..15cef82cd3 100644 --- a/dts/Bindings/mailbox/fsl,mu.yaml +++ b/dts/Bindings/mailbox/fsl,mu.yaml @@ -38,8 +38,9 @@ properties: - const: fsl,imx6sx-mu - description: To communicate with i.MX8 SCU with fast IPC items: - - const: fsl,imx8qxp-mu - const: fsl,imx8-mu-scu + - const: fsl,imx8qxp-mu + - const: fsl,imx6sx-mu reg: maxItems: 1 @@ -71,6 +72,9 @@ properties: description: boolean, if present, means it is for side B MU. type: boolean + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/mailbox/mtk-gce.txt b/dts/Bindings/mailbox/mtk-gce.txt index cf48cd806e..7771ecaac5 100644 --- a/dts/Bindings/mailbox/mtk-gce.txt +++ b/dts/Bindings/mailbox/mtk-gce.txt @@ -47,7 +47,7 @@ Example: interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; - #mbox-cells = <3>; + #mbox-cells = <2>; }; Example for a client device: diff --git a/dts/Bindings/mailbox/omap-mailbox.txt b/dts/Bindings/mailbox/omap-mailbox.txt index 35c3f56b7f..5fe80c1c19 100644 --- a/dts/Bindings/mailbox/omap-mailbox.txt +++ b/dts/Bindings/mailbox/omap-mailbox.txt @@ -69,7 +69,7 @@ The following are mandatory properties for the K3 AM65x and J721E SoCs only: the interrupt routes between the IP and the main GIC controllers. See the following binding for additional details, - Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt + Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml Child Nodes: ============ diff --git a/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml b/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml index 8f810fc5c1..ffd09b664f 100644 --- a/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -16,6 +16,7 @@ maintainers: properties: compatible: enum: + - qcom,ipq6018-apcs-apps-global - qcom,ipq8074-apcs-apps-global - qcom,msm8916-apcs-kpss-global - qcom,msm8994-apcs-kpss-global |