diff options
Diffstat (limited to 'dts/Bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml')
| -rw-r--r-- | dts/Bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/dts/Bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml b/dts/Bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml index 8f72e2f858..b74ad9a330 100644 --- a/dts/Bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml +++ b/dts/Bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml @@ -8,12 +8,11 @@ title: Zynq A05 DDR Memory Controller maintainers: - Krzysztof Kozlowski <krzk@kernel.org> - - Manish Narani <manish.narani@xilinx.com> - - Michal Simek <michal.simek@xilinx.com> + - Michal Simek <michal.simek@amd.com> description: The Zynq DDR ECC controller has an optional ECC support in half-bus width - (16-bit) configuration. It is cappable of correcting single bit ECC errors + (16-bit) configuration. It is capable of correcting single bit ECC errors and detecting double bit ECC errors. properties: |