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-rw-r--r--dts/Bindings/mmc/amlogic,meson-mx-sdhc.yaml68
-rw-r--r--dts/Bindings/mmc/arasan,sdhci.txt135
-rw-r--r--dts/Bindings/mmc/arasan,sdhci.yaml299
-rw-r--r--dts/Bindings/mmc/aspeed,sdhci.yaml4
-rw-r--r--dts/Bindings/mmc/cdns,sdhci.yaml79
-rw-r--r--dts/Bindings/mmc/fsl-imx-esdhc.txt67
-rw-r--r--dts/Bindings/mmc/fsl-imx-esdhc.yaml124
-rw-r--r--dts/Bindings/mmc/fsl-imx-mmc.txt23
-rw-r--r--dts/Bindings/mmc/fsl-imx-mmc.yaml53
-rw-r--r--dts/Bindings/mmc/ingenic,mmc.yaml79
-rw-r--r--dts/Bindings/mmc/jz4740.txt41
-rw-r--r--dts/Bindings/mmc/mmc-controller.yaml42
-rw-r--r--dts/Bindings/mmc/mmc-pwrseq-emmc.txt25
-rw-r--r--dts/Bindings/mmc/mmc-pwrseq-emmc.yaml46
-rw-r--r--dts/Bindings/mmc/mmc-pwrseq-sd8787.txt16
-rw-r--r--dts/Bindings/mmc/mmc-pwrseq-sd8787.yaml39
-rw-r--r--dts/Bindings/mmc/mmc-pwrseq-simple.txt31
-rw-r--r--dts/Bindings/mmc/mmc-pwrseq-simple.yaml62
-rw-r--r--dts/Bindings/mmc/mtk-sd.txt1
-rw-r--r--dts/Bindings/mmc/mxs-mmc.txt27
-rw-r--r--dts/Bindings/mmc/mxs-mmc.yaml58
-rw-r--r--dts/Bindings/mmc/owl-mmc.yaml2
-rw-r--r--dts/Bindings/mmc/renesas,mmcif.txt5
-rw-r--r--dts/Bindings/mmc/renesas,sdhi.txt113
-rw-r--r--dts/Bindings/mmc/renesas,sdhi.yaml191
-rw-r--r--dts/Bindings/mmc/rockchip-dw-mshc.yaml24
-rw-r--r--dts/Bindings/mmc/sdhci-am654.txt1
-rw-r--r--dts/Bindings/mmc/sdhci-msm.txt32
-rw-r--r--dts/Bindings/mmc/sdhci-pxa.txt50
-rw-r--r--dts/Bindings/mmc/sdhci-pxa.yaml102
-rw-r--r--dts/Bindings/mmc/socionext,uniphier-sd.yaml14
-rw-r--r--dts/Bindings/mmc/synopsys-dw-mshc-common.yaml14
32 files changed, 1239 insertions, 628 deletions
diff --git a/dts/Bindings/mmc/amlogic,meson-mx-sdhc.yaml b/dts/Bindings/mmc/amlogic,meson-mx-sdhc.yaml
new file mode 100644
index 0000000..0cd74c3
--- /dev/null
+++ b/dts/Bindings/mmc/amlogic,meson-mx-sdhc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson SDHC controller Device Tree Bindings
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+maintainers:
+ - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+description: |
+ The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC
+ card interface with 1/4/8-bit bus width.
+ It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock).
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - amlogic,meson8-sdhc
+ - amlogic,meson8b-sdhc
+ - amlogic,meson8m2-sdhc
+ - const: amlogic,meson-mx-sdhc
+
+ reg:
+ minItems: 1
+
+ interrupts:
+ minItems: 1
+
+ clocks:
+ minItems: 5
+
+ clock-names:
+ items:
+ - const: clkin0
+ - const: clkin1
+ - const: clkin2
+ - const: clkin3
+ - const: pclk
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ sdhc: mmc@8e00 {
+ compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
+ reg = <0x8e00 0x42>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>,
+ <&fclk_div4>,
+ <&fclk_div3>,
+ <&fclk_div5>,
+ <&sdhc_pclk>;
+ clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
+ };
diff --git a/dts/Bindings/mmc/arasan,sdhci.txt b/dts/Bindings/mmc/arasan,sdhci.txt
deleted file mode 100644
index 428685e..0000000
--- a/dts/Bindings/mmc/arasan,sdhci.txt
+++ /dev/null
@@ -1,135 +0,0 @@
-Device Tree Bindings for the Arasan SDHCI Controller
-
- The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
- Only deviations are documented here.
-
- [1] Documentation/devicetree/bindings/mmc/mmc.txt
- [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
- [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
-
-Required Properties:
- - compatible: Compatibility string. One of:
- - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
- - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
- - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
- - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
- For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
- For this device it is strongly suggested to include clock-output-names and
- #clock-cells.
- - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
- Note: This binding has been deprecated and moved to [5].
- - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
- For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
- For this device it is strongly suggested to include arasan,soc-ctl-syscon.
-
- [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
-
- - reg: From mmc bindings: Register location and length.
- - clocks: From clock bindings: Handles to clock inputs.
- - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
- - interrupts: Interrupt specifier
-
-Required Properties for "arasan,sdhci-5.1":
- - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
- - phy-names: MUST be "phy_arasan".
-
-Optional Properties:
- - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
- used to access core corecfg registers. Offsets of registers in this
- syscon are determined based on the main compatible string for the device.
- - clock-output-names: If specified, this will be the name of the card clock
- which will be exposed by this device. Required if #clock-cells is
- specified.
- - #clock-cells: If specified this should be the value <0> or <1>. With this
- property in place we will export one or two clocks representing the Card
- Clock. These clocks are expected to be consumed by our PHY.
- - xlnx,fails-without-test-cd: when present, the controller doesn't work when
- the CD line is not connected properly, and the line is not connected
- properly. Test mode can be used to force the controller to function.
- - xlnx,int-clock-stable-broken: when present, the controller always reports
- that the internal clock is stable even when it is not.
-
- - xlnx,mio-bank: When specified, this will indicate the MIO bank number in
- which the command and data lines are configured. If not specified, driver
- will assume this as 0.
-
-Example:
- sdhci@e0100000 {
- compatible = "arasan,sdhci-8.9a";
- reg = <0xe0100000 0x1000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clkc 21>, <&clkc 32>;
- interrupt-parent = <&gic>;
- interrupts = <0 24 4>;
- } ;
-
- sdhci@e2800000 {
- compatible = "arasan,sdhci-5.1";
- reg = <0xe2800000 0x1000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&cru 8>, <&cru 18>;
- interrupt-parent = <&gic>;
- interrupts = <0 24 4>;
- phys = <&emmc_phy>;
- phy-names = "phy_arasan";
- } ;
-
- sdhci: sdhci@fe330000 {
- compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
- reg = <0x0 0xfe330000 0x0 0x10000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
- clock-names = "clk_xin", "clk_ahb";
- arasan,soc-ctl-syscon = <&grf>;
- assigned-clocks = <&cru SCLK_EMMC>;
- assigned-clock-rates = <200000000>;
- clock-output-names = "emmc_cardclock";
- phys = <&emmc_phy>;
- phy-names = "phy_arasan";
- #clock-cells = <0>;
- };
-
- sdhci: mmc@ff160000 {
- compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
- interrupt-parent = <&gic>;
- interrupts = <0 48 4>;
- reg = <0x0 0xff160000 0x0 0x1000>;
- clocks = <&clk200>, <&clk200>;
- clock-names = "clk_xin", "clk_ahb";
- clock-output-names = "clk_out_sd0", "clk_in_sd0";
- #clock-cells = <1>;
- clk-phase-sd-hs = <63>, <72>;
- };
-
- emmc: sdhci@ec700000 {
- compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
- reg = <0xec700000 0x300>;
- interrupt-parent = <&ioapic1>;
- interrupts = <44 1>;
- clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
- <&cgu0 LGM_GCLK_EMMC>;
- clock-names = "clk_xin", "clk_ahb", "gate";
- clock-output-names = "emmc_cardclock";
- #clock-cells = <0>;
- phys = <&emmc_phy>;
- phy-names = "phy_arasan";
- arasan,soc-ctl-syscon = <&sysconf>;
- };
-
- sdxc: sdhci@ec600000 {
- compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
- reg = <0xec600000 0x300>;
- interrupt-parent = <&ioapic1>;
- interrupts = <43 1>;
- clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
- <&cgu0 LGM_GCLK_SDXC>;
- clock-names = "clk_xin", "clk_ahb", "gate";
- clock-output-names = "sdxc_cardclock";
- #clock-cells = <0>;
- phys = <&sdxc_phy>;
- phy-names = "phy_arasan";
- arasan,soc-ctl-syscon = <&sysconf>;
- };
diff --git a/dts/Bindings/mmc/arasan,sdhci.yaml b/dts/Bindings/mmc/arasan,sdhci.yaml
new file mode 100644
index 0000000..5887c91
--- /dev/null
+++ b/dts/Bindings/mmc/arasan,sdhci.yaml
@@ -0,0 +1,299 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Device Tree Bindings for the Arasan SDHCI Controller
+
+maintainers:
+ - Adrian Hunter <adrian.hunter@intel.com>
+
+allOf:
+ - $ref: "mmc-controller.yaml#"
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: arasan,sdhci-5.1
+ then:
+ required:
+ - phys
+ - phy-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - xlnx,zynqmp-8.9a
+ - xlnx,versal-8.9a
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: clk_out_sd0
+ - const: clk_in_sd0
+
+properties:
+ compatible:
+ oneOf:
+ - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
+ - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
+ - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
+ - items:
+ - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
+ - const: arasan,sdhci-5.1
+ description:
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+ - items:
+ - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
+ - const: arasan,sdhci-8.9a
+ description:
+ For this device it is strongly suggested to include
+ clock-output-names and '#clock-cells'.
+ - items:
+ - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
+ - const: arasan,sdhci-8.9a
+ description:
+ For this device it is strongly suggested to include
+ clock-output-names and '#clock-cells'.
+ - items:
+ - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
+ - const: arasan,sdhci-5.1
+ description:
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+ - items:
+ - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
+ - const: arasan,sdhci-5.1
+ description:
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+ - items:
+ - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
+ - const: arasan,sdhci-5.1
+ description:
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+ - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
+ description:
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+ - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
+ description:
+ For this device it is strongly suggested to include
+ arasan,soc-ctl-syscon.
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ items:
+ - const: clk_xin
+ - const: clk_ahb
+ - const: gate
+
+ interrupts:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: phy_arasan
+
+ arasan,soc-ctl-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ A phandle to a syscon device (see ../mfd/syscon.txt) used to access
+ core corecfg registers. Offsets of registers in this syscon are
+ determined based on the main compatible string for the device.
+
+ clock-output-names:
+ minItems: 1
+ maxItems: 2
+ description:
+ Name of the card clock which will be exposed by this device.
+
+ '#clock-cells':
+ enum: [0, 1]
+ description:
+ With this property in place we will export one or two clocks
+ representing the Card Clock. These clocks are expected to be
+ consumed by our PHY.
+
+ xlnx,fails-without-test-cd:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ When present, the controller doesn't work when the CD line is not
+ connected properly, and the line is not connected properly.
+ Test mode can be used to force the controller to function.
+
+ xlnx,int-clock-stable-broken:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ When present, the controller always reports that the internal clock
+ is stable even when it is not.
+
+ xlnx,mio-bank:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2]
+ default: 0
+ description:
+ The MIO bank number in which the command and data lines are configured.
+
+dependencies:
+ clock-output-names: [ '#clock-cells' ]
+ '#clock-cells': [ clock-output-names ]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@e0100000 {
+ compatible = "arasan,sdhci-8.9a";
+ reg = <0xe0100000 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clkc 21>, <&clkc 32>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 24 4>;
+ };
+
+ - |
+ mmc@e2800000 {
+ compatible = "arasan,sdhci-5.1";
+ reg = <0xe2800000 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&cru 8>, <&cru 18>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 24 4>;
+ phys = <&emmc_phy>;
+ phy-names = "phy_arasan";
+ };
+
+ - |
+ #include <dt-bindings/clock/rk3399-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ mmc@fe330000 {
+ compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
+ reg = <0xfe330000 0x10000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
+ clock-names = "clk_xin", "clk_ahb";
+ arasan,soc-ctl-syscon = <&grf>;
+ assigned-clocks = <&cru SCLK_EMMC>;
+ assigned-clock-rates = <200000000>;
+ clock-output-names = "emmc_cardclock";
+ phys = <&emmc_phy>;
+ phy-names = "phy_arasan";
+ #clock-cells = <0>;
+ };
+
+ - |
+ mmc@ff160000 {
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ interrupt-parent = <&gic>;
+ interrupts = <0 48 4>;
+ reg = <0xff160000 0x1000>;
+ clocks = <&clk200>, <&clk200>;
+ clock-names = "clk_xin", "clk_ahb";
+ clock-output-names = "clk_out_sd0", "clk_in_sd0";
+ #clock-cells = <1>;
+ clk-phase-sd-hs = <63>, <72>;
+ };
+
+ - |
+ mmc@f1040000 {
+ compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
+ interrupt-parent = <&gic>;
+ interrupts = <0 126 4>;
+ reg = <0xf1040000 0x10000>;
+ clocks = <&clk200>, <&clk200>;
+ clock-names = "clk_xin", "clk_ahb";
+ clock-output-names = "clk_out_sd0", "clk_in_sd0";
+ #clock-cells = <1>;
+ clk-phase-sd-hs = <132>, <60>;
+ };
+
+ - |
+ #define LGM_CLK_EMMC5
+ #define LGM_CLK_NGI
+ #define LGM_GCLK_EMMC
+ mmc@ec700000 {
+ compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
+ reg = <0xec700000 0x300>;
+ interrupt-parent = <&ioapic1>;
+ interrupts = <44 1>;
+ clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
+ <&cgu0 LGM_GCLK_EMMC>;
+ clock-names = "clk_xin", "clk_ahb", "gate";
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0>;
+ phys = <&emmc_phy>;
+ phy-names = "phy_arasan";
+ arasan,soc-ctl-syscon = <&sysconf>;
+ };
+
+ - |
+ #define LGM_CLK_SDIO
+ #define LGM_GCLK_SDXC
+ mmc@ec600000 {
+ compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
+ reg = <0xec600000 0x300>;
+ interrupt-parent = <&ioapic1>;
+ interrupts = <43 1>;
+ clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
+ <&cgu0 LGM_GCLK_SDXC>;
+ clock-names = "clk_xin", "clk_ahb", "gate";
+ clock-output-names = "sdxc_cardclock";
+ #clock-cells = <0>;
+ phys = <&sdxc_phy>;
+ phy-names = "phy_arasan";
+ arasan,soc-ctl-syscon = <&sysconf>;
+ };
+
+ - |
+ #define KEEM_BAY_PSS_AUX_EMMC
+ #define KEEM_BAY_PSS_EMMC
+ mmc@33000000 {
+ compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x33000000 0x300>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
+ <&scmi_clk KEEM_BAY_PSS_EMMC>;
+ phys = <&emmc_phy>;
+ phy-names = "phy_arasan";
+ assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
+ assigned-clock-rates = <200000000>;
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0>;
+ arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
+ };
+
+ - |
+ #define KEEM_BAY_PSS_AUX_SD0
+ #define KEEM_BAY_PSS_SD0
+ mmc@31000000 {
+ compatible = "intel,keembay-sdhci-5.1-sd";
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x31000000 0x300>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
+ <&scmi_clk KEEM_BAY_PSS_SD0>;
+ arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
+ };
diff --git a/dts/Bindings/mmc/aspeed,sdhci.yaml b/dts/Bindings/mmc/aspeed,sdhci.yaml
index 200de93..987b287 100644
--- a/dts/Bindings/mmc/aspeed,sdhci.yaml
+++ b/dts/Bindings/mmc/aspeed,sdhci.yaml
@@ -41,8 +41,8 @@ properties:
patternProperties:
"^sdhci@[0-9a-f]+$":
type: object
- allOf:
- - $ref: mmc-controller.yaml
+ $ref: mmc-controller.yaml
+
properties:
compatible:
enum:
diff --git a/dts/Bindings/mmc/cdns,sdhci.yaml b/dts/Bindings/mmc/cdns,sdhci.yaml
index 2f45dd0..d93f779 100644
--- a/dts/Bindings/mmc/cdns,sdhci.yaml
+++ b/dts/Bindings/mmc/cdns,sdhci.yaml
@@ -17,7 +17,7 @@ properties:
compatible:
items:
- enum:
- - socionext,uniphier-sd4hc
+ - socionext,uniphier-sd4hc
- const: cdns,sd4hc
reg:
@@ -36,91 +36,80 @@ properties:
cdns,phy-input-delay-sd-highspeed:
description: Value of the delay in the input path for SD high-speed timing
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- - maximum: 0x1f
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 0x1f
cdns,phy-input-delay-legacy:
description: Value of the delay in the input path for legacy timing
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- - maximum: 0x1f
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 0x1f
cdns,phy-input-delay-sd-uhs-sdr12:
description: Value of the delay in the input path for SD UHS SDR12 timing
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- - maximum: 0x1f
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 0x1f
cdns,phy-input-delay-sd-uhs-sdr25:
description: Value of the delay in the input path for SD UHS SDR25 timing
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- - maximum: 0x1f
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 0x1f
cdns,phy-input-delay-sd-uhs-sdr50:
description: Value of the delay in the input path for SD UHS SDR50 timing
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- - maximum: 0x1f
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 0x1f
cdns,phy-input-delay-sd-uhs-ddr50:
description: Value of the delay in the input path for SD UHS DDR50 timing
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- - maximum: 0x1f
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 0x1f
cdns,phy-input-delay-mmc-highspeed:
description: Value of the delay in the input path for MMC high-speed timing
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- - maximum: 0x1f
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 0x1f
cdns,phy-input-delay-mmc-ddr:
description: Value of the delay in the input path for eMMC high-speed DDR timing
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- - maximum: 0x1f
# PHY DLL clock delays:
# Each delay property represents the fraction of the clock period.
# The approximate delay value will be
# (<delay property value>/128)*sdmclk_clock_period.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 0x1f
cdns,phy-dll-delay-sdclk:
description: |
Value of the delay introduced on the sdclk output for all modes except
HS200, HS400 and HS400_ES.
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- - maximum: 0x7f
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 0x7f
cdns,phy-dll-delay-sdclk-hsmmc:
description: |
Value of the delay introduced on the sdclk output for HS200, HS400 and
HS400_ES speed modes.
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- - maximum: 0x7f
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 0x7f
cdns,phy-dll-delay-strobe:
description: |
Value of the delay introduced on the dat_strobe input used in
HS400 / HS400_ES speed modes.
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- - maximum: 0x7f
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 0x7f
required:
- compatible
diff --git a/dts/Bindings/mmc/fsl-imx-esdhc.txt b/dts/Bindings/mmc/fsl-imx-esdhc.txt
deleted file mode 100644
index de1b8bd..0000000
--- a/dts/Bindings/mmc/fsl-imx-esdhc.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-* Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
-
-The Enhanced Secure Digital Host Controller on Freescale i.MX family
-provides an interface for MMC, SD, and SDIO types of memory cards.
-
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
-
-Required properties:
-- compatible : Should be "fsl,<chip>-esdhc", the supported chips include
- "fsl,imx25-esdhc"
- "fsl,imx35-esdhc"
- "fsl,imx51-esdhc"
- "fsl,imx53-esdhc"
- "fsl,imx6q-usdhc"
- "fsl,imx6sl-usdhc"
- "fsl,imx6sx-usdhc"
- "fsl,imx6ull-usdhc"
- "fsl,imx7d-usdhc"
- "fsl,imx7ulp-usdhc"
- "fsl,imx8mq-usdhc"
- "fsl,imx8mm-usdhc"
- "fsl,imx8mn-usdhc"
- "fsl,imx8mp-usdhc"
- "fsl,imx8qm-usdhc"
- "fsl,imx8qxp-usdhc"
-
-Optional properties:
-- fsl,wp-controller : Indicate to use controller internal write protection
-- fsl,delay-line : Specify the number of delay cells for override mode.
- This is used to set the clock delay for DLL(Delay Line) on override mode
- to select a proper data sampling window in case the clock quality is not good
- due to signal path is too long on the board. Please refer to eSDHC/uSDHC
- chapter, DLL (Delay Line) section in RM for details.
-- voltage-ranges : Specify the voltage range in case there are software
- transparent level shifters on the outputs of the controller. Two cells are
- required, first cell specifies minimum slot voltage (mV), second cell
- specifies maximum slot voltage (mV). Several ranges could be specified.
-- fsl,tuning-start-tap: Specify the start dealy cell point when send first CMD19
- in tuning procedure.
-- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure.
- The uSDHC use one delay cell as default increasing step to do tuning process.
- This property allows user to change the tuning step to more than one delay
- cells which is useful for some special boards or cards when the default
- tuning step can't find the proper delay window within limited tuning retries.
-- fsl,strobe-dll-delay-target: Specify the strobe dll control slave delay target.
- This delay target programming host controller loopback read clock, and this
- property allows user to change the delay target for the strobe input read clock.
- If not use this property, driver default set the delay target to value 7.
- Only eMMC HS400 mode need to take care of this property.
-
-Examples:
-
-esdhc@70004000 {
- compatible = "fsl,imx51-esdhc";
- reg = <0x70004000 0x4000>;
- interrupts = <1>;
- fsl,wp-controller;
-};
-
-esdhc@70008000 {
- compatible = "fsl,imx51-esdhc";
- reg = <0x70008000 0x4000>;
- interrupts = <2>;
- cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
- wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
-};
diff --git a/dts/Bindings/mmc/fsl-imx-esdhc.yaml b/dts/Bindings/mmc/fsl-imx-esdhc.yaml
new file mode 100644
index 0000000..75dc116
--- /dev/null
+++ b/dts/Bindings/mmc/fsl-imx-esdhc.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
+
+maintainers:
+ - Shawn Guo <shawn.guo@linaro.org>
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+description: |
+ The Enhanced Secure Digital Host Controller on Freescale i.MX family
+ provides an interface for MMC, SD, and SDIO types of memory cards.
+
+ This file documents differences between the core properties described
+ by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx25-esdhc
+ - fsl,imx35-esdhc
+ - fsl,imx51-esdhc
+ - fsl,imx53-esdhc
+ - fsl,imx6q-usdhc
+ - fsl,imx6sl-usdhc
+ - fsl,imx6sx-usdhc
+ - fsl,imx6ull-usdhc
+ - fsl,imx7d-usdhc
+ - fsl,imx7ulp-usdhc
+ - fsl,imx8mq-usdhc
+ - fsl,imx8mm-usdhc
+ - fsl,imx8mn-usdhc
+ - fsl,imx8mp-usdhc
+ - fsl,imx8qm-usdhc
+ - fsl,imx8qxp-usdhc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ fsl,wp-controller:
+ description: |
+ boolean, if present, indicate to use controller internal write protection.
+ type: boolean
+
+ fsl,delay-line:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specify the number of delay cells for override mode.
+ This is used to set the clock delay for DLL(Delay Line) on override mode
+ to select a proper data sampling window in case the clock quality is not good
+ due to signal path is too long on the board. Please refer to eSDHC/uSDHC
+ chapter, DLL (Delay Line) section in RM for details.
+ default: 0
+
+ voltage-ranges:
+ $ref: '/schemas/types.yaml#/definitions/uint32-matrix'
+ description: |
+ Specify the voltage range in case there are software transparent level
+ shifters on the outputs of the controller. Two cells are required, first
+ cell specifies minimum slot voltage (mV), second cell specifies maximum
+ slot voltage (mV).
+ items:
+ items:
+ - description: value for minimum slot voltage
+ - description: value for maximum slot voltage
+ maxItems: 1
+
+ fsl,tuning-start-tap:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specify the start delay cell point when send first CMD19 in tuning procedure.
+ default: 0
+
+ fsl,tuning-step:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specify the increasing delay cell steps in tuning procedure.
+ The uSDHC use one delay cell as default increasing step to do tuning process.
+ This property allows user to change the tuning step to more than one delay
+ cells which is useful for some special boards or cards when the default
+ tuning step can't find the proper delay window within limited tuning retries.
+ default: 0
+
+ fsl,strobe-dll-delay-target:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specify the strobe dll control slave delay target.
+ This delay target programming host controller loopback read clock, and this
+ property allows user to change the delay target for the strobe input read clock.
+ If not use this property, driver default set the delay target to value 7.
+ Only eMMC HS400 mode need to take care of this property.
+ default: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@70004000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70004000 0x4000>;
+ interrupts = <1>;
+ fsl,wp-controller;
+ };
+
+ mmc@70008000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70008000 0x4000>;
+ interrupts = <2>;
+ cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
+ wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
+ };
diff --git a/dts/Bindings/mmc/fsl-imx-mmc.txt b/dts/Bindings/mmc/fsl-imx-mmc.txt
deleted file mode 100644
index 184ccff..0000000
--- a/dts/Bindings/mmc/fsl-imx-mmc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Freescale Secure Digital Host Controller for i.MX2/3 series
-
-This file documents differences to the properties defined in mmc.txt.
-
-Required properties:
-- compatible : Should be "fsl,<chip>-mmc", chip can be imx21 or imx31
-
-Optional properties:
-- dmas: One DMA phandle with arguments as defined by the devicetree bindings
- of the used DMA controller.
-- dma-names: Has to be "rx-tx".
-
-Example:
-
-sdhci1: sdhci@10014000 {
- compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
- reg = <0x10014000 0x1000>;
- interrupts = <11>;
- dmas = <&dma 7>;
- dma-names = "rx-tx";
- bus-width = <4>;
- cd-gpios = <&gpio3 29>;
-};
diff --git a/dts/Bindings/mmc/fsl-imx-mmc.yaml b/dts/Bindings/mmc/fsl-imx-mmc.yaml
new file mode 100644
index 0000000..ffa1627
--- /dev/null
+++ b/dts/Bindings/mmc/fsl-imx-mmc.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/fsl-imx-mmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Secure Digital Host Controller for i.MX2/3 series
+
+maintainers:
+ - Markus Pargmann <mpa@pengutronix.de>
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,imx21-mmc
+ - const: fsl,imx31-mmc
+ - items:
+ - const: fsl,imx27-mmc
+ - const: fsl,imx21-mmc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: rx-tx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@10014000 {
+ compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+ reg = <0x10014000 0x1000>;
+ interrupts = <11>;
+ dmas = <&dma 7>;
+ dma-names = "rx-tx";
+ bus-width = <4>;
+ cd-gpios = <&gpio3 29>;
+ };
diff --git a/dts/Bindings/mmc/ingenic,mmc.yaml b/dts/Bindings/mmc/ingenic,mmc.yaml
new file mode 100644
index 0000000..9b63df1
--- /dev/null
+++ b/dts/Bindings/mmc/ingenic,mmc.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/ingenic,mmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs MMC Controller DT bindings
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+allOf:
+ - $ref: mmc-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - ingenic,jz4740-mmc
+ - ingenic,jz4725b-mmc
+ - ingenic,jz4760-mmc
+ - ingenic,jz4780-mmc
+ - ingenic,x1000-mmc
+ - items:
+ - const: ingenic,jz4770-mmc
+ - const: ingenic,jz4760-mmc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: mmc
+
+ dmas:
+ items:
+ - description: DMA controller phandle and request line for RX
+ - description: DMA controller phandle and request line for TX
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4780-cgu.h>
+ #include <dt-bindings/dma/jz4780-dma.h>
+ mmc0: mmc@13450000 {
+ compatible = "ingenic,jz4780-mmc";
+ reg = <0x13450000 0x1000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <37>;
+
+ clocks = <&cgu JZ4780_CLK_MSC0>;
+ clock-names = "mmc";
+
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ cap-sdio-irq;
+ dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
+ <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
+ dma-names = "rx", "tx";
+ };
diff --git a/dts/Bindings/mmc/jz4740.txt b/dts/Bindings/mmc/jz4740.txt
deleted file mode 100644
index 453d3b9..0000000
--- a/dts/Bindings/mmc/jz4740.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-* Ingenic XBurst MMC controllers
-
-This file documents the device tree properties used for the MMC controller in
-Ingenic JZ4740/JZ4760/JZ4780/X1000 SoCs. These are in addition to the core MMC
-properties described in mmc.txt.
-
-Required properties:
-- compatible: Should be one of the following:
- - "ingenic,jz4740-mmc" for the JZ4740
- - "ingenic,jz4725b-mmc" for the JZ4725B
- - "ingenic,jz4760-mmc" for the JZ4760
- - "ingenic,jz4780-mmc" for the JZ4780
- - "ingenic,x1000-mmc" for the X1000
-- reg: Should contain the MMC controller registers location and length.
-- interrupts: Should contain the interrupt specifier of the MMC controller.
-- clocks: Clock for the MMC controller.
-
-Optional properties:
-- dmas: List of DMA specifiers with the controller specific format
- as described in the generic DMA client binding. A tx and rx
- specifier is required.
-- dma-names: RX and TX DMA request names.
- Should be "rx" and "tx", in that order.
-
-For additional details on DMA client bindings see ../dma/dma.txt.
-
-Example:
-
-mmc0: mmc@13450000 {
- compatible = "ingenic,jz4780-mmc";
- reg = <0x13450000 0x1000>;
-
- interrupt-parent = <&intc>;
- interrupts = <37>;
-
- clocks = <&cgu JZ4780_CLK_MSC0>;
- clock-names = "mmc";
-
- dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>, <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
- dma-names = "rx", "tx";
-};
diff --git a/dts/Bindings/mmc/mmc-controller.yaml b/dts/Bindings/mmc/mmc-controller.yaml
index acc9f10..b96da0c 100644
--- a/dts/Bindings/mmc/mmc-controller.yaml
+++ b/dts/Bindings/mmc/mmc-controller.yaml
@@ -76,20 +76,18 @@ properties:
# Other properties
bus-width:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - enum: [1, 4, 8]
- default: 1
description:
Number of data lines.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 4, 8]
+ default: 1
max-frequency:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - minimum: 400000
- - maximum: 200000000
description:
Maximum operating frequency of the bus.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 400000
+ maximum: 200000000
disable-wp:
$ref: /schemas/types.yaml#/definitions/flag
@@ -171,6 +169,11 @@ properties:
description:
Full power cycle of the card is supported.
+ full-pwr-cycle-in-suspend:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Full power cycle of the card in suspend is supported.
+
mmc-ddr-1_2v:
$ref: /schemas/types.yaml#/definitions/flag
description:
@@ -212,13 +215,12 @@ properties:
eMMC HS400 enhanced strobe mode is supported
dsr:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - minimum: 0
- - maximum: 0xffff
description:
Value the card Driver Stage Register (DSR) should be programmed
with.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
no-sdio:
$ref: /schemas/types.yaml#/definitions/flag
@@ -238,25 +240,23 @@ properties:
initialization.
fixed-emmc-driver-type:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - minimum: 0
- - maximum: 4
description:
For non-removable eMMC, enforce this driver type. The value is
the driver type as specified in the eMMC specification (table
206 in spec version 5.1)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 4
post-power-on-delay-ms:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - default: 10
description:
It was invented for MMC pwrseq-simple which could be referred to
mmc-pwrseq-simple.txt. But now it\'s reused as a tunable delay
waiting for I/O signalling and card power supply to be stable,
regardless of whether pwrseq-simple is used. Default to 10ms if
no available.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 10
supports-cqe:
$ref: /schemas/types.yaml#/definitions/flag
@@ -333,8 +333,8 @@ patternProperties:
- reg
"^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32-array
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
minItems: 2
maxItems: 2
items:
diff --git a/dts/Bindings/mmc/mmc-pwrseq-emmc.txt b/dts/Bindings/mmc/mmc-pwrseq-emmc.txt
deleted file mode 100644
index 3d965d5..0000000
--- a/dts/Bindings/mmc/mmc-pwrseq-emmc.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* The simple eMMC hardware reset provider
-
-The purpose of this driver is to perform standard eMMC hw reset
-procedure, as described by Jedec 4.4 specification. This procedure is
-performed just after MMC core enabled power to the given mmc host (to
-fix possible issues if bootloader has left eMMC card in initialized or
-unknown state), and before performing complete system reboot (also in
-case of emergency reboot call). The latter is needed on boards, which
-doesn't have hardware reset logic connected to emmc card and (limited or
-broken) ROM bootloaders are unable to read second stage from the emmc
-card if the card is left in unknown or already initialized state.
-
-Required properties:
-- compatible : contains "mmc-pwrseq-emmc".
-- reset-gpios : contains a GPIO specifier. The reset GPIO is asserted
- and then deasserted to perform eMMC card reset. To perform
- reset procedure as described in Jedec 4.4 specification, the
- gpio line should be defined as GPIO_ACTIVE_LOW.
-
-Example:
-
- sdhci0_pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
- }
diff --git a/dts/Bindings/mmc/mmc-pwrseq-emmc.yaml b/dts/Bindings/mmc/mmc-pwrseq-emmc.yaml
new file mode 100644
index 0000000..77f746f
--- /dev/null
+++ b/dts/Bindings/mmc/mmc-pwrseq-emmc.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Simple eMMC hardware reset provider binding
+
+maintainers:
+ - Ulf Hansson <ulf.hansson@linaro.org>
+
+description:
+ The purpose of this driver is to perform standard eMMC hw reset
+ procedure, as described by Jedec 4.4 specification. This procedure is
+ performed just after MMC core enabled power to the given mmc host (to
+ fix possible issues if bootloader has left eMMC card in initialized or
+ unknown state), and before performing complete system reboot (also in
+ case of emergency reboot call). The latter is needed on boards, which
+ doesn't have hardware reset logic connected to emmc card and (limited or
+ broken) ROM bootloaders are unable to read second stage from the emmc
+ card if the card is left in unknown or already initialized state.
+
+properties:
+ compatible:
+ const: mmc-pwrseq-emmc
+
+ reset-gpios:
+ minItems: 1
+ description:
+ contains a GPIO specifier. The reset GPIO is asserted
+ and then deasserted to perform eMMC card reset. To perform
+ reset procedure as described in Jedec 4.4 specification, the
+ gpio line should be defined as GPIO_ACTIVE_LOW.
+
+required:
+ - compatible
+ - reset-gpios
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ sdhci0_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ };
+...
diff --git a/dts/Bindings/mmc/mmc-pwrseq-sd8787.txt b/dts/Bindings/mmc/mmc-pwrseq-sd8787.txt
deleted file mode 100644
index 22e9340..0000000
--- a/dts/Bindings/mmc/mmc-pwrseq-sd8787.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-* Marvell SD8787 power sequence provider
-
-Required properties:
-- compatible: must be "mmc-pwrseq-sd8787".
-- powerdown-gpios: contains a power down GPIO specifier with the
- default active state
-- reset-gpios: contains a reset GPIO specifier with the default
- active state
-
-Example:
-
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-sd8787";
- powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
- reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>;
- }
diff --git a/dts/Bindings/mmc/mmc-pwrseq-sd8787.yaml b/dts/Bindings/mmc/mmc-pwrseq-sd8787.yaml
new file mode 100644
index 0000000..a68820d
--- /dev/null
+++ b/dts/Bindings/mmc/mmc-pwrseq-sd8787.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-sd8787.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell SD8787 power sequence provider binding
+
+maintainers:
+ - Ulf Hansson <ulf.hansson@linaro.org>
+
+properties:
+ compatible:
+ const: mmc-pwrseq-sd8787
+
+ powerdown-gpios:
+ minItems: 1
+ description:
+ contains a power down GPIO specifier with the default active state
+
+ reset-gpios:
+ minItems: 1
+ description:
+ contains a reset GPIO specifier with the default active state
+
+required:
+ - compatible
+ - powerdown-gpios
+ - reset-gpios
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-sd8787";
+ powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>;
+ };
+...
diff --git a/dts/Bindings/mmc/mmc-pwrseq-simple.txt b/dts/Bindings/mmc/mmc-pwrseq-simple.txt
deleted file mode 100644
index 9029b45..0000000
--- a/dts/Bindings/mmc/mmc-pwrseq-simple.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* The simple MMC power sequence provider
-
-The purpose of the simple MMC power sequence provider is to supports a set of
-common properties between various SOC designs. It thus enables us to use the
-same provider for several SOC designs.
-
-Required properties:
-- compatible : contains "mmc-pwrseq-simple".
-
-Optional properties:
-- reset-gpios : contains a list of GPIO specifiers. The reset GPIOs are asserted
- at initialization and prior we start the power up procedure of the card.
- They will be de-asserted right after the power has been provided to the
- card.
-- clocks : Must contain an entry for the entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names : Must include the following entry:
- "ext_clock" (External clock provided to the card).
-- post-power-on-delay-ms : Delay in ms after powering the card and
- de-asserting the reset-gpios (if any)
-- power-off-delay-us : Delay in us after asserting the reset-gpios (if any)
- during power off of the card.
-
-Example:
-
- sdhci0_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
- clocks = <&clk_32768_ck>;
- clock-names = "ext_clock";
- }
diff --git a/dts/Bindings/mmc/mmc-pwrseq-simple.yaml b/dts/Bindings/mmc/mmc-pwrseq-simple.yaml
new file mode 100644
index 0000000..4492154
--- /dev/null
+++ b/dts/Bindings/mmc/mmc-pwrseq-simple.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Simple MMC power sequence provider binding
+
+maintainers:
+ - Ulf Hansson <ulf.hansson@linaro.org>
+
+description:
+ The purpose of the simple MMC power sequence provider is to supports a set
+ of common properties between various SOC designs. It thus enables us to use
+ the same provider for several SOC designs.
+
+properties:
+ compatible:
+ const: mmc-pwrseq-simple
+
+ reset-gpios:
+ minItems: 1
+ description:
+ contains a list of GPIO specifiers. The reset GPIOs are asserted
+ at initialization and prior we start the power up procedure of the card.
+ They will be de-asserted right after the power has been provided to the
+ card.
+
+ clocks:
+ minItems: 1
+ description: Handle for the entry in clock-names.
+
+ clock-names:
+ items:
+ - const: ext_clock
+ description: External clock provided to the card.
+
+ post-power-on-delay-ms:
+ description:
+ Delay in ms after powering the card and de-asserting the
+ reset-gpios (if any).
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ power-off-delay-us:
+ description:
+ Delay in us after asserting the reset-gpios (if any)
+ during power off of the card.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ sdhci0_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_32768_ck>;
+ clock-names = "ext_clock";
+ };
+...
diff --git a/dts/Bindings/mmc/mtk-sd.txt b/dts/Bindings/mmc/mtk-sd.txt
index 8a532f4..0c9cf6a 100644
--- a/dts/Bindings/mmc/mtk-sd.txt
+++ b/dts/Bindings/mmc/mtk-sd.txt
@@ -12,6 +12,7 @@ Required properties:
"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
"mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
"mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
+ "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
"mediatek,mt7622-mmc": for MT7622 SoC
diff --git a/dts/Bindings/mmc/mxs-mmc.txt b/dts/Bindings/mmc/mxs-mmc.txt
deleted file mode 100644
index 515addc..0000000
--- a/dts/Bindings/mmc/mxs-mmc.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* Freescale MXS MMC controller
-
-The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
-to support MMC, SD, and SDIO types of memory cards.
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the mxsmmc driver.
-
-Required properties:
-- compatible: Should be "fsl,<chip>-mmc". The supported chips include
- imx23 and imx28.
-- interrupts: Should contain ERROR interrupt number
-- dmas: DMA specifier, consisting of a phandle to DMA controller node
- and SSP DMA channel ID.
- Refer to dma.txt and fsl-mxs-dma.txt for details.
-- dma-names: Must be "rx-tx".
-
-Examples:
-
-ssp0: ssp@80010000 {
- compatible = "fsl,imx28-mmc";
- reg = <0x80010000 2000>;
- interrupts = <96>;
- dmas = <&dma_apbh 0>;
- dma-names = "rx-tx";
- bus-width = <8>;
-};
diff --git a/dts/Bindings/mmc/mxs-mmc.yaml b/dts/Bindings/mmc/mxs-mmc.yaml
new file mode 100644
index 0000000..1cccc04
--- /dev/null
+++ b/dts/Bindings/mmc/mxs-mmc.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mxs-mmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MXS MMC controller
+
+maintainers:
+ - Shawn Guo <shawn.guo@linaro.org>
+
+description: |
+ The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
+ to support MMC, SD, and SDIO types of memory cards.
+
+ This file documents differences between the core properties in mmc.txt
+ and the properties used by the mxsmmc driver.
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx23-mmc
+ - fsl,imx28-mmc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: rx-tx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - dmas
+ - dma-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@80010000 {
+ compatible = "fsl,imx28-mmc";
+ reg = <0x80010000 2000>;
+ interrupts = <96>;
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ bus-width = <8>;
+ };
diff --git a/dts/Bindings/mmc/owl-mmc.yaml b/dts/Bindings/mmc/owl-mmc.yaml
index 12b4021..1380501 100644
--- a/dts/Bindings/mmc/owl-mmc.yaml
+++ b/dts/Bindings/mmc/owl-mmc.yaml
@@ -47,7 +47,7 @@ examples:
- |
mmc0: mmc@e0330000 {
compatible = "actions,owl-mmc";
- reg = <0x0 0xe0330000 0x0 0x4000>;
+ reg = <0xe0330000 0x4000>;
interrupts = <0 42 4>;
clocks = <&cmu 56>;
resets = <&cmu 23>;
diff --git a/dts/Bindings/mmc/renesas,mmcif.txt b/dts/Bindings/mmc/renesas,mmcif.txt
index c064af5..291532a 100644
--- a/dts/Bindings/mmc/renesas,mmcif.txt
+++ b/dts/Bindings/mmc/renesas,mmcif.txt
@@ -11,6 +11,7 @@ Required properties:
- "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs
- "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs
- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
+ - "renesas,mmcif-r8a7742" for the MMCIF found in r8a7742 SoCs
- "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs
- "renesas,mmcif-r8a7744" for the MMCIF found in r8a7744 SoCs
- "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs
@@ -24,8 +25,8 @@ Required properties:
- interrupts: Some SoCs have only 1 shared interrupt, while others have either
2 or 3 individual interrupts (error, int, card detect). Below is the number
of interrupts for each SoC:
- 1: r8a73a4, r8a7743, r8a7744, r8a7745, r8a7778, r8a7790, r8a7791, r8a7793,
- r8a7794
+ 1: r8a73a4, r8a7742, r8a7743, r8a7744, r8a7745, r8a7778, r8a7790, r8a7791,
+ r8a7793, r8a7794
2: r8a7740, sh73a0
3: r7s72100
diff --git a/dts/Bindings/mmc/renesas,sdhi.txt b/dts/Bindings/mmc/renesas,sdhi.txt
deleted file mode 100644
index e6cc478..0000000
--- a/dts/Bindings/mmc/renesas,sdhi.txt
+++ /dev/null
@@ -1,113 +0,0 @@
-* Renesas SDHI SD/MMC controller
-
-Required properties:
-- compatible: should contain one or more of the following:
- "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
- "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
- "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
- "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
- "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
- "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
- "renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
- "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
- "renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC
- "renesas,sdhi-r8a774b1" - SDHI IP on R8A774B1 SoC
- "renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC
- "renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC
- "renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC
- "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
- "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
- "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
- "renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC
- "renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC
- "renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC
- "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
- "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
- "renesas,sdhi-r8a7796" - SDHI IP on R8A77960 SoC
- "renesas,sdhi-r8a77961" - SDHI IP on R8A77961 SoC
- "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
- "renesas,sdhi-r8a77970" - SDHI IP on R8A77970 SoC
- "renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
- "renesas,sdhi-r8a77990" - SDHI IP on R8A77990 SoC
- "renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
- "renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
- "renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller
- "renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 and RZ/G1 SDHI
- (not SDHI/MMC) controller
- "renesas,rcar-gen3-sdhi" - a generic R-Car Gen3 or RZ/G2
- SDHI controller
-
-
- When compatible with the generic version, nodes must list
- the SoC-specific version corresponding to the platform
- first followed by the generic version.
-
-- clocks: Most controllers only have 1 clock source per channel. However, on
- some variations of this controller, the internal card detection
- logic that exists in this controller is sectioned off to be run by a
- separate second clock source to allow the main core clock to be turned
- off to save power.
- If 2 clocks are specified by the hardware, you must name them as
- "core" and "cd". If the controller only has 1 clock, naming is not
- required.
- Devices which have more than 1 clock are listed below:
- 2: R7S72100, R7S9210
-
-Optional properties:
-- pinctrl-names: should be "default", "state_uhs"
-- pinctrl-0: should contain default/high speed pin ctrl
-- pinctrl-1: should contain uhs mode pin ctrl
-
-Example: R8A7790 (R-Car H2) SDHI controller nodes
-
- sdhi0: sd@ee100000 {
- compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
- reg = <0 0xee100000 0 0x328>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 314>;
- dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
- <&dmac1 0xcd>, <&dmac1 0xce>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 314>;
- };
-
- sdhi1: sd@ee120000 {
- compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
- reg = <0 0xee120000 0 0x328>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 313>;
- dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
- <&dmac1 0xc9>, <&dmac1 0xca>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <195000000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 313>;
- };
-
- sdhi2: sd@ee140000 {
- compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
- reg = <0 0xee140000 0 0x100>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 312>;
- dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
- <&dmac1 0xc1>, <&dmac1 0xc2>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 312>;
- };
-
- sdhi3: sd@ee160000 {
- compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
- reg = <0 0xee160000 0 0x100>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 311>;
- dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
- <&dmac1 0xd3>, <&dmac1 0xd4>;
- dma-names = "tx", "rx", "tx", "rx";
- max-frequency = <97500000>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 311>;
- };
diff --git a/dts/Bindings/mmc/renesas,sdhi.yaml b/dts/Bindings/mmc/renesas,sdhi.yaml
new file mode 100644
index 0000000..b4c3fd4
--- /dev/null
+++ b/dts/Bindings/mmc/renesas,sdhi.yaml
@@ -0,0 +1,191 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas SDHI SD/MMC controller
+
+maintainers:
+ - Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: renesas,sdhi-sh73a0 # R-Mobile APE6
+ - items:
+ - const: renesas,sdhi-r7s72100 # RZ/A1H
+ - items:
+ - const: renesas,sdhi-r7s9210 # SH-Mobile AG5
+ - items:
+ - const: renesas,sdhi-r8a73a4 # R-Mobile APE6
+ - items:
+ - const: renesas,sdhi-r8a7740 # R-Mobile A1
+ - items:
+ - enum:
+ - renesas,sdhi-r8a7778 # R-Car M1
+ - renesas,sdhi-r8a7779 # R-Car H1
+ - const: renesas,rcar-gen1-sdhi # R-Car Gen1
+ - items:
+ - enum:
+ - renesas,sdhi-r8a7742 # RZ/G1H
+ - renesas,sdhi-r8a7743 # RZ/G1M
+ - renesas,sdhi-r8a7744 # RZ/G1N
+ - renesas,sdhi-r8a7745 # RZ/G1E
+ - renesas,sdhi-r8a77470 # RZ/G1C
+ - renesas,sdhi-r8a7790 # R-Car H2
+ - renesas,sdhi-r8a7791 # R-Car M2-W
+ - renesas,sdhi-r8a7792 # R-Car V2H
+ - renesas,sdhi-r8a7793 # R-Car M2-N
+ - renesas,sdhi-r8a7794 # R-Car E2
+ - const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1
+ - items:
+ - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
+ - items:
+ - enum:
+ - renesas,sdhi-r8a774a1 # RZ/G2M
+ - renesas,sdhi-r8a774b1 # RZ/G2N
+ - renesas,sdhi-r8a774c0 # RZ/G2E
+ - renesas,sdhi-r8a7795 # R-Car H3
+ - renesas,sdhi-r8a7796 # R-Car M3-W
+ - renesas,sdhi-r8a77961 # R-Car M3-W+
+ - renesas,sdhi-r8a77965 # R-Car M3-N
+ - renesas,sdhi-r8a77970 # R-Car V3M
+ - renesas,sdhi-r8a77980 # R-Car V3H
+ - renesas,sdhi-r8a77990 # R-Car E3
+ - renesas,sdhi-r8a77995 # R-Car D3
+ - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 3
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: core
+ - const: cd
+
+ dmas:
+ minItems: 4
+ maxItems: 4
+
+ dma-names:
+ minItems: 4
+ maxItems: 4
+ items:
+ enum:
+ - tx
+ - rx
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ pinctrl-0:
+ minItems: 1
+ maxItems: 2
+
+ pinctrl-1:
+ maxItems: 1
+
+ pinctrl-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: default
+ - const: state_uhs
+
+ max-frequency: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+
+if:
+ properties:
+ compatible:
+ items:
+ enum:
+ - renesas,sdhi-r7s72100
+ - renesas,sdhi-r7s9210
+then:
+ required:
+ - clock-names
+ description:
+ The internal card detection logic that exists in these controllers is
+ sectioned off to be run by a separate second clock source to allow
+ the main core clock to be turned off to save power.
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7790-sysc.h>
+
+ sdhi0: mmc@ee100000 {
+ compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ reg = <0xee100000 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ };
+
+ sdhi1: mmc@ee120000 {
+ compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ reg = <0xee120000 0x328>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 313>;
+ dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 313>;
+ };
+
+ sdhi2: mmc@ee140000 {
+ compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ reg = <0xee140000 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ };
+
+ sdhi3: mmc@ee160000 {
+ compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ reg = <0xee160000 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ };
diff --git a/dts/Bindings/mmc/rockchip-dw-mshc.yaml b/dts/Bindings/mmc/rockchip-dw-mshc.yaml
index 89c3edd..0131618 100644
--- a/dts/Bindings/mmc/rockchip-dw-mshc.yaml
+++ b/dts/Bindings/mmc/rockchip-dw-mshc.yaml
@@ -30,21 +30,21 @@ properties:
- items:
- enum:
# for Rockchip PX30
- - rockchip,px30-dw-mshc
+ - rockchip,px30-dw-mshc
# for Rockchip RK3036
- - rockchip,rk3036-dw-mshc
+ - rockchip,rk3036-dw-mshc
# for Rockchip RK322x
- - rockchip,rk3228-dw-mshc
+ - rockchip,rk3228-dw-mshc
# for Rockchip RK3308
- - rockchip,rk3308-dw-mshc
+ - rockchip,rk3308-dw-mshc
# for Rockchip RK3328
- - rockchip,rk3328-dw-mshc
+ - rockchip,rk3328-dw-mshc
# for Rockchip RK3368
- - rockchip,rk3368-dw-mshc
+ - rockchip,rk3368-dw-mshc
# for Rockchip RK3399
- - rockchip,rk3399-dw-mshc
+ - rockchip,rk3399-dw-mshc
# for Rockchip RV1108
- - rockchip,rv1108-dw-mshc
+ - rockchip,rv1108-dw-mshc
- const: rockchip,rk3288-dw-mshc
reg:
@@ -76,8 +76,7 @@ properties:
high speed modes.
rockchip,default-sample-phase:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 360
default: 0
@@ -87,8 +86,7 @@ properties:
If not specified 0 deg will be used.
rockchip,desired-num-phases:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 360
default: 360
@@ -111,7 +109,7 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
sdmmc: mmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xff0c0000 0x0 0x4000>;
+ reg = <0xff0c0000 0x4000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
diff --git a/dts/Bindings/mmc/sdhci-am654.txt b/dts/Bindings/mmc/sdhci-am654.txt
index c6ccecb..6d202f4 100644
--- a/dts/Bindings/mmc/sdhci-am654.txt
+++ b/dts/Bindings/mmc/sdhci-am654.txt
@@ -39,6 +39,7 @@ Optional Properties (Required for ti,am654-sdhci-5.1 and ti,j721e-sdhci-8bit):
Valid values are 33, 40, 50, 66 and 100 ohms.
Optional Properties:
- ti,strobe-sel: strobe select delay for HS400 speed mode. Default value: 0x0.
+ - ti,clkbuf-sel: Clock Delay Buffer Select
Example:
diff --git a/dts/Bindings/mmc/sdhci-msm.txt b/dts/Bindings/mmc/sdhci-msm.txt
index 5445931..3b602fd 100644
--- a/dts/Bindings/mmc/sdhci-msm.txt
+++ b/dts/Bindings/mmc/sdhci-msm.txt
@@ -17,6 +17,7 @@ Required properties:
"qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
"qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
"qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
+ "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
"qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
"qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
"qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
@@ -46,6 +47,28 @@ Required properties:
"cal" - reference clock for RCLK delay calibration (optional)
"sleep" - sleep clock for RCLK delay calibration (optional)
+- qcom,ddr-config: Certain chipsets and platforms require particular settings
+ for the DDR_CONFIG register. Use this field to specify the register
+ value as per the Hardware Programming Guide.
+
+- qcom,dll-config: Chipset and Platform specific value. Use this field to
+ specify the DLL_CONFIG register value as per Hardware Programming Guide.
+
+Optional Properties:
+* Following bus parameters are required for interconnect bandwidth scaling:
+- interconnects: Pairs of phandles and interconnect provider specifier
+ to denote the edge source and destination ports of
+ the interconnect path.
+
+- interconnect-names: For sdhc, we have two main paths.
+ 1. Data path : sdhc to ddr
+ 2. Config path : cpu to sdhc
+ For Data interconnect path the name supposed to be
+ is "sdhc-ddr" and for config interconnect path it is
+ "cpu-sdhc".
+ Please refer to Documentation/devicetree/bindings/
+ interconnect/ for more details.
+
Example:
sdhc_1: sdhci@f9824900 {
@@ -63,6 +86,12 @@ Example:
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
+ interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>,
+ <&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>;
+ interconnect-names = "sdhc-ddr","cpu-sdhc";
+
+ qcom,dll-config = <0x000f642c>;
+ qcom,ddr-config = <0x80040868>;
};
sdhc_2: sdhci@f98a4900 {
@@ -80,4 +109,7 @@ Example:
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
+
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
};
diff --git a/dts/Bindings/mmc/sdhci-pxa.txt b/dts/Bindings/mmc/sdhci-pxa.txt
deleted file mode 100644
index 3d1b449..0000000
--- a/dts/Bindings/mmc/sdhci-pxa.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-* Marvell sdhci-pxa v2/v3 controller
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers.
-
-Required properties:
-- compatible: Should be "mrvl,pxav2-mmc", "mrvl,pxav3-mmc" or
- "marvell,armada-380-sdhci".
-- reg:
- * for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for
- the SDHCI registers.
-
- * for "marvell,armada-380-sdhci", three register areas. The first
- one for the SDHCI registers themselves, the second one for the
- AXI/Mbus bridge registers of the SDHCI unit, the third one for the
- SDIO3 Configuration register
-- reg names: should be "sdhci", "mbus", "conf-sdio3". only mandatory
- for "marvell,armada-380-sdhci"
-- clocks: Array of clocks required for SDHCI; requires at least one for
- I/O clock.
-- clock-names: Array of names corresponding to clocks property; shall be
- "io" for I/O clock and "core" for optional core clock.
-
-Optional properties:
-- mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.
-
-Example:
-
-sdhci@d4280800 {
- compatible = "mrvl,pxav3-mmc";
- reg = <0xd4280800 0x800>;
- bus-width = <8>;
- interrupts = <27>;
- clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
- clock-names = "io", "core";
- non-removable;
- mrvl,clk-delay-cycles = <31>;
-};
-
-sdhci@d8000 {
- compatible = "marvell,armada-380-sdhci";
- reg-names = "sdhci", "mbus", "conf-sdio3";
- reg = <0xd8000 0x1000>,
- <0xdc000 0x100>;
- <0x18454 0x4>;
- interrupts = <0 25 0x4>;
- clocks = <&gateclk 17>;
- clock-names = "io";
- mrvl,clk-delay-cycles = <0x1F>;
-};
diff --git a/dts/Bindings/mmc/sdhci-pxa.yaml b/dts/Bindings/mmc/sdhci-pxa.yaml
new file mode 100644
index 0000000..a58715c
--- /dev/null
+++ b/dts/Bindings/mmc/sdhci-pxa.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell PXA SDHCI v2/v3 bindings
+
+maintainers:
+ - Ulf Hansson <ulf.hansson@linaro.org>
+
+allOf:
+ - $ref: mmc-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: marvell,armada-380-sdhci
+ then:
+ properties:
+ regs:
+ minItems: 3
+ reg-names:
+ minItems: 3
+ required:
+ - reg-names
+ else:
+ properties:
+ regs:
+ maxItems: 1
+ reg-names:
+ maxItems: 1
+
+properties:
+ compatible:
+ enum:
+ - mrvl,pxav2-mmc
+ - mrvl,pxav3-mmc
+ - marvell,armada-380-sdhci
+
+ reg:
+ minItems: 1
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: sdhci
+ - const: mbus
+ - const: conf-sdio3
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: io
+ - const: core
+
+ mrvl,clk-delay-cycles:
+ description: Specify a number of cycles to delay for tuning.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/berlin2.h>
+ mmc@d4280800 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0xd4280800 0x800>;
+ bus-width = <8>;
+ interrupts = <27>;
+ clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
+ clock-names = "io", "core";
+ non-removable;
+ mrvl,clk-delay-cycles = <31>;
+ };
+ - |
+ mmc@d8000 {
+ compatible = "marvell,armada-380-sdhci";
+ reg-names = "sdhci", "mbus", "conf-sdio3";
+ reg = <0xd8000 0x1000>,
+ <0xdc000 0x100>,
+ <0x18454 0x4>;
+ interrupts = <0 25 0x4>;
+ clocks = <&gateclk 17>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <0x1F>;
+ };
+
+...
diff --git a/dts/Bindings/mmc/socionext,uniphier-sd.yaml b/dts/Bindings/mmc/socionext,uniphier-sd.yaml
index cdfac9b..8d6413f 100644
--- a/dts/Bindings/mmc/socionext,uniphier-sd.yaml
+++ b/dts/Bindings/mmc/socionext,uniphier-sd.yaml
@@ -35,15 +35,15 @@ properties:
oneOf:
- const: host
- items:
- - const: host
- - const: bridge
+ - const: host
+ - const: bridge
- items:
- - const: host
- - const: hw
+ - const: host
+ - const: hw
- items:
- - const: host
- - const: bridge
- - const: hw
+ - const: host
+ - const: bridge
+ - const: hw
resets:
minItems: 1
diff --git a/dts/Bindings/mmc/synopsys-dw-mshc-common.yaml b/dts/Bindings/mmc/synopsys-dw-mshc-common.yaml
index 890d47a..85bd528 100644
--- a/dts/Bindings/mmc/synopsys-dw-mshc-common.yaml
+++ b/dts/Bindings/mmc/synopsys-dw-mshc-common.yaml
@@ -27,39 +27,35 @@ properties:
clock to this at probe time.
fifo-depth:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
description:
The maximum size of the tx/rx fifo's. If this property is not
specified, the default value of the fifo size is determined from the
controller registers.
+ $ref: /schemas/types.yaml#/definitions/uint32
card-detect-delay:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - default: 0
description:
Delay in milli-seconds before detecting card after card
insert event. The default value is 0.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
data-addr:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
description:
Override fifo address with value provided by DT. The default FIFO reg
offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A)
by driver. If the controller does not follow this rule, please use
this property to set fifo address in device tree.
+ $ref: /schemas/types.yaml#/definitions/uint32
fifo-watermark-aligned:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/flag
description:
Data done irq is expected if data length is less than
watermark in PIO mode. But fifo watermark is requested to be aligned
with data length in some SoC so that TX/RX irq can be generated with
data done irq. Add this watermark quirk to mark this requirement and
force fifo watermark setting accordingly.
+ $ref: /schemas/types.yaml#/definitions/flag
dmas:
maxItems: 1