diff options
Diffstat (limited to 'dts/Bindings/powerpc/fsl')
| -rw-r--r-- | dts/Bindings/powerpc/fsl/cpus.txt | 4 | ||||
| -rw-r--r-- | dts/Bindings/powerpc/fsl/dcsr.txt | 4 | ||||
| -rw-r--r-- | dts/Bindings/powerpc/fsl/l2cache.txt | 55 | ||||
| -rw-r--r-- | dts/Bindings/powerpc/fsl/mpc5200.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/powerpc/fsl/raideng.txt | 2 |
5 files changed, 6 insertions, 61 deletions
diff --git a/dts/Bindings/powerpc/fsl/cpus.txt b/dts/Bindings/powerpc/fsl/cpus.txt index d63ab1dec1..4787db8de2 100644 --- a/dts/Bindings/powerpc/fsl/cpus.txt +++ b/dts/Bindings/powerpc/fsl/cpus.txt @@ -5,7 +5,7 @@ Copyright 2013 Freescale Semiconductor Inc. Power Architecture CPUs in Freescale SOCs are represented in device trees as per the definition in the Devicetree Specification. -In addition to the the Devicetree Specification definitions, the properties +In addition to the Devicetree Specification definitions, the properties defined below may be present on CPU nodes. PROPERTIES @@ -28,6 +28,6 @@ PROPERTIES Snoop ID Port Mapping registers, which are part of the CoreNet Coherency fabric (CCF), provide a CoreNet Coherency Subdomain ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from - these registers should be set if the coresponding CPU should be + these registers should be set if the corresponding CPU should be snooped. This property defines a bitmask which selects the bit that should be set if this cpu should be snooped. diff --git a/dts/Bindings/powerpc/fsl/dcsr.txt b/dts/Bindings/powerpc/fsl/dcsr.txt index 4b01e1afaf..62744afb5b 100644 --- a/dts/Bindings/powerpc/fsl/dcsr.txt +++ b/dts/Bindings/powerpc/fsl/dcsr.txt @@ -185,10 +185,10 @@ PROPERTIES with distinct functionality. The first register range describes the CoreNet Debug Controller - functionalty to perform transaction and transaction attribute matches. + functionality to perform transaction and transaction attribute matches. The second register range describes the CoreNet Debug Controller - functionalty to trigger event notifications and debug traces. + functionality to trigger event notifications and debug traces. EXAMPLE dcsr-corenet { diff --git a/dts/Bindings/powerpc/fsl/l2cache.txt b/dts/Bindings/powerpc/fsl/l2cache.txt deleted file mode 100644 index 22ad012660..0000000000 --- a/dts/Bindings/powerpc/fsl/l2cache.txt +++ /dev/null @@ -1,55 +0,0 @@ -Freescale L2 Cache Controller - -L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. -The cache bindings explained below are Devicetree Specification compliant - -Required Properties: - -- compatible : Should include one of the following: - "fsl,b4420-l2-cache-controller" - "fsl,b4860-l2-cache-controller" - "fsl,bsc9131-l2-cache-controller" - "fsl,bsc9132-l2-cache-controller" - "fsl,c293-l2-cache-controller" - "fsl,mpc8536-l2-cache-controller" - "fsl,mpc8540-l2-cache-controller" - "fsl,mpc8541-l2-cache-controller" - "fsl,mpc8544-l2-cache-controller" - "fsl,mpc8548-l2-cache-controller" - "fsl,mpc8555-l2-cache-controller" - "fsl,mpc8560-l2-cache-controller" - "fsl,mpc8568-l2-cache-controller" - "fsl,mpc8569-l2-cache-controller" - "fsl,mpc8572-l2-cache-controller" - "fsl,p1010-l2-cache-controller" - "fsl,p1011-l2-cache-controller" - "fsl,p1012-l2-cache-controller" - "fsl,p1013-l2-cache-controller" - "fsl,p1014-l2-cache-controller" - "fsl,p1015-l2-cache-controller" - "fsl,p1016-l2-cache-controller" - "fsl,p1020-l2-cache-controller" - "fsl,p1021-l2-cache-controller" - "fsl,p1022-l2-cache-controller" - "fsl,p1023-l2-cache-controller" - "fsl,p1024-l2-cache-controller" - "fsl,p1025-l2-cache-controller" - "fsl,p2010-l2-cache-controller" - "fsl,p2020-l2-cache-controller" - "fsl,t2080-l2-cache-controller" - "fsl,t4240-l2-cache-controller" - and "cache". -- reg : Address and size of L2 cache controller registers -- cache-size : Size of the entire L2 cache -- interrupts : Error interrupt of L2 controller -- cache-line-size : Size of L2 cache lines - -Example: - - L2: l2-cache-controller@20000 { - compatible = "fsl,bsc9132-l2-cache-controller", "cache"; - reg = <0x20000 0x1000>; - cache-line-size = <32>; // 32 bytes - cache-size = <0x40000>; // L2,256K - interrupts = <16 2 1 0>; - }; diff --git a/dts/Bindings/powerpc/fsl/mpc5200.txt b/dts/Bindings/powerpc/fsl/mpc5200.txt index d096cf461d..4571c857db 100644 --- a/dts/Bindings/powerpc/fsl/mpc5200.txt +++ b/dts/Bindings/powerpc/fsl/mpc5200.txt @@ -172,7 +172,7 @@ Interrupt controller (fsl,mpc5200-pic) node The mpc5200 pic binding splits hardware IRQ numbers into two levels. The split reflects the layout of the PIC hardware itself, which groups interrupts into one of three groups; CRIT, MAIN or PERP. Also, the -Bestcomm dma engine has it's own set of interrupt sources which are +Bestcomm dma engine has its own set of interrupt sources which are cascaded off of peripheral interrupt 0, which the driver interprets as a fourth group, SDMA. diff --git a/dts/Bindings/powerpc/fsl/raideng.txt b/dts/Bindings/powerpc/fsl/raideng.txt index 4ad29b9ac2..ea902bc587 100644 --- a/dts/Bindings/powerpc/fsl/raideng.txt +++ b/dts/Bindings/powerpc/fsl/raideng.txt @@ -60,7 +60,7 @@ Optional property: - fsl,liodn: Specifies the LIODN to be used for Job Ring. This property is normally set by firmware. Value is of 12-bits which is the LIODN number for this JR. - This property is used by the IOMMU (PAMU) to distinquish + This property is used by the IOMMU (PAMU) to distinguish transactions from this JR and than be able to do address translation & protection accordingly. |