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-rw-r--r--dts/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml53
-rw-r--r--dts/Bindings/pwm/brcm,bcm7038-pwm.yaml1
-rw-r--r--dts/Bindings/pwm/google,cros-ec-pwm.yaml5
-rw-r--r--dts/Bindings/pwm/imx-pwm.yaml4
-rw-r--r--dts/Bindings/pwm/imx-tpm-pwm.yaml4
-rw-r--r--dts/Bindings/pwm/intel,keembay-pwm.yaml1
-rw-r--r--dts/Bindings/pwm/intel,lgm-pwm.yaml3
-rw-r--r--dts/Bindings/pwm/iqs620a-pwm.yaml4
-rw-r--r--dts/Bindings/pwm/microchip,corepwm.yaml81
-rw-r--r--dts/Bindings/pwm/mxs-pwm.yaml4
-rw-r--r--dts/Bindings/pwm/pwm-mtk-disp.txt1
-rw-r--r--dts/Bindings/pwm/pwm-rockchip.yaml74
-rw-r--r--dts/Bindings/pwm/pwm-samsung.yaml1
-rw-r--r--dts/Bindings/pwm/pwm-sifive.yaml4
-rw-r--r--dts/Bindings/pwm/pwm-tiecap.yaml1
-rw-r--r--dts/Bindings/pwm/pwm-tiehrpwm.yaml1
-rw-r--r--dts/Bindings/pwm/renesas,pwm-rcar.yaml26
-rw-r--r--dts/Bindings/pwm/renesas,tpu-pwm.yaml1
-rw-r--r--dts/Bindings/pwm/toshiba,pwm-visconti.yaml4
19 files changed, 187 insertions, 86 deletions
diff --git a/dts/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/dts/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml
index 800d511502..e93e935564 100644
--- a/dts/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml
+++ b/dts/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml
@@ -52,33 +52,36 @@ properties:
resets:
maxItems: 1
-if:
- properties:
- compatible:
- contains:
- const: allwinner,sun50i-h6-pwm
-
-then:
- properties:
- clocks:
- maxItems: 2
-
- clock-names:
- items:
- - const: mod
- - const: bus
-
- required:
- - clock-names
- - resets
-
-else:
- properties:
- clocks:
- maxItems: 1
+
+allOf:
+ - $ref: pwm.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun50i-h6-pwm
+
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: mod
+ - const: bus
+
+ required:
+ - clock-names
+ - resets
+
+ else:
+ properties:
+ clocks:
+ maxItems: 1
required:
- - "#pwm-cells"
- compatible
- reg
- clocks
diff --git a/dts/Bindings/pwm/brcm,bcm7038-pwm.yaml b/dts/Bindings/pwm/brcm,bcm7038-pwm.yaml
index 4080e098f7..119de3d7f9 100644
--- a/dts/Bindings/pwm/brcm,bcm7038-pwm.yaml
+++ b/dts/Bindings/pwm/brcm,bcm7038-pwm.yaml
@@ -28,7 +28,6 @@ properties:
required:
- compatible
- reg
- - "#pwm-cells"
- clocks
additionalProperties: false
diff --git a/dts/Bindings/pwm/google,cros-ec-pwm.yaml b/dts/Bindings/pwm/google,cros-ec-pwm.yaml
index 4cfbffd841..7ab6912a84 100644
--- a/dts/Bindings/pwm/google,cros-ec-pwm.yaml
+++ b/dts/Bindings/pwm/google,cros-ec-pwm.yaml
@@ -16,6 +16,9 @@ description: |
An EC PWM node should be only found as a sub-node of the EC node (see
Documentation/devicetree/bindings/mfd/google,cros-ec.yaml).
+allOf:
+ - $ref: pwm.yaml#
+
properties:
compatible:
const: google,cros-ec-pwm
@@ -39,7 +42,7 @@ examples:
compatible = "google,cros-ec-spi";
reg = <0>;
- cros_ec_pwm: ec-pwm {
+ cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
};
diff --git a/dts/Bindings/pwm/imx-pwm.yaml b/dts/Bindings/pwm/imx-pwm.yaml
index 379d693889..b3da4e6293 100644
--- a/dts/Bindings/pwm/imx-pwm.yaml
+++ b/dts/Bindings/pwm/imx-pwm.yaml
@@ -9,6 +9,9 @@ title: Freescale i.MX PWM controller
maintainers:
- Philipp Zabel <p.zabel@pengutronix.de>
+allOf:
+ - $ref: pwm.yaml#
+
properties:
"#pwm-cells":
description: |
@@ -59,7 +62,6 @@ properties:
maxItems: 1
required:
- - "#pwm-cells"
- compatible
- reg
- clocks
diff --git a/dts/Bindings/pwm/imx-tpm-pwm.yaml b/dts/Bindings/pwm/imx-tpm-pwm.yaml
index fe9ef42544..8bef9dfeba 100644
--- a/dts/Bindings/pwm/imx-tpm-pwm.yaml
+++ b/dts/Bindings/pwm/imx-tpm-pwm.yaml
@@ -13,6 +13,9 @@ description: |
The TPM counter and period counter are shared between multiple
channels, so all channels should use same period setting.
+allOf:
+ - $ref: pwm.yaml#
+
properties:
"#pwm-cells":
const: 3
@@ -34,7 +37,6 @@ properties:
maxItems: 1
required:
- - "#pwm-cells"
- compatible
- reg
- clocks
diff --git a/dts/Bindings/pwm/intel,keembay-pwm.yaml b/dts/Bindings/pwm/intel,keembay-pwm.yaml
index ff6880a02c..ec9f6bab79 100644
--- a/dts/Bindings/pwm/intel,keembay-pwm.yaml
+++ b/dts/Bindings/pwm/intel,keembay-pwm.yaml
@@ -31,7 +31,6 @@ required:
- compatible
- reg
- clocks
- - '#pwm-cells'
additionalProperties: false
diff --git a/dts/Bindings/pwm/intel,lgm-pwm.yaml b/dts/Bindings/pwm/intel,lgm-pwm.yaml
index 11a6065361..59d7c4d864 100644
--- a/dts/Bindings/pwm/intel,lgm-pwm.yaml
+++ b/dts/Bindings/pwm/intel,lgm-pwm.yaml
@@ -9,6 +9,9 @@ title: LGM SoC PWM fan controller
maintainers:
- Rahul Tanwar <rtanwar@maxlinear.com>
+allOf:
+ - $ref: pwm.yaml#
+
properties:
compatible:
const: intel,lgm-pwm
diff --git a/dts/Bindings/pwm/iqs620a-pwm.yaml b/dts/Bindings/pwm/iqs620a-pwm.yaml
index 1d7c27be50..0a46af240d 100644
--- a/dts/Bindings/pwm/iqs620a-pwm.yaml
+++ b/dts/Bindings/pwm/iqs620a-pwm.yaml
@@ -15,6 +15,9 @@ description: |
Documentation/devicetree/bindings/mfd/iqs62x.yaml for further details as
well as an example.
+allOf:
+ - $ref: pwm.yaml#
+
properties:
compatible:
enum:
@@ -25,7 +28,6 @@ properties:
required:
- compatible
- - "#pwm-cells"
additionalProperties: false
diff --git a/dts/Bindings/pwm/microchip,corepwm.yaml b/dts/Bindings/pwm/microchip,corepwm.yaml
new file mode 100644
index 0000000000..a7fae1772a
--- /dev/null
+++ b/dts/Bindings/pwm/microchip,corepwm.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip IP corePWM controller bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+description: |
+ corePWM is an 16 channel pulse width modulator FPGA IP
+
+ https://www.microsemi.com/existing-parts/parts/152118
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: microchip,corepwm-rtl-v4
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ microchip,sync-update-mask:
+ description: |
+ Depending on how the IP is instantiated, there are two modes of operation.
+ In synchronous mode, all channels are updated at the beginning of the PWM period,
+ and in asynchronous mode updates happen as the control registers are written.
+ A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
+ mode is possible for each channel, and is set by the bitstream programmed to the
+ FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
+ control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
+ At runtime a bit wide register exposed to APB can be used to toggle on/off
+ synchronised mode for all channels it has been synthesised for.
+ Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
+ whether synchronous mode is possible for the PWM channel.
+
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+ microchip,dac-mode-mask:
+ description: |
+ Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
+ a minimum period pulse train whose High/Low average is that of the chosen duty
+ cycle. This "DAC" will have far better bandwidth and ripple performance than the
+ standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
+ core, set at instantiation and by the bitstream programmed to the FPGA, determines
+ whether a given channel operates in regular PWM or DAC mode.
+ Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
+ for that channel.
+
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm@41000000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ microchip,sync-update-mask = /bits/ 32 <0>;
+ clocks = <&clkcfg 30>;
+ reg = <0x41000000 0xF0>;
+ #pwm-cells = <2>;
+ };
diff --git a/dts/Bindings/pwm/mxs-pwm.yaml b/dts/Bindings/pwm/mxs-pwm.yaml
index 8740e07606..a34cbc13f6 100644
--- a/dts/Bindings/pwm/mxs-pwm.yaml
+++ b/dts/Bindings/pwm/mxs-pwm.yaml
@@ -10,6 +10,9 @@ maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Anson Huang <anson.huang@nxp.com>
+allOf:
+ - $ref: pwm.yaml#
+
properties:
compatible:
enum:
@@ -28,7 +31,6 @@ properties:
required:
- compatible
- reg
- - "#pwm-cells"
- fsl,pwm-number
additionalProperties: false
diff --git a/dts/Bindings/pwm/pwm-mtk-disp.txt b/dts/Bindings/pwm/pwm-mtk-disp.txt
index 902b271891..691e58b6c2 100644
--- a/dts/Bindings/pwm/pwm-mtk-disp.txt
+++ b/dts/Bindings/pwm/pwm-mtk-disp.txt
@@ -6,6 +6,7 @@ Required properties:
- "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
- "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
- "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
+ - "mediatek,mt8183-disp-pwm": found on mt8183 SoC.$
- reg: physical base address and length of the controller's registers.
- #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
the cell format.
diff --git a/dts/Bindings/pwm/pwm-rockchip.yaml b/dts/Bindings/pwm/pwm-rockchip.yaml
index 81a54a4e8e..a336ff9364 100644
--- a/dts/Bindings/pwm/pwm-rockchip.yaml
+++ b/dts/Bindings/pwm/pwm-rockchip.yaml
@@ -51,42 +51,44 @@ properties:
required:
- compatible
- reg
- - "#pwm-cells"
-
-if:
- properties:
- compatible:
- contains:
- enum:
- - rockchip,rk3328-pwm
- - rockchip,rv1108-pwm
-
-then:
- properties:
- clocks:
- items:
- - description: Used to derive the functional clock for the device.
- - description: Used as the APB bus clock.
-
- clock-names:
- items:
- - const: pwm
- - const: pclk
-
- required:
- - clocks
- - clock-names
-
-else:
- properties:
- clocks:
- maxItems: 1
- description:
- Used both to derive the functional clock
- for the device and as the bus clock.
-
- required:
- - clocks
+
+allOf:
+ - $ref: pwm.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rk3328-pwm
+ - rockchip,rv1108-pwm
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Used to derive the functional clock for the device.
+ - description: Used as the APB bus clock.
+
+ clock-names:
+ items:
+ - const: pwm
+ - const: pclk
+
+ required:
+ - clocks
+ - clock-names
+
+ else:
+ properties:
+ clocks:
+ maxItems: 1
+ description:
+ Used both to derive the functional clock
+ for the device and as the bus clock.
+
+ required:
+ - clocks
additionalProperties: false
diff --git a/dts/Bindings/pwm/pwm-samsung.yaml b/dts/Bindings/pwm/pwm-samsung.yaml
index 188679cb8b..fe603fb1b2 100644
--- a/dts/Bindings/pwm/pwm-samsung.yaml
+++ b/dts/Bindings/pwm/pwm-samsung.yaml
@@ -86,7 +86,6 @@ required:
- clocks
- clock-names
- compatible
- - "#pwm-cells"
- reg
additionalProperties: false
diff --git a/dts/Bindings/pwm/pwm-sifive.yaml b/dts/Bindings/pwm/pwm-sifive.yaml
index db41cd7bf1..605c1766db 100644
--- a/dts/Bindings/pwm/pwm-sifive.yaml
+++ b/dts/Bindings/pwm/pwm-sifive.yaml
@@ -21,6 +21,9 @@ description:
https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
+allOf:
+ - $ref: pwm.yaml#
+
properties:
compatible:
items:
@@ -54,7 +57,6 @@ required:
- compatible
- reg
- clocks
- - "#pwm-cells"
- interrupts
additionalProperties: false
diff --git a/dts/Bindings/pwm/pwm-tiecap.yaml b/dts/Bindings/pwm/pwm-tiecap.yaml
index ed35b6cc48..3840ae709b 100644
--- a/dts/Bindings/pwm/pwm-tiecap.yaml
+++ b/dts/Bindings/pwm/pwm-tiecap.yaml
@@ -47,7 +47,6 @@ properties:
required:
- compatible
- reg
- - "#pwm-cells"
- clocks
- clock-names
diff --git a/dts/Bindings/pwm/pwm-tiehrpwm.yaml b/dts/Bindings/pwm/pwm-tiehrpwm.yaml
index ee312cb210..70a8f76621 100644
--- a/dts/Bindings/pwm/pwm-tiehrpwm.yaml
+++ b/dts/Bindings/pwm/pwm-tiehrpwm.yaml
@@ -48,7 +48,6 @@ properties:
required:
- compatible
- reg
- - "#pwm-cells"
- clocks
- clock-names
diff --git a/dts/Bindings/pwm/renesas,pwm-rcar.yaml b/dts/Bindings/pwm/renesas,pwm-rcar.yaml
index 7ea1070b4b..1c94acbc2b 100644
--- a/dts/Bindings/pwm/renesas,pwm-rcar.yaml
+++ b/dts/Bindings/pwm/renesas,pwm-rcar.yaml
@@ -59,21 +59,23 @@ properties:
required:
- compatible
- reg
- - '#pwm-cells'
- clocks
- power-domains
-if:
- not:
- properties:
- compatible:
- contains:
- enum:
- - renesas,pwm-r8a7778
- - renesas,pwm-r8a7779
-then:
- required:
- - resets
+allOf:
+ - $ref: pwm.yaml#
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,pwm-r8a7778
+ - renesas,pwm-r8a7779
+ then:
+ required:
+ - resets
additionalProperties: false
diff --git a/dts/Bindings/pwm/renesas,tpu-pwm.yaml b/dts/Bindings/pwm/renesas,tpu-pwm.yaml
index 1f5c638418..c6b2ab56b7 100644
--- a/dts/Bindings/pwm/renesas,tpu-pwm.yaml
+++ b/dts/Bindings/pwm/renesas,tpu-pwm.yaml
@@ -68,7 +68,6 @@ properties:
required:
- compatible
- reg
- - '#pwm-cells'
- clocks
- power-domains
diff --git a/dts/Bindings/pwm/toshiba,pwm-visconti.yaml b/dts/Bindings/pwm/toshiba,pwm-visconti.yaml
index d350f5edfb..46622661e5 100644
--- a/dts/Bindings/pwm/toshiba,pwm-visconti.yaml
+++ b/dts/Bindings/pwm/toshiba,pwm-visconti.yaml
@@ -9,6 +9,9 @@ title: Toshiba Visconti PWM Controller
maintainers:
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
+allOf:
+ - $ref: pwm.yaml#
+
properties:
compatible:
items:
@@ -23,7 +26,6 @@ properties:
required:
- compatible
- reg
- - '#pwm-cells'
additionalProperties: false
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-28 05:13:34 +0000