diff options
Diffstat (limited to 'dts/Bindings/reset')
29 files changed, 248 insertions, 235 deletions
diff --git a/dts/Bindings/reset/altr,rst-mgr.yaml b/dts/Bindings/reset/altr,rst-mgr.yaml index 4379cec6b3..761c70cf9d 100644 --- a/dts/Bindings/reset/altr,rst-mgr.yaml +++ b/dts/Bindings/reset/altr,rst-mgr.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Altera SOCFPGA Reset Manager maintainers: - - Dinh Nguyen <dinguyen@altera.com> + - Dinh Nguyen <dinguyen@kernel.org> properties: compatible: @@ -32,9 +32,17 @@ properties: required: - compatible - reg - - altr,modrst-offset - '#reset-cells' +if: + properties: + compatible: + contains: + const: altr,stratix10-rst-mgr +then: + properties: + altr,modrst-offset: false + additionalProperties: false examples: diff --git a/dts/Bindings/reset/amlogic,meson-axg-audio-arb.yaml b/dts/Bindings/reset/amlogic,meson-axg-audio-arb.yaml index 704a502adc..bc1d284785 100644 --- a/dts/Bindings/reset/amlogic,meson-axg-audio-arb.yaml +++ b/dts/Bindings/reset/amlogic,meson-axg-audio-arb.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/amlogic,meson-axg-audio-arb.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/amlogic,meson-axg-audio-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic audio memory arbiter controller diff --git a/dts/Bindings/reset/amlogic,meson-reset.yaml b/dts/Bindings/reset/amlogic,meson-reset.yaml index 98db2aa74d..f0c6c0df0c 100644 --- a/dts/Bindings/reset/amlogic,meson-reset.yaml +++ b/dts/Bindings/reset/amlogic,meson-reset.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson SoC Reset Controller @@ -18,6 +18,7 @@ properties: - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs + - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs reg: maxItems: 1 diff --git a/dts/Bindings/reset/bitmain,bm1880-reset.yaml b/dts/Bindings/reset/bitmain,bm1880-reset.yaml index f0aca74438..1f40b654f6 100644 --- a/dts/Bindings/reset/bitmain,bm1880-reset.yaml +++ b/dts/Bindings/reset/bitmain,bm1880-reset.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Manivannan Sadhasivam <mani@kernel.org> %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/bitmain,bm1880-reset.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/bitmain,bm1880-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Bitmain BM1880 SoC Reset Controller diff --git a/dts/Bindings/reset/brcm,bcm6345-reset.yaml b/dts/Bindings/reset/brcm,bcm6345-reset.yaml index 560cf6522c..00150b93fc 100644 --- a/dts/Bindings/reset/brcm,bcm6345-reset.yaml +++ b/dts/Bindings/reset/brcm,bcm6345-reset.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: BCM6345 reset controller diff --git a/dts/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml b/dts/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml index dfce6738b0..34cfc642d8 100644 --- a/dts/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml +++ b/dts/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml @@ -2,8 +2,8 @@ # Copyright 2020 Broadcom %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/brcm,bcm7216-pcie-sata-rescal.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/brcm,bcm7216-pcie-sata-rescal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: BCM7216 RESCAL reset controller diff --git a/dts/Bindings/reset/brcm,brcmstb-reset.yaml b/dts/Bindings/reset/brcm,brcmstb-reset.yaml index e00efa88a1..b115b86e2f 100644 --- a/dts/Bindings/reset/brcm,brcmstb-reset.yaml +++ b/dts/Bindings/reset/brcm,brcmstb-reset.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Broadcom STB SW_INIT-style reset controller diff --git a/dts/Bindings/reset/canaan,k210-rst.yaml b/dts/Bindings/reset/canaan,k210-rst.yaml index ee8a2dcf5d..0c0135964b 100644 --- a/dts/Bindings/reset/canaan,k210-rst.yaml +++ b/dts/Bindings/reset/canaan,k210-rst.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Canaan Kendryte K210 Reset Controller maintainers: - - Damien Le Moal <damien.lemoal@wdc.com> + - Damien Le Moal <dlemoal@kernel.org> description: | Canaan Kendryte K210 reset controller driver which supports the SoC diff --git a/dts/Bindings/reset/fsl,imx-src.yaml b/dts/Bindings/reset/fsl,imx-src.yaml index b11ac533f9..f5ec1d54aa 100644 --- a/dts/Bindings/reset/fsl,imx-src.yaml +++ b/dts/Bindings/reset/fsl,imx-src.yaml @@ -28,28 +28,17 @@ description: | properties: compatible: oneOf: - - const: "fsl,imx51-src" + - const: fsl,imx51-src - items: - - const: "fsl,imx50-src" - - const: "fsl,imx51-src" - - items: - - const: "fsl,imx53-src" - - const: "fsl,imx51-src" - - items: - - const: "fsl,imx6q-src" - - const: "fsl,imx51-src" - - items: - - const: "fsl,imx6sx-src" - - const: "fsl,imx51-src" - - items: - - const: "fsl,imx6sl-src" - - const: "fsl,imx51-src" - - items: - - const: "fsl,imx6ul-src" - - const: "fsl,imx51-src" - - items: - - const: "fsl,imx6sll-src" - - const: "fsl,imx51-src" + - enum: + - fsl,imx50-src + - fsl,imx53-src + - fsl,imx6q-src + - fsl,imx6sx-src + - fsl,imx6sl-src + - fsl,imx6ul-src + - fsl,imx6sll-src + - const: fsl,imx51-src reg: maxItems: 1 diff --git a/dts/Bindings/reset/hisilicon,hi3660-reset.yaml b/dts/Bindings/reset/hisilicon,hi3660-reset.yaml index cdfcf32c53..e4de002d69 100644 --- a/dts/Bindings/reset/hisilicon,hi3660-reset.yaml +++ b/dts/Bindings/reset/hisilicon,hi3660-reset.yaml @@ -50,32 +50,9 @@ additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/irq.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/clock/hi3660-clock.h> - - iomcu: iomcu@ffd7e000 { - compatible = "hisilicon,hi3660-iomcu", "syscon"; - reg = <0xffd7e000 0x1000>; - }; - - iomcu_rst: iomcu_rst_controller { + iomcu_rst_controller { compatible = "hisilicon,hi3660-reset"; hisilicon,rst-syscon = <&iomcu>; #reset-cells = <2>; }; - - /* Specifying reset lines connected to IP modules */ - i2c@ffd71000 { - compatible = "snps,designware-i2c"; - reg = <0xffd71000 0x1000>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; - resets = <&iomcu_rst 0x20 3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; - }; ... diff --git a/dts/Bindings/reset/marvell,berlin2-reset.yaml b/dts/Bindings/reset/marvell,berlin2-reset.yaml index d71d0f0a13..dc86568bfd 100644 --- a/dts/Bindings/reset/marvell,berlin2-reset.yaml +++ b/dts/Bindings/reset/marvell,berlin2-reset.yaml @@ -2,8 +2,8 @@ # Copyright 2015 Antoine Tenart <atenart@kernel.org> %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/marvell,berlin2-reset.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/marvell,berlin2-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Marvell Berlin reset controller diff --git a/dts/Bindings/reset/microchip,rst.yaml b/dts/Bindings/reset/microchip,rst.yaml index 81cd8c8376..f2da0693b0 100644 --- a/dts/Bindings/reset/microchip,rst.yaml +++ b/dts/Bindings/reset/microchip,rst.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/microchip,rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip Sparx5 Switch Reset Controller @@ -36,7 +36,7 @@ properties: const: 1 cpu-syscon: - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle description: syscon used to access CPU reset required: diff --git a/dts/Bindings/reset/mobileye,eyeq5-reset.yaml b/dts/Bindings/reset/mobileye,eyeq5-reset.yaml new file mode 100644 index 0000000000..062b451834 --- /dev/null +++ b/dts/Bindings/reset/mobileye,eyeq5-reset.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mobileye,eyeq5-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 reset controller + +description: + The EyeQ5 reset driver handles three reset domains. Its registers live in a + shared region called OLB. + +maintainers: + - Grégory Clement <gregory.clement@bootlin.com> + - Théo Lebrun <theo.lebrun@bootlin.com> + - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> + +properties: + compatible: + const: mobileye,eyeq5-reset + + reg: + maxItems: 3 + + reg-names: + items: + - const: d0 + - const: d1 + - const: d2 + + "#reset-cells": + const: 2 + description: + The first cell is the domain (0 to 2 inclusive) and the second one is the + reset index inside that domain. + +required: + - compatible + - reg + - reg-names + - "#reset-cells" + +additionalProperties: false diff --git a/dts/Bindings/reset/nuvoton,ma35d1-reset.yaml b/dts/Bindings/reset/nuvoton,ma35d1-reset.yaml new file mode 100644 index 0000000000..34c5c1c08e --- /dev/null +++ b/dts/Bindings/reset/nuvoton,ma35d1-reset.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Reset Controller + +maintainers: + - Chi-Fang Li <cfli0@nuvoton.com> + - Jacky Huang <ychuang3@nuvoton.com> + +description: + The system reset controller can be used to reset various peripheral + controllers in MA35D1 SoC. + +properties: + compatible: + items: + - const: nuvoton,ma35d1-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + # system reset controller node: + - | + + system-management@40460000 { + compatible = "nuvoton,ma35d1-reset"; + reg = <0x40460000 0x200>; + #reset-cells = <1>; + }; +... + diff --git a/dts/Bindings/reset/oxnas,reset.txt b/dts/Bindings/reset/oxnas,reset.txt deleted file mode 100644 index d27ccb5d04..0000000000 --- a/dts/Bindings/reset/oxnas,reset.txt +++ /dev/null @@ -1,32 +0,0 @@ -Oxford Semiconductor OXNAS SoC Family RESET Controller -================================================ - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: For OX810SE, should be "oxsemi,ox810se-reset" - For OX820, should be "oxsemi,ox820-reset" -- #reset-cells: 1, see below - -Parent node should have the following properties : -- compatible: For OX810SE, should be : - "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" - For OX820, should be : - "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd" - -Reset indices are in dt-bindings include files : -- For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h -- For OX820: include/dt-bindings/reset/oxsemi,ox820.h - -example: - -sys: sys-ctrl@000000 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - reset: reset-controller { - compatible = "oxsemi,ox810se-reset"; - #reset-cells = <1>; - }; -}; diff --git a/dts/Bindings/reset/qca,ar7100-reset.yaml b/dts/Bindings/reset/qca,ar7100-reset.yaml index 9be60e55cd..47f8525a9b 100644 --- a/dts/Bindings/reset/qca,ar7100-reset.yaml +++ b/dts/Bindings/reset/qca,ar7100-reset.yaml @@ -2,8 +2,8 @@ # Copyright 2015 Alban Bedel <albeu@free.fr> %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/qca,ar7100-reset.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/qca,ar7100-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Atheros AR7xxx/AR9XXX reset controller diff --git a/dts/Bindings/reset/qcom,aoss-reset.yaml b/dts/Bindings/reset/qcom,aoss-reset.yaml index d92e2b3cc8..24beb712b5 100644 --- a/dts/Bindings/reset/qcom,aoss-reset.yaml +++ b/dts/Bindings/reset/qcom,aoss-reset.yaml @@ -18,17 +18,17 @@ properties: oneOf: - description: on SC7180 SoCs the following compatibles must be specified items: - - const: "qcom,sc7180-aoss-cc" - - const: "qcom,sdm845-aoss-cc" + - const: qcom,sc7180-aoss-cc + - const: qcom,sdm845-aoss-cc - description: on SC7280 SoCs the following compatibles must be specified items: - - const: "qcom,sc7280-aoss-cc" - - const: "qcom,sdm845-aoss-cc" + - const: qcom,sc7280-aoss-cc + - const: qcom,sdm845-aoss-cc - description: on SDM845 SoCs the following compatibles must be specified items: - - const: "qcom,sdm845-aoss-cc" + - const: qcom,sdm845-aoss-cc reg: maxItems: 1 diff --git a/dts/Bindings/reset/qcom,pdc-global.yaml b/dts/Bindings/reset/qcom,pdc-global.yaml index ca5d793321..f514363aa4 100644 --- a/dts/Bindings/reset/qcom,pdc-global.yaml +++ b/dts/Bindings/reset/qcom,pdc-global.yaml @@ -18,16 +18,16 @@ properties: oneOf: - description: on SC7180 SoCs the following compatibles must be specified items: - - const: "qcom,sc7180-pdc-global" - - const: "qcom,sdm845-pdc-global" + - const: qcom,sc7180-pdc-global + - const: qcom,sdm845-pdc-global - description: on SC7280 SoCs the following compatibles must be specified items: - - const: "qcom,sc7280-pdc-global" + - const: qcom,sc7280-pdc-global - description: on SDM845 SoCs the following compatibles must be specified items: - - const: "qcom,sdm845-pdc-global" + - const: qcom,sdm845-pdc-global reg: maxItems: 1 diff --git a/dts/Bindings/reset/renesas,rst.yaml b/dts/Bindings/reset/renesas,rst.yaml index 0d1b89e2fe..58b4a45d33 100644 --- a/dts/Bindings/reset/renesas,rst.yaml +++ b/dts/Bindings/reset/renesas,rst.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/renesas,rst.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/renesas,rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas R-Car and RZ/G Reset Controller @@ -50,6 +50,7 @@ properties: - renesas,r8a779a0-rst # R-Car V3U - renesas,r8a779f0-rst # R-Car S4-8 - renesas,r8a779g0-rst # R-Car V4H + - renesas,r8a779h0-rst # R-Car V4M reg: maxItems: 1 diff --git a/dts/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/dts/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml index 731b8ce015..03c18611e4 100644 --- a/dts/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml +++ b/dts/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -17,7 +17,7 @@ properties: compatible: items: - enum: - - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} - renesas,r9a07g054-usbphy-ctrl # RZ/V2L - const: renesas,rzg2l-usbphy-ctrl diff --git a/dts/Bindings/reset/socionext,uniphier-glue-reset.yaml b/dts/Bindings/reset/socionext,uniphier-glue-reset.yaml index 0a2c13e1e2..fa253c518d 100644 --- a/dts/Bindings/reset/socionext,uniphier-glue-reset.yaml +++ b/dts/Bindings/reset/socionext,uniphier-glue-reset.yaml @@ -95,19 +95,12 @@ required: examples: - | - usb-glue@65b00000 { - compatible = "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_rst: reset@0 { - compatible = "socionext,uniphier-ld20-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; + usb_rst: reset-controller@0 { + compatible = "socionext,uniphier-ld20-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; }; diff --git a/dts/Bindings/reset/socionext,uniphier-reset.yaml b/dts/Bindings/reset/socionext,uniphier-reset.yaml index 6566804ec5..033b252a3d 100644 --- a/dts/Bindings/reset/socionext,uniphier-reset.yaml +++ b/dts/Bindings/reset/socionext,uniphier-reset.yaml @@ -66,53 +66,7 @@ required: examples: - | - sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - reset { - compatible = "socionext,uniphier-ld11-reset"; - #reset-cells = <1>; - }; - - // other nodes ... - }; - - - | - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - reset { - compatible = "socionext,uniphier-ld11-mio-reset"; - #reset-cells = <1>; - }; - - // other nodes ... - }; - - - | - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - reset { - compatible = "socionext,uniphier-ld11-peri-reset"; - #reset-cells = <1>; - }; - - // other nodes ... - }; - - - | - adamv@57920000 { - compatible = "socionext,uniphier-ld11-adamv", "simple-mfd", "syscon"; - reg = <0x57920000 0x1000>; - - reset { - compatible = "socionext,uniphier-ld11-adamv-reset"; - #reset-cells = <1>; - }; - - // other nodes ... + reset-controller { + compatible = "socionext,uniphier-ld11-reset"; + #reset-cells = <1>; }; diff --git a/dts/Bindings/reset/sophgo,sg2042-reset.yaml b/dts/Bindings/reset/sophgo,sg2042-reset.yaml new file mode 100644 index 0000000000..76e1931f09 --- /dev/null +++ b/dts/Bindings/reset/sophgo,sg2042-reset.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 SoC Reset Controller + +maintainers: + - Chen Wang <unicorn_wang@outlook.com> + +properties: + compatible: + const: sophgo,sg2042-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rstgen: reset-controller@c00 { + compatible = "sophgo,sg2042-reset"; + reg = <0xc00 0xc>; + #reset-cells = <1>; + }; diff --git a/dts/Bindings/reset/sunplus,reset.yaml b/dts/Bindings/reset/sunplus,reset.yaml index f24646ba97..205918ce32 100644 --- a/dts/Bindings/reset/sunplus,reset.yaml +++ b/dts/Bindings/reset/sunplus,reset.yaml @@ -2,8 +2,8 @@ # Copyright (C) Sunplus Co., Ltd. 2021 %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/sunplus,reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Sunplus SoC Reset Controller diff --git a/dts/Bindings/reset/ti,sci-reset.yaml b/dts/Bindings/reset/ti,sci-reset.yaml index dcf9206e12..e10eb98edd 100644 --- a/dts/Bindings/reset/ti,sci-reset.yaml +++ b/dts/Bindings/reset/ti,sci-reset.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml# diff --git a/dts/Bindings/reset/ti,tps380x-reset.yaml b/dts/Bindings/reset/ti,tps380x-reset.yaml index f436f2cf1d..6063784f03 100644 --- a/dts/Bindings/reset/ti,tps380x-reset.yaml +++ b/dts/Bindings/reset/ti,tps380x-reset.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/reset/ti,tps380x-reset.yaml# diff --git a/dts/Bindings/reset/ti-syscon-reset.txt b/dts/Bindings/reset/ti-syscon-reset.txt index 86945502cc..61a0ff33e8 100644 --- a/dts/Bindings/reset/ti-syscon-reset.txt +++ b/dts/Bindings/reset/ti-syscon-reset.txt @@ -43,7 +43,7 @@ Required properties: Cell #6 : bit position of the reset in the reset status register Cell #7 : Flags used to control reset behavior, - availible flags defined in the DT include + available flags defined in the DT include file <dt-bindings/reset/ti-syscon.h> SysCon Reset Consumer Nodes diff --git a/dts/Bindings/reset/xlnx,zynqmp-reset.txt b/dts/Bindings/reset/xlnx,zynqmp-reset.txt deleted file mode 100644 index ed836868db..0000000000 --- a/dts/Bindings/reset/xlnx,zynqmp-reset.txt +++ /dev/null @@ -1,55 +0,0 @@ --------------------------------------------------------------------------- - = Zynq UltraScale+ MPSoC and Versal reset driver binding = --------------------------------------------------------------------------- -The Zynq UltraScale+ MPSoC and Versal has several different resets. - -See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information -about zynqmp resets. - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required Properties: -- compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform - "xlnx,versal-reset" for Versal platform -- #reset-cells: Specifies the number of cells needed to encode reset - line, should be 1 - -------- -Example -------- - -firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - method = "smc"; - - zynqmp_reset: reset-controller { - compatible = "xlnx,zynqmp-reset"; - #reset-cells = <1>; - }; - }; -}; - -Specifying reset lines connected to IP modules -============================================== - -Device nodes that need access to reset lines should -specify them as a reset phandle in their corresponding node as -specified in reset.txt. - -For list of all valid reset indices for Zynq UltraScale+ MPSoC see -<dt-bindings/reset/xlnx-zynqmp-resets.h> -For list of all valid reset indices for Versal see -<dt-bindings/reset/xlnx-versal-resets.h> - -Example: - -serdes: zynqmp_phy@fd400000 { - ... - - resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - reset-names = "sata_rst"; - - ... -}; diff --git a/dts/Bindings/reset/xlnx,zynqmp-reset.yaml b/dts/Bindings/reset/xlnx,zynqmp-reset.yaml new file mode 100644 index 0000000000..1f1b42dde9 --- /dev/null +++ b/dts/Bindings/reset/xlnx,zynqmp-reset.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Zynq UltraScale+ MPSoC and Versal reset + +maintainers: + - Mubin Sayyed <mubin.sayyed@amd.com> + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> + +description: | + The Zynq UltraScale+ MPSoC and Versal has several different resets. + + The PS reset subsystem is responsible for handling the external reset + input to the device and that all internal reset requirements are met + for the system (as a whole) and for the functional units. + + Please also refer to reset.txt in this directory for common reset + controller binding usage. Device nodes that need access to reset + lines should specify them as a reset phandle in their corresponding + node as specified in reset.txt. + + For list of all valid reset indices for Zynq UltraScale+ MPSoC + <dt-bindings/reset/xlnx-zynqmp-resets.h> + + For list of all valid reset indices for Versal + <dt-bindings/reset/xlnx-versal-resets.h> + +properties: + compatible: + enum: + - xlnx,zynqmp-reset + - xlnx,versal-reset + - xlnx,versal-net-reset + + "#reset-cells": + const: 1 + +required: + - compatible + - "#reset-cells" + +additionalProperties: false + +examples: + - | + zynqmp_reset: reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; + +... |