diff options
Diffstat (limited to 'dts/Bindings/serial/fsl-imx-uart.yaml')
| -rw-r--r-- | dts/Bindings/serial/fsl-imx-uart.yaml | 65 |
1 files changed, 53 insertions, 12 deletions
diff --git a/dts/Bindings/serial/fsl-imx-uart.yaml b/dts/Bindings/serial/fsl-imx-uart.yaml index 9d949296a1..9c6dc16f88 100644 --- a/dts/Bindings/serial/fsl-imx-uart.yaml +++ b/dts/Bindings/serial/fsl-imx-uart.yaml @@ -9,10 +9,6 @@ title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART) maintainers: - Fabio Estevam <festevam@gmail.com> -allOf: - - $ref: "serial.yaml" - - $ref: "rs485.yaml" - properties: compatible: oneOf: @@ -49,8 +45,32 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: per + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + interrupts: - maxItems: 1 + items: + - description: UART RX Interrupt + - description: UART TX Interrupt + - description: UART RTS Interrupt + minItems: 1 + + wakeup-source: true fsl,dte-mode: $ref: /schemas/types.yaml#/definitions/flag @@ -83,22 +103,38 @@ properties: are sensible for most use cases. If you need low latency processing on slow connections this needs to be configured appropriately. - uart-has-rtscts: true - - rs485-rts-delay: true - rs485-rts-active-low: true - rs485-rx-during-tx: true - linux,rs485-enabled-at-boot-time: true - required: - compatible - reg + - clocks + - clock-names - interrupts +allOf: + - $ref: serial.yaml# + - $ref: rs485.yaml# + + - if: + properties: + compatible: + contains: + const: fsl,imx1-uart + then: + properties: + interrupts: + minItems: 3 + maxItems: 3 + else: + properties: + interrupts: + maxItems: 1 + unevaluatedProperties: false examples: - | + #include <dt-bindings/clock/imx5-clock.h> + aliases { serial0 = &uart1; }; @@ -107,6 +143,11 @@ examples: compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; interrupts = <31>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 18 4 1>, <&sdma 19 4 2>; + dma-names = "rx", "tx"; uart-has-rtscts; fsl,dte-mode; }; |