diff options
Diffstat (limited to 'dts/Bindings/soc/xilinx')
| -rw-r--r-- | dts/Bindings/soc/xilinx/xlnx,vcu-settings.yaml | 43 | ||||
| -rw-r--r-- | dts/Bindings/soc/xilinx/xlnx,vcu.txt | 9 |
2 files changed, 45 insertions, 7 deletions
diff --git a/dts/Bindings/soc/xilinx/xlnx,vcu-settings.yaml b/dts/Bindings/soc/xilinx/xlnx,vcu-settings.yaml new file mode 100644 index 0000000000..cb245f4002 --- /dev/null +++ b/dts/Bindings/soc/xilinx/xlnx,vcu-settings.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/xilinx/xlnx,vcu-settings.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx VCU Settings + +maintainers: + - Michael Tretter <kernel@pengutronix.de> + +description: | + The Xilinx VCU Settings provides information about the configuration of the + video codec unit. + +properties: + compatible: + items: + - const: xlnx,vcu-settings + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + fpga { + #address-cells = <2>; + #size-cells = <2>; + + xlnx_vcu: vcu@a0041000 { + compatible = "xlnx,vcu-settings", "syscon"; + reg = <0x0 0xa0041000 0x0 0x1000>; + }; + }; + +... diff --git a/dts/Bindings/soc/xilinx/xlnx,vcu.txt b/dts/Bindings/soc/xilinx/xlnx,vcu.txt index 6786d6715d..2417b13ba4 100644 --- a/dts/Bindings/soc/xilinx/xlnx,vcu.txt +++ b/dts/Bindings/soc/xilinx/xlnx,vcu.txt @@ -12,10 +12,7 @@ Required properties: - compatible: shall be one of: "xlnx,vcu" "xlnx,vcu-logicoreip-1.0" -- reg, reg-names: There are two sets of registers need to provide. - 1. vcu slcr - 2. Logicore - reg-names should contain name for the each register sequence. +- reg : The base offset and size of the VCU_PL_SLCR register space. - clocks: phandle for aclk and pll_ref clocksource - clock-names: The identification string, "aclk", is always required for the axi clock. "pll_ref" is required for pll. @@ -23,9 +20,7 @@ Example: xlnx_vcu: vcu@a0040000 { compatible = "xlnx,vcu-logicoreip-1.0"; - reg = <0x0 0xa0040000 0x0 0x1000>, - <0x0 0xa0041000 0x0 0x1000>; - reg-names = "vcu_slcr", "logicore"; + reg = <0x0 0xa0040000 0x0 0x1000>; clocks = <&si570_1>, <&clkc 71>; clock-names = "pll_ref", "aclk"; }; |