diff options
Diffstat (limited to 'dts/Bindings/soc')
| -rw-r--r-- | dts/Bindings/soc/fsl/cpm_qe/gpio.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/soc/fsl/cpm_qe/qe/ucc.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/soc/fsl/cpm_qe/qe/usb.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/soc/mediatek/pwrap.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/soc/qcom/qcom,geni-se.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/soc/qcom/qcom,glink.txt | 5 | ||||
| -rw-r--r-- | dts/Bindings/soc/qcom/rpmh-rsc.txt | 137 |
7 files changed, 144 insertions, 5 deletions
diff --git a/dts/Bindings/soc/fsl/cpm_qe/gpio.txt b/dts/Bindings/soc/fsl/cpm_qe/gpio.txt index 626e1afa64..cce3cd71e8 100644 --- a/dts/Bindings/soc/fsl/cpm_qe/gpio.txt +++ b/dts/Bindings/soc/fsl/cpm_qe/gpio.txt @@ -21,7 +21,6 @@ Optional properties: one as described by the fsl,cpm1-gpio-irq-mask property. There should be as many interrupts as number of ones in the mask property. The first interrupt in the list corresponds to the most significant bit of the mask. -- interrupt-parent : Parent for the above interrupt property. Example of four SOC GPIO banks defined as gpio-controller nodes: diff --git a/dts/Bindings/soc/fsl/cpm_qe/qe/ucc.txt b/dts/Bindings/soc/fsl/cpm_qe/qe/ucc.txt index e47734bee3..5efb7ac94c 100644 --- a/dts/Bindings/soc/fsl/cpm_qe/qe/ucc.txt +++ b/dts/Bindings/soc/fsl/cpm_qe/qe/ucc.txt @@ -11,8 +11,6 @@ Required properties: information for the interrupt. This should be encoded based on the information in section 2) depending on the type of interrupt controller you have. -- interrupt-parent : the phandle for the interrupt controller that - services interrupts for this device. - pio-handle : The phandle for the Parallel I/O port configuration. - port-number : for UART drivers, the port number to use, between 0 and 3. This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0. diff --git a/dts/Bindings/soc/fsl/cpm_qe/qe/usb.txt b/dts/Bindings/soc/fsl/cpm_qe/qe/usb.txt index 9ccd5f3040..da13999337 100644 --- a/dts/Bindings/soc/fsl/cpm_qe/qe/usb.txt +++ b/dts/Bindings/soc/fsl/cpm_qe/qe/usb.txt @@ -6,7 +6,6 @@ Required properties: length, the next two two cells should contain PRAM location and length. - interrupts : should contain USB interrupt. -- interrupt-parent : interrupt source phandle. - fsl,fullspeed-clock : specifies the full speed USB clock source: "none": clock source is disabled "brg1" through "brg16": clock source is BRG1-BRG16, respectively diff --git a/dts/Bindings/soc/mediatek/pwrap.txt b/dts/Bindings/soc/mediatek/pwrap.txt index bf80e3f96f..f9987c30f0 100644 --- a/dts/Bindings/soc/mediatek/pwrap.txt +++ b/dts/Bindings/soc/mediatek/pwrap.txt @@ -19,6 +19,7 @@ IP Pairing Required properties in pwrap device node. - compatible: "mediatek,mt2701-pwrap" for MT2701/7623 SoCs + "mediatek,mt6797-pwrap" for MT6797 SoCs "mediatek,mt7622-pwrap" for MT7622 SoCs "mediatek,mt8135-pwrap" for MT8135 SoCs "mediatek,mt8173-pwrap" for MT8173 SoCs diff --git a/dts/Bindings/soc/qcom/qcom,geni-se.txt b/dts/Bindings/soc/qcom/qcom,geni-se.txt index 68b7d6207e..ff92e5a41b 100644 --- a/dts/Bindings/soc/qcom/qcom,geni-se.txt +++ b/dts/Bindings/soc/qcom/qcom,geni-se.txt @@ -46,7 +46,7 @@ Child nodes should conform to I2C bus binding as described in i2c.txt. Qualcomm Technologies Inc. GENI Serial Engine based UART Controller Required properties: -- compatible: Must be "qcom,geni-debug-uart". +- compatible: Must be "qcom,geni-debug-uart" or "qcom,geni-uart". - reg: Must contain UART register location and length. - interrupts: Must contain UART core interrupts. - clock-names: Must contain "se". diff --git a/dts/Bindings/soc/qcom/qcom,glink.txt b/dts/Bindings/soc/qcom/qcom,glink.txt index 9663cab522..0b8cc533ca 100644 --- a/dts/Bindings/soc/qcom/qcom,glink.txt +++ b/dts/Bindings/soc/qcom/qcom,glink.txt @@ -10,6 +10,11 @@ edge. Value type: <stringlist> Definition: must be "qcom,glink-rpm" +- label: + Usage: optional + Value type: <string> + Definition: should specify the subsystem name this edge corresponds to. + - interrupts: Usage: required Value type: <prop-encoded-array> diff --git a/dts/Bindings/soc/qcom/rpmh-rsc.txt b/dts/Bindings/soc/qcom/rpmh-rsc.txt new file mode 100644 index 0000000000..9b86d1eff2 --- /dev/null +++ b/dts/Bindings/soc/qcom/rpmh-rsc.txt @@ -0,0 +1,137 @@ +RPMH RSC: +------------ + +Resource Power Manager Hardened (RPMH) is the mechanism for communicating with +the hardened resource accelerators on Qualcomm SoCs. Requests to the resources +can be written to the Trigger Command Set (TCS) registers and using a (addr, +val) pair and triggered. Messages in the TCS are then sent in sequence over an +internal bus. + +The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity +(Resource State Coordinator a.k.a RSC) that can handle multiple sleep and +active/wake resource requests. Multiple such DRVs can exist in a SoC and can +be written to from Linux. The structure of each DRV follows the same template +with a few variations that are captured by the properties here. + +A TCS may be triggered from Linux or triggered by the F/W after all the CPUs +have powered off to facilitate idle power saving. TCS could be classified as - + + ACTIVE /* Triggered by Linux */ + SLEEP /* Triggered by F/W */ + WAKE /* Triggered by F/W */ + CONTROL /* Triggered by F/W */ + +The order in which they are described in the DT, should match the hardware +configuration. + +Requests can be made for the state of a resource, when the subsystem is active +or idle. When all subsystems like Modem, GPU, CPU are idle, the resource state +will be an aggregate of the sleep votes from each of those subsystems. Clients +may request a sleep value for their shared resources in addition to the active +mode requests. + +Properties: + +- compatible: + Usage: required + Value type: <string> + Definition: Should be "qcom,rpmh-rsc". + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: The first register specifies the base address of the + DRV(s). The number of DRVs in the dependent on the RSC. + The tcs-offset specifies the start address of the + TCS in the DRVs. + +- reg-names: + Usage: required + Value type: <string> + Definition: Maps the register specified in the reg property. Must be + "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The + +- interrupts: + Usage: required + Value type: <prop-encoded-interrupt> + Definition: The interrupt that trips when a message complete/response + is received for this DRV from the accelerators. + +- qcom,drv-id: + Usage: required + Value type: <u32> + Definition: The id of the DRV in the RSC block that will be used by + this controller. + +- qcom,tcs-config: + Usage: required + Value type: <prop-encoded-array> + Definition: The tuple defining the configuration of TCS. + Must have 2 cells which describe each TCS type. + <type number_of_tcs>. + The order of the TCS must match the hardware + configuration. + - Cell #1 (TCS Type): TCS types to be specified - + ACTIVE_TCS + SLEEP_TCS + WAKE_TCS + CONTROL_TCS + - Cell #2 (Number of TCS): <u32> + +- label: + Usage: optional + Value type: <string> + Definition: Name for the RSC. The name would be used in trace logs. + +Drivers that want to use the RSC to communicate with RPMH must specify their +bindings as child nodes of the RSC controllers they wish to communicate with. + +Example 1: + +For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the +register offsets for DRV2 start at 0D00, the register calculations are like +this - +DRV0: 0x179C0000 +DRV2: 0x179C0000 + 0x10000 = 0x179D0000 +DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000 +TCS-OFFSET: 0xD00 + + apps_rsc: rsc@179c0000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x179c0000 0x10000>, + <0x179d0000 0x10000>, + <0x179e0000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, + <SLEEP_TCS 3>, + <WAKE_TCS 3>, + <CONTROL_TCS 1>; + }; + +Example 2: + +For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the +register offsets for DRV0 start at 01C00, the register calculations are like +this - +DRV0: 0xAF20000 +TCS-OFFSET: 0x1C00 + + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0x1c00>; + qcom,drv-id = <0>; + qcom,tcs-config = <ACTIVE_TCS 0>, + <SLEEP_TCS 1>, + <WAKE_TCS 1>, + <CONTROL_TCS 0>; + }; |