diff options
Diffstat (limited to 'dts/Bindings/spi')
65 files changed, 1300 insertions, 620 deletions
diff --git a/dts/Bindings/spi/adi,axi-spi-engine.txt b/dts/Bindings/spi/adi,axi-spi-engine.txt deleted file mode 100644 index 8a18d71e68..0000000000 --- a/dts/Bindings/spi/adi,axi-spi-engine.txt +++ /dev/null @@ -1,31 +0,0 @@ -Analog Devices AXI SPI Engine controller Device Tree Bindings - -Required properties: -- compatible : Must be "adi,axi-spi-engine-1.00.a"" -- reg : Physical base address and size of the register map. -- interrupts : Property with a value describing the interrupt - number. -- clock-names : List of input clock names - "s_axi_aclk", "spi_clk" -- clocks : Clock phandles and specifiers (See clock bindings for - details on clock-names and clocks). -- #address-cells : Must be <1> -- #size-cells : Must be <0> - -Optional subnodes: - Subnodes are use to represent the SPI slave devices connected to the SPI - master. They follow the generic SPI bindings as outlined in spi-bus.txt. - -Example: - - spi@@44a00000 { - compatible = "adi,axi-spi-engine-1.00.a"; - reg = <0x44a00000 0x1000>; - interrupts = <0 56 4>; - clocks = <&clkc 15 &clkc 15>; - clock-names = "s_axi_aclk", "spi_clk"; - - #address-cells = <1>; - #size-cells = <0>; - - /* SPI devices */ - }; diff --git a/dts/Bindings/spi/adi,axi-spi-engine.yaml b/dts/Bindings/spi/adi,axi-spi-engine.yaml new file mode 100644 index 0000000000..d48faa42d0 --- /dev/null +++ b/dts/Bindings/spi/adi,axi-spi-engine.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AXI SPI Engine Controller + +description: | + The AXI SPI Engine controller is part of the SPI Engine framework[1] and + allows memory mapped access to the SPI Engine control bus. This allows it + to be used as a general purpose software driven SPI controller as well as + some optional advanced acceleration and offloading capabilities. + + [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine + +maintainers: + - Michael Hennerich <Michael.Hennerich@analog.com> + - Nuno Sá <nuno.sa@analog.com> + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: adi,axi-spi-engine-1.00.a + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The AXI interconnect clock. + - description: The SPI controller clock. + + clock-names: + items: + - const: s_axi_aclk + - const: spi_clk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + spi@44a00000 { + compatible = "adi,axi-spi-engine-1.00.a"; + reg = <0x44a00000 0x1000>; + interrupts = <0 56 4>; + clocks = <&clkc 15>, <&clkc 15>; + clock-names = "s_axi_aclk", "spi_clk"; + + #address-cells = <1>; + #size-cells = <0>; + + /* SPI devices */ + }; diff --git a/dts/Bindings/spi/allwinner,sun4i-a10-spi.yaml b/dts/Bindings/spi/allwinner,sun4i-a10-spi.yaml index f1176a28fd..e1ab3f523a 100644 --- a/dts/Bindings/spi/allwinner,sun4i-a10-spi.yaml +++ b/dts/Bindings/spi/allwinner,sun4i-a10-spi.yaml @@ -7,16 +7,13 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner A10 SPI Controller allOf: - - $ref: "spi-controller.yaml" + - $ref: spi-controller.yaml maintainers: - Chen-Yu Tsai <wens@csie.org> - Maxime Ripard <mripard@kernel.org> properties: - "#address-cells": true - "#size-cells": true - compatible: const: allwinner,sun4i-a10-spi @@ -46,11 +43,11 @@ properties: - const: rx - const: tx - num-cs: true - patternProperties: "^.*@[0-9a-f]+": type: object + additionalProperties: true + properties: reg: items: @@ -70,7 +67,7 @@ required: - clocks - clock-names -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml b/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml index 58b7056f4a..3b47b68b92 100644 --- a/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -7,18 +7,16 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner A31 SPI Controller allOf: - - $ref: "spi-controller.yaml" + - $ref: spi-controller.yaml maintainers: - Chen-Yu Tsai <wens@csie.org> - Maxime Ripard <mripard@kernel.org> properties: - "#address-cells": true - "#size-cells": true - compatible: oneOf: + - const: allwinner,sun50i-r329-spi - const: allwinner,sun6i-a31-spi - const: allwinner,sun8i-h3-spi - items: @@ -28,6 +26,15 @@ properties: - allwinner,sun50i-h616-spi - allwinner,suniv-f1c100s-spi - const: allwinner,sun8i-h3-spi + - items: + - enum: + - allwinner,sun20i-d1-spi + - allwinner,sun50i-r329-spi-dbi + - const: allwinner,sun50i-r329-spi + - items: + - const: allwinner,sun20i-d1-spi-dbi + - const: allwinner,sun50i-r329-spi-dbi + - const: allwinner,sun50i-r329-spi reg: maxItems: 1 @@ -58,11 +65,11 @@ properties: - const: rx - const: tx - num-cs: true - patternProperties: "^.*@[0-9a-f]+": type: object + additionalProperties: true + properties: reg: items: @@ -82,7 +89,7 @@ required: - clocks - clock-names -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/spi/amlogic,a1-spifc.yaml b/dts/Bindings/spi/amlogic,a1-spifc.yaml new file mode 100644 index 0000000000..ea47d30eef --- /dev/null +++ b/dts/Bindings/spi/amlogic,a1-spifc.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/amlogic,a1-spifc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A1 SPI Flash Controller + +maintainers: + - Martin Kurbanov <mmkurbanov@sberdevices.ru> + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + enum: + - amlogic,a1-spifc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + spi@fd000400 { + compatible = "amlogic,a1-spifc"; + reg = <0xfd000400 0x290>; + clocks = <&clkc_clkid_spifc>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/dts/Bindings/spi/amlogic,meson-gx-spicc.yaml b/dts/Bindings/spi/amlogic,meson-gx-spicc.yaml index 53eb6562b9..4e28e6e9d8 100644 --- a/dts/Bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/dts/Bindings/spi/amlogic,meson-gx-spicc.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson SPI Communication Controller @@ -41,7 +41,7 @@ properties: maxItems: 2 allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# - if: properties: compatible: @@ -100,17 +100,17 @@ unevaluatedProperties: false examples: - | spi@c1108d80 { - compatible = "amlogic,meson-gx-spicc"; - reg = <0xc1108d80 0x80>; - interrupts = <112>; - clocks = <&clk81>; - clock-names = "core"; - #address-cells = <1>; - #size-cells = <0>; - - display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <1000000>; - reg = <0>; - }; + compatible = "amlogic,meson-gx-spicc"; + reg = <0xc1108d80 0x80>; + interrupts = <112>; + clocks = <&clk81>; + clock-names = "core"; + #address-cells = <1>; + #size-cells = <0>; + + display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <1000000>; + reg = <0>; + }; }; diff --git a/dts/Bindings/spi/amlogic,meson6-spifc.yaml b/dts/Bindings/spi/amlogic,meson6-spifc.yaml index ac3b2ec300..8e769ccda9 100644 --- a/dts/Bindings/spi/amlogic,meson6-spifc.yaml +++ b/dts/Bindings/spi/amlogic,meson6-spifc.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson SPI Flash Controller @@ -11,7 +11,7 @@ maintainers: - Neil Armstrong <neil.armstrong@linaro.org> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# description: | The Meson SPIFC is a controller optimized for communication with SPI @@ -40,15 +40,15 @@ unevaluatedProperties: false examples: - | spi@c1108c80 { - compatible = "amlogic,meson6-spifc"; - reg = <0xc1108c80 0x80>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - - flash: flash@0 { - compatible = "spansion,m25p80", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; + compatible = "amlogic,meson6-spifc"; + reg = <0xc1108c80 0x80>; + clocks = <&clk81>; + #address-cells = <1>; + #size-cells = <0>; + + flash: flash@0 { + compatible = "spansion,m25p80", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; }; diff --git a/dts/Bindings/spi/arm,pl022-peripheral-props.yaml b/dts/Bindings/spi/arm,pl022-peripheral-props.yaml new file mode 100644 index 0000000000..bb8b6863b1 --- /dev/null +++ b/dts/Bindings/spi/arm,pl022-peripheral-props.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/arm,pl022-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral-specific properties for Arm PL022 SPI controller + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +select: false + +properties: + pl022,interface: + description: SPI interface type + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # SPI + - 1 # Texas Instruments Synchronous Serial Frame Format + - 2 # Microwire (Half Duplex) + + pl022,com-mode: + description: Specifies the transfer mode + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # interrupt mode + - 1 # polling mode + - 2 # DMA mode + default: 1 + + pl022,rx-level-trig: + description: Rx FIFO watermark level + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 4 + + pl022,tx-level-trig: + description: Tx FIFO watermark level + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 4 + + pl022,ctrl-len: + description: Microwire interface - Control length + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x03 + maximum: 0x1f + + pl022,wait-state: + description: Microwire interface - Wait state + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + pl022,duplex: + description: Microwire interface - Full/Half duplex + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + +additionalProperties: true +... diff --git a/dts/Bindings/spi/aspeed,ast2600-fmc.yaml b/dts/Bindings/spi/aspeed,ast2600-fmc.yaml index e6c817de34..57d932af45 100644 --- a/dts/Bindings/spi/aspeed,ast2600-fmc.yaml +++ b/dts/Bindings/spi/aspeed,ast2600-fmc.yaml @@ -15,7 +15,7 @@ description: | SPI) of the AST2400, AST2500 and AST2600 SOCs. allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: @@ -60,23 +60,23 @@ examples: interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; flash@0 { - reg = < 0 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; }; flash@1 { - reg = < 1 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; }; flash@2 { - reg = < 2 >; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <2>; + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; }; }; diff --git a/dts/Bindings/spi/atmel,at91rm9200-spi.yaml b/dts/Bindings/spi/atmel,at91rm9200-spi.yaml index 6c57dd6c3a..58367587bf 100644 --- a/dts/Bindings/spi/atmel,at91rm9200-spi.yaml +++ b/dts/Bindings/spi/atmel,at91rm9200-spi.yaml @@ -20,6 +20,10 @@ properties: - items: - const: microchip,sam9x60-spi - const: atmel,at91rm9200-spi + - items: + - const: microchip,sam9x7-spi + - const: microchip,sam9x60-spi + - const: atmel,at91rm9200-spi reg: maxItems: 1 diff --git a/dts/Bindings/spi/brcm,bcm2835-aux-spi.txt b/dts/Bindings/spi/brcm,bcm2835-aux-spi.txt index 9887b07247..d7668f41b0 100644 --- a/dts/Bindings/spi/brcm,bcm2835-aux-spi.txt +++ b/dts/Bindings/spi/brcm,bcm2835-aux-spi.txt @@ -1,4 +1,4 @@ -Broadcom BCM2835 auxiliar SPI1/2 controller +Broadcom BCM2835 auxiliary SPI1/2 controller The BCM2835 contains two forms of SPI master controller, one known simply as SPI0, and the other known as the "Universal SPI Master"; part of the @@ -9,7 +9,7 @@ Required properties: - reg: Should contain register location and length for the spi block - interrupts: Should contain shared interrupt of the aux block - clocks: The clock feeding the SPI controller - needs to - point to the auxiliar clock driver of the bcm2835, + point to the auxiliary clock driver of the bcm2835, as this clock will enable the output gate for the specific clock. - cs-gpios: the cs-gpios (native cs is NOT supported) diff --git a/dts/Bindings/spi/brcm,bcm63xx-hsspi.yaml b/dts/Bindings/spi/brcm,bcm63xx-hsspi.yaml new file mode 100644 index 0000000000..6554978583 --- /dev/null +++ b/dts/Bindings/spi/brcm,bcm63xx-hsspi.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Broadband SoC High Speed SPI controller + +maintainers: + - William Zhang <william.zhang@broadcom.com> + - Kursad Oney <kursad.oney@broadcom.com> + - Jonas Gorski <jonas.gorski@gmail.com> + +description: | + Broadcom Broadband SoC supports High Speed SPI master controller since the + early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0 + controller was carried over to recent ARM based chips, such as BCM63138, + BCM4908 and BCM6858. The old MIPS based chip should continue to use the + brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to + use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as + defined below to match the specific chip along with ip revision info. + + This rev 1.0 controller has a limitation that can not keep the chip select line + active between the SPI transfers within the same SPI message. This can + terminate the transaction to some SPI devices prematurely. The issue can be + worked around by either the controller's prepend mode or using the dummy chip + select workaround. Driver automatically picks the suitable mode based on + transfer type so it is transparent to the user. + + The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI + controller rev 1.1 that add the capability to allow the driver to control chip + select explicitly. This solves the issue in the old controller. + +properties: + compatible: + oneOf: + - const: brcm,bcm6328-hsspi + - items: + - enum: + - brcm,bcm47622-hsspi + - brcm,bcm4908-hsspi + - brcm,bcm63138-hsspi + - brcm,bcm63146-hsspi + - brcm,bcm63148-hsspi + - brcm,bcm63158-hsspi + - brcm,bcm63178-hsspi + - brcm,bcm6846-hsspi + - brcm,bcm6856-hsspi + - brcm,bcm6858-hsspi + - brcm,bcm6878-hsspi + - const: brcm,bcmbca-hsspi-v1.0 + - items: + - enum: + - brcm,bcm4912-hsspi + - brcm,bcm6756-hsspi + - brcm,bcm6813-hsspi + - brcm,bcm6855-hsspi + - const: brcm,bcmbca-hsspi-v1.1 + + reg: + items: + - description: main registers + - description: miscellaneous control registers + minItems: 1 + + reg-names: + items: + - const: hsspi + - const: spim-ctrl + minItems: 1 + + clocks: + items: + - description: SPI master reference clock + - description: SPI master pll clock + + clock-names: + items: + - const: hsspi + - const: pll + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm6328-hsspi + - brcm,bcmbca-hsspi-v1.0 + then: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + else: + properties: + reg: + minItems: 2 + maxItems: 2 + reg-names: + minItems: 2 + maxItems: 2 + required: + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + spi@ff801000 { + compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0xff801000 0x1000>, + <0xff802610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/dts/Bindings/spi/brcm,bcm63xx-spi.yaml b/dts/Bindings/spi/brcm,bcm63xx-spi.yaml new file mode 100644 index 0000000000..fa03cdd68e --- /dev/null +++ b/dts/Bindings/spi/brcm,bcm63xx-spi.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM6348/BCM6358 SPI controller + +maintainers: + - Jonas Gorski <jonas.gorski@gmail.com> + +description: | + Broadcom "Low Speed" SPI controller found in many older MIPS based Broadband + SoCs. + + This controller has a limitation that can not keep the chip select line active + between the SPI transfers within the same SPI message. This can terminate the + transaction to some SPI devices prematurely. The issue can be worked around by + the controller's prepend mode. + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - brcm,bcm6368-spi + - brcm,bcm6362-spi + - brcm,bcm63268-spi + - const: brcm,bcm6358-spi + - enum: + - brcm,bcm6348-spi + - brcm,bcm6358-spi + + reg: + maxItems: 1 + + clocks: + items: + - description: SPI master reference clock + + clock-names: + items: + - const: spi + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + spi@10000800 { + compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi"; + reg = <0x10000800 0x70c>; + interrupts = <1>; + clocks = <&clkctl 9>; + clock-names = "spi"; + num-cs = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/dts/Bindings/spi/brcm,spi-bcm-qspi.yaml b/dts/Bindings/spi/brcm,spi-bcm-qspi.yaml index ec58739191..45975f40d9 100644 --- a/dts/Bindings/spi/brcm,spi-bcm-qspi.yaml +++ b/dts/Bindings/spi/brcm,spi-bcm-qspi.yaml @@ -12,7 +12,7 @@ maintainers: description: | The Broadcom SPI controller is a SPI master found on various SOCs, including - BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits + BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists of: MSPI : SPI master controller can read and write to a SPI slave device BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration @@ -20,7 +20,7 @@ description: | io with 3-byte and 4-byte addressing support. Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. - MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance + MSPI master can be used without BSPI. BRCMSTB SoCs have an additional instance of a MSPI master without the BSPI to use with non flash slave devices that use SPI protocol. @@ -99,98 +99,98 @@ required: examples: - | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access spi@f03e3400 { - compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi"; - reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>; - reg-names = "mspi", "bspi", "cs_reg"; - interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>; - interrupt-parent = <&gic>; - interrupt-names = "mspi_done", - "mspi_halted", - "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done", - "spi_lr_overread"; - clocks = <&hif_spi>; - #address-cells = <0x1>; - #size-cells = <0x0>; - - flash@0 { - #size-cells = <0x2>; - #address-cells = <0x2>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <0x2625a00>; - spi-cpol; - spi-cpha; - }; + compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi"; + reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>; + reg-names = "mspi", "bspi", "cs_reg"; + interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>; + interrupt-parent = <&gic>; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overread"; + clocks = <&hif_spi>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + flash@0 { + #size-cells = <0x2>; + #address-cells = <0x2>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <0x2625a00>; + spi-cpol; + spi-cpha; + }; }; - | # BRCMSTB SoC: MSPI master for any SPI device spi@f0416000 { - clocks = <&upg_fixed>; - compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi"; - reg = <0xf0416000 0x180>; - reg-names = "mspi"; - interrupts = <0x14>; - interrupt-parent = <&irq0_aon_intc>; - interrupt-names = "mspi_done"; - #address-cells = <1>; - #size-cells = <0>; + clocks = <&upg_fixed>; + compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi"; + reg = <0xf0416000 0x180>; + reg-names = "mspi"; + interrupts = <0x14>; + interrupt-parent = <&irq0_aon_intc>; + interrupt-names = "mspi_done"; + #address-cells = <1>; + #size-cells = <0>; }; - | # iProc SoC #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> spi@18027200 { - compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; - reg = <0x18027200 0x184>, - <0x18027000 0x124>, - <0x1811c408 0x004>, - <0x180273a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mspi_done", - "mspi_halted", - "spi_lr_fullness_reached", - "spi_lr_session_aborted", - "spi_lr_impatient", - "spi_lr_session_done"; - clocks = <&iprocmed>; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x18027200 0x184>, + <0x18027000 0x124>, + <0x1811c408 0x004>, + <0x180273a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done"; + clocks = <&iprocmed>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; }; - | # NS2 SoC #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> spi@66470200 { - compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; - reg = <0x66470200 0x184>, - <0x66470000 0x124>, - <0x67017408 0x004>, - <0x664703a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; - interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "spi_l1_intr"; - clocks = <&iprocmed>; - num-cs = <2>; + compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, + <0x664703a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "spi_l1_intr"; + clocks = <&iprocmed>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { #address-cells = <1>; - #size-cells = <0>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - spi-cpol; - spi-cpha; - }; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + spi-cpol; + spi-cpha; + }; }; diff --git a/dts/Bindings/spi/cdns,qspi-nor.yaml b/dts/Bindings/spi/cdns,qspi-nor.yaml index 4707294d8f..cca81f89e2 100644 --- a/dts/Bindings/spi/cdns,qspi-nor.yaml +++ b/dts/Bindings/spi/cdns,qspi-nor.yaml @@ -19,17 +19,61 @@ allOf: then: required: - power-domains + - if: + properties: + compatible: + contains: + const: starfive,jh7110-qspi + then: + properties: + resets: + minItems: 2 + maxItems: 3 + + reset-names: + minItems: 2 + maxItems: 3 + items: + enum: [ qspi, qspi-ocp, rstc_ref ] + + else: + properties: + resets: + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 + items: + enum: [ qspi, qspi-ocp ] + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-qspi + then: + properties: + cdns,fifo-depth: + enum: [ 128, 256, 1024 ] + default: 1024 + else: + properties: + cdns,fifo-depth: + enum: [ 128, 256 ] + default: 128 properties: compatible: oneOf: - items: - enum: + - amd,pensando-elba-qspi - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi - xlnx,versal-ospi-1.0 - intel,socfpga-qspi + - starfive,jh7110-qspi - const: cdns,qspi-nor - const: cdns,qspi-nor @@ -42,14 +86,22 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 3 + + clock-names: + oneOf: + - items: + - const: ref + - items: + - const: ref + - const: ahb + - const: apb cdns,fifo-depth: description: Size of the data FIFO in words. - $ref: "/schemas/types.yaml#/definitions/uint32" - enum: [ 128, 256 ] - default: 128 + $ref: /schemas/types.yaml#/definitions/uint32 cdns,fifo-width: $ref: /schemas/types.yaml#/definitions/uint32 @@ -79,13 +131,14 @@ properties: maxItems: 1 resets: - maxItems: 2 + minItems: 2 + maxItems: 3 reset-names: - minItems: 1 - maxItems: 2 + minItems: 2 + maxItems: 3 items: - enum: [ qspi, qspi-ocp ] + enum: [ qspi, qspi-ocp, rstc_ref ] required: - compatible @@ -103,21 +156,21 @@ unevaluatedProperties: false examples: - | qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - clocks = <&qspi_clk>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - resets = <&rst 0x1>, <&rst 0x2>; - reset-names = "qspi", "qspi-ocp"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - }; + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + resets = <&rst 0x1>, <&rst 0x2>; + reset-names = "qspi", "qspi-ocp"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + }; }; diff --git a/dts/Bindings/spi/cdns,xspi.yaml b/dts/Bindings/spi/cdns,xspi.yaml index b8bb8a3dbf..eb0f924681 100644 --- a/dts/Bindings/spi/cdns,xspi.yaml +++ b/dts/Bindings/spi/cdns,xspi.yaml @@ -2,8 +2,8 @@ # Copyright 2020-21 Cadence %YAML 1.2 --- -$id: "http://devicetree.org/schemas/spi/cdns,xspi.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/spi/cdns,xspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence XSPI Controller @@ -16,7 +16,7 @@ description: | read/write access to slaves such as SPI-NOR flash. allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/dts/Bindings/spi/fsl,spi-fsl-qspi.yaml b/dts/Bindings/spi/fsl,spi-fsl-qspi.yaml index e586445584..f2dd20370d 100644 --- a/dts/Bindings/spi/fsl,spi-fsl-qspi.yaml +++ b/dts/Bindings/spi/fsl,spi-fsl-qspi.yaml @@ -10,7 +10,7 @@ maintainers: - Han Xu <han.xu@nxp.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/dts/Bindings/spi/fsl-imx-cspi.yaml b/dts/Bindings/spi/fsl-imx-cspi.yaml index 12cb767110..14cac0e6e0 100644 --- a/dts/Bindings/spi/fsl-imx-cspi.yaml +++ b/dts/Bindings/spi/fsl-imx-cspi.yaml @@ -10,7 +10,7 @@ maintainers: - Shawn Guo <shawnguo@kernel.org> allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: @@ -23,6 +23,13 @@ properties: - const: fsl,imx51-ecspi - const: fsl,imx53-ecspi - items: + - enum: + - fsl,imx25-cspi + - fsl,imx50-cspi + - fsl,imx51-cspi + - fsl,imx53-cspi + - const: fsl,imx35-cspi + - items: - const: fsl,imx8mp-ecspi - const: fsl,imx6ul-ecspi - items: diff --git a/dts/Bindings/spi/loongson,ls2k-spi.yaml b/dts/Bindings/spi/loongson,ls2k-spi.yaml new file mode 100644 index 0000000000..de9d32fead --- /dev/null +++ b/dts/Bindings/spi/loongson,ls2k-spi.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/loongson,ls2k-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson SPI controller + +maintainers: + - Yinbo Zhu <zhuyinbo@loongson.cn> + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + oneOf: + - enum: + - loongson,ls2k1000-spi + - items: + - enum: + - loongson,ls2k0500-spi + - const: loongson,ls2k1000-spi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + spi0: spi@1fff0220{ + compatible = "loongson,ls2k1000-spi"; + reg = <0x1fff0220 0x10>; + clocks = <&clk 17>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/dts/Bindings/spi/mediatek,spi-mt65xx.yaml b/dts/Bindings/spi/mediatek,spi-mt65xx.yaml index 8d2a6c084e..b6249880c3 100644 --- a/dts/Bindings/spi/mediatek,spi-mt65xx.yaml +++ b/dts/Bindings/spi/mediatek,spi-mt65xx.yaml @@ -10,7 +10,7 @@ maintainers: - Leilk Liu <leilk.liu@mediatek.com> allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: diff --git a/dts/Bindings/spi/mediatek,spi-mtk-snfi.yaml b/dts/Bindings/spi/mediatek,spi-mtk-snfi.yaml index 6e6e02c917..1e5e89a693 100644 --- a/dts/Bindings/spi/mediatek,spi-mtk-snfi.yaml +++ b/dts/Bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -18,14 +18,12 @@ description: | using the accompanying ECC engine. There should be only one spi slave device following generic spi bindings. -allOf: - - $ref: /schemas/spi/spi-controller.yaml# - properties: compatible: enum: - mediatek,mt7622-snand - mediatek,mt7629-snand + - mediatek,mt7986-snand reg: items: @@ -36,19 +34,20 @@ properties: - description: NFI interrupt clocks: - items: - - description: clock used for the controller - - description: clock used for the SPI bus + minItems: 2 + maxItems: 3 clock-names: - items: - - const: nfi_clk - - const: pad_clk + minItems: 2 + maxItems: 3 nand-ecc-engine: description: device-tree node of the accompanying ECC engine. $ref: /schemas/types.yaml#/definitions/phandle + mediatek,rx-latch-latency-ns: + description: Data read latch latency, unit is nanoseconds. + required: - compatible - reg @@ -57,6 +56,43 @@ required: - clock-names - nand-ecc-engine +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + - if: + properties: + compatible: + enum: + - mediatek,mt7622-snand + - mediatek,mt7629-snand + then: + properties: + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + clock-names: + items: + - const: nfi_clk + - const: pad_clk + + - if: + properties: + compatible: + enum: + - mediatek,mt7986-snand + then: + properties: + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + - description: clock used for the AHB bus + clock-names: + items: + - const: nfi_clk + - const: pad_clk + - const: nfi_hclk + unevaluatedProperties: false examples: diff --git a/dts/Bindings/spi/mediatek,spi-slave-mt27xx.yaml b/dts/Bindings/spi/mediatek,spi-slave-mt27xx.yaml index 7977799a8e..d19c9f7397 100644 --- a/dts/Bindings/spi/mediatek,spi-slave-mt27xx.yaml +++ b/dts/Bindings/spi/mediatek,spi-slave-mt27xx.yaml @@ -10,7 +10,7 @@ maintainers: - Leilk Liu <leilk.liu@mediatek.com> allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: diff --git a/dts/Bindings/spi/microchip,mpfs-spi.yaml b/dts/Bindings/spi/microchip,mpfs-spi.yaml index 1051690e37..74a817cc7d 100644 --- a/dts/Bindings/spi/microchip,mpfs-spi.yaml +++ b/dts/Bindings/spi/microchip,mpfs-spi.yaml @@ -22,7 +22,7 @@ properties: - items: - const: microchip,mpfs-qspi - const: microchip,coreqspi-rtl-v2 - - const: microchip,coreqspi-rtl-v2 #FPGA QSPI + - const: microchip,coreqspi-rtl-v2 # FPGA QSPI - const: microchip,mpfs-spi reg: diff --git a/dts/Bindings/spi/mikrotik,rb4xx-spi.yaml b/dts/Bindings/spi/mikrotik,rb4xx-spi.yaml index 3fd0a8adfe..303f6dca89 100644 --- a/dts/Bindings/spi/mikrotik,rb4xx-spi.yaml +++ b/dts/Bindings/spi/mikrotik,rb4xx-spi.yaml @@ -11,7 +11,7 @@ maintainers: - Bert Vermeulen <bert@biot.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/dts/Bindings/spi/mxicy,mx25f0a-spi.yaml b/dts/Bindings/spi/mxicy,mx25f0a-spi.yaml index a3aa5e07c0..221fe6e2ef 100644 --- a/dts/Bindings/spi/mxicy,mx25f0a-spi.yaml +++ b/dts/Bindings/spi/mxicy,mx25f0a-spi.yaml @@ -10,7 +10,7 @@ maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/dts/Bindings/spi/mxs-spi.yaml b/dts/Bindings/spi/mxs-spi.yaml index 51f8c66432..e2512166c1 100644 --- a/dts/Bindings/spi/mxs-spi.yaml +++ b/dts/Bindings/spi/mxs-spi.yaml @@ -10,7 +10,7 @@ maintainers: - Marek Vasut <marex@denx.de> allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: diff --git a/dts/Bindings/spi/nvidia,tegra114-spi.txt b/dts/Bindings/spi/nvidia,tegra114-spi.txt deleted file mode 100644 index db8e0d71c5..0000000000 --- a/dts/Bindings/spi/nvidia,tegra114-spi.txt +++ /dev/null @@ -1,61 +0,0 @@ -NVIDIA Tegra114 SPI controller. - -Required properties: -- compatible : For Tegra114, must contain "nvidia,tegra114-spi". - Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where - <chip> is tegra124, tegra132, or tegra210. -- reg: Should contain SPI registers location and length. -- interrupts: Should contain SPI interrupts. -- clock-names : Must include the following entries: - - spi -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - spi -- dmas : Must contain an entry for each entry in clock-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx - - tx -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - -Recommended properties: -- spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt -Optional properties: -- nvidia,tx-clk-tap-delay: Delays the clock going out to the external device - with this tap value. This property is used to tune the outgoing data from - Tegra SPI master with respect to outgoing Tegra SPI master clock. - Tap values vary based on the platform design trace lengths from Tegra SPI - to corresponding slave devices. Valid tap values are from 0 thru 63. -- nvidia,rx-clk-tap-delay: Delays the clock coming in from the external device - with this tap value. This property is used to adjust the Tegra SPI master - clock with respect to the data from the SPI slave device. - Tap values vary based on the platform design trace lengths from Tegra SPI - to corresponding slave devices. Valid tap values are from 0 thru 63. - -Example: - -spi@7000d600 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; - spi-max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 44>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - <spi-client>@<bus_num> { - ... - ... - nvidia,rx-clk-tap-delay = <0>; - nvidia,tx-clk-tap-delay = <16>; - ... - }; - -}; diff --git a/dts/Bindings/spi/nvidia,tegra114-spi.yaml b/dts/Bindings/spi/nvidia,tegra114-spi.yaml new file mode 100644 index 0000000000..58222ffa53 --- /dev/null +++ b/dts/Bindings/spi/nvidia,tegra114-spi.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nvidia,tegra114-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra114 SPI controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + oneOf: + - const: nvidia,tegra114-spi + - items: + - enum: + - nvidia,tegra210-spi + - nvidia,tegra124-spi + - const: nvidia,tegra114-spi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: SPI module clock + + clock-names: + items: + - const: spi + + resets: + items: + - description: SPI module reset + + reset-names: + items: + - const: spi + + dmas: + items: + - description: DMA channel for the reception FIFO + - description: DMA channel for the transmission FIFO + + dma-names: + items: + - const: rx + - const: tx + + spi-max-frequency: + description: Maximum SPI clocking speed of the controller in Hz. + $ref: /schemas/types.yaml#/definitions/uint32 + +allOf: + - $ref: spi-controller.yaml + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - dmas + - dma-names + +examples: + - | + spi@7000d600 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + clocks = <&tegra_car 44>; + clock-names = "spi"; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + + spi-max-frequency = <25000000>; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + nvidia,rx-clk-tap-delay = <0>; + nvidia,tx-clk-tap-delay = <16>; + }; + }; diff --git a/dts/Bindings/spi/nvidia,tegra20-sflash.txt b/dts/Bindings/spi/nvidia,tegra20-sflash.txt deleted file mode 100644 index c212491929..0000000000 --- a/dts/Bindings/spi/nvidia,tegra20-sflash.txt +++ /dev/null @@ -1,37 +0,0 @@ -NVIDIA Tegra20 SFLASH controller. - -Required properties: -- compatible : should be "nvidia,tegra20-sflash". -- reg: Should contain SFLASH registers location and length. -- interrupts: Should contain SFLASH interrupts. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - spi -- dmas : Must contain an entry for each entry in clock-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx - - tx - -Recommended properties: -- spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - -spi@7000c380 { - compatible = "nvidia,tegra20-sflash"; - reg = <0x7000c380 0x80>; - interrupts = <0 39 0x04>; - spi-max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 43>; - resets = <&tegra_car 43>; - reset-names = "spi"; - dmas = <&apbdma 11>, <&apbdma 11>; - dma-names = "rx", "tx"; -}; diff --git a/dts/Bindings/spi/nvidia,tegra20-sflash.yaml b/dts/Bindings/spi/nvidia,tegra20-sflash.yaml new file mode 100644 index 0000000000..e245bad85a --- /dev/null +++ b/dts/Bindings/spi/nvidia,tegra20-sflash.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nvidia,tegra20-sflash.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 SFLASH controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra20-sflash + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: module clock + + resets: + items: + - description: module reset + + reset-names: + items: + - const: spi + + dmas: + items: + - description: DMA channel used for reception + - description: DMA channel used for transmission + + dma-names: + items: + - const: rx + - const: tx + + spi-max-frequency: + description: Maximum SPI clocking speed of the controller in Hz. + $ref: /schemas/types.yaml#/definitions/uint32 + +allOf: + - $ref: spi-controller.yaml + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - reset-names + - dmas + - dma-names + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + spi@7000c380 { + compatible = "nvidia,tegra20-sflash"; + reg = <0x7000c380 0x80>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SPI>; + resets = <&tegra_car 43>; + reset-names = "spi"; + dmas = <&apbdma 11>, <&apbdma 11>; + dma-names = "rx", "tx"; + }; diff --git a/dts/Bindings/spi/nvidia,tegra20-slink.txt b/dts/Bindings/spi/nvidia,tegra20-slink.txt deleted file mode 100644 index 40d80b93e3..0000000000 --- a/dts/Bindings/spi/nvidia,tegra20-slink.txt +++ /dev/null @@ -1,37 +0,0 @@ -NVIDIA Tegra20/Tegra30 SLINK controller. - -Required properties: -- compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink". -- reg: Should contain SLINK registers location and length. -- interrupts: Should contain SLINK interrupts. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - spi -- dmas : Must contain an entry for each entry in clock-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx - - tx - -Recommended properties: -- spi-max-frequency: Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - -spi@7000d600 { - compatible = "nvidia,tegra20-slink"; - reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; - spi-max-frequency = <25000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 44>; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; -}; diff --git a/dts/Bindings/spi/nvidia,tegra20-slink.yaml b/dts/Bindings/spi/nvidia,tegra20-slink.yaml new file mode 100644 index 0000000000..291c25ec01 --- /dev/null +++ b/dts/Bindings/spi/nvidia,tegra20-slink.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nvidia,tegra20-slink.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20/30 SLINK controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + enum: + - nvidia,tegra20-slink + - nvidia,tegra30-slink + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: module clock + + resets: + items: + - description: module reset + + reset-names: + items: + - const: spi + + dmas: + items: + - description: DMA channel used for reception + - description: DMA channel used for transmission + + dma-names: + items: + - const: rx + - const: tx + + operating-points-v2: + $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + items: + - description: phandle to the core power domain + + spi-max-frequency: + description: Maximum SPI clocking speed of the controller in Hz. + $ref: /schemas/types.yaml#/definitions/uint32 + +allOf: + - $ref: spi-controller.yaml + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - reset-names + - dmas + - dma-names + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + spi@7000d600 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d600 0x200>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + }; diff --git a/dts/Bindings/spi/nvidia,tegra210-quad.yaml b/dts/Bindings/spi/nvidia,tegra210-quad.yaml index 899100e783..48e97e2402 100644 --- a/dts/Bindings/spi/nvidia,tegra210-quad.yaml +++ b/dts/Bindings/spi/nvidia,tegra210-quad.yaml @@ -11,7 +11,7 @@ maintainers: - Jonathan Hunter <jonathanh@nvidia.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: @@ -50,6 +50,7 @@ properties: patternProperties: "@[0-9a-f]+$": type: object + additionalProperties: true properties: spi-rx-bus-width: @@ -74,25 +75,25 @@ examples: #include <dt-bindings/reset/tegra210-car.h> #include <dt-bindings/interrupt-controller/arm-gic.h> spi@70410000 { - compatible = "nvidia,tegra210-qspi"; - reg = <0x70410000 0x1000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_QSPI>, - <&tegra_car TEGRA210_CLK_QSPI_PM>; - clock-names = "qspi", "qspi_out"; - resets = <&tegra_car 211>; - dmas = <&apbdma 5>, <&apbdma 5>; - dma-names = "rx", "tx"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - nvidia,tx-clk-tap-delay = <0>; - nvidia,rx-clk-tap-delay = <0>; - }; + compatible = "nvidia,tegra210-qspi"; + reg = <0x70410000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_QSPI>, + <&tegra_car TEGRA210_CLK_QSPI_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&tegra_car 211>; + dmas = <&apbdma 5>, <&apbdma 5>; + dma-names = "rx", "tx"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + nvidia,tx-clk-tap-delay = <0>; + nvidia,rx-clk-tap-delay = <0>; + }; }; diff --git a/dts/Bindings/spi/omap-spi.yaml b/dts/Bindings/spi/omap-spi.yaml index 352affa4b7..ff4d361707 100644 --- a/dts/Bindings/spi/omap-spi.yaml +++ b/dts/Bindings/spi/omap-spi.yaml @@ -68,7 +68,7 @@ properties: dma-names: description: List of DMA request names. These strings correspond 1:1 with - the DMA sepecifiers listed in dmas. The string names is to be + the DMA specifiers listed in dmas. The string names is to be "rxN" and "txN" for RX and TX requests, respectively. Where N is the chip select number. minItems: 1 diff --git a/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml b/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml index b622bb7363..1696ac46a6 100644 --- a/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml +++ b/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml @@ -1,9 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- -$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Quad Serial Peripheral Interface (QSPI) @@ -30,6 +29,9 @@ properties: reg: maxItems: 1 + iommus: + maxItems: 1 + interrupts: maxItems: 1 @@ -53,6 +55,11 @@ properties: - const: qspi-config - const: qspi-memory + operating-points-v2: true + + power-domains: + maxItems: 1 + required: - compatible - reg @@ -88,7 +95,6 @@ examples: spi-tx-bus-width = <2>; spi-rx-bus-width = <2>; }; - }; }; ... diff --git a/dts/Bindings/spi/qcom,spi-qup.yaml b/dts/Bindings/spi/qcom,spi-qup.yaml index 93f14dd01a..88be132689 100644 --- a/dts/Bindings/spi/qcom,spi-qup.yaml +++ b/dts/Bindings/spi/qcom,spi-qup.yaml @@ -44,9 +44,17 @@ properties: - const: tx - const: rx + interconnects: + maxItems: 1 + interrupts: maxItems: 1 + operating-points-v2: true + + power-domains: + maxItems: 1 + reg: maxItems: 1 @@ -62,7 +70,9 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,gcc-msm8996.h> + #include <dt-bindings/interconnect/qcom,msm8996.h> #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> spi@7575000 { compatible = "qcom,spi-qup-v2.2.1"; @@ -76,6 +86,9 @@ examples: pinctrl-1 = <&blsp1_spi1_sleep>; dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; dma-names = "tx", "rx"; + power-domains = <&rpmpd MSM8996_VDDCX>; + operating-points-v2 = <&spi_opp_table>; + interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; #address-cells = <1>; #size-cells = <0>; }; diff --git a/dts/Bindings/spi/realtek,rtl-spi.yaml b/dts/Bindings/spi/realtek,rtl-spi.yaml index 2f938c293f..70330d945a 100644 --- a/dts/Bindings/spi/realtek,rtl-spi.yaml +++ b/dts/Bindings/spi/realtek,rtl-spi.yaml @@ -11,7 +11,7 @@ maintainers: - Birger Koblitz <mail@birger-koblitz.de> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/dts/Bindings/spi/renesas,rspi.yaml b/dts/Bindings/spi/renesas,rspi.yaml index f45d3b75d6..0ef3f84219 100644 --- a/dts/Bindings/spi/renesas,rspi.yaml +++ b/dts/Bindings/spi/renesas,rspi.yaml @@ -21,7 +21,7 @@ properties: - enum: - renesas,rspi-r7s72100 # RZ/A1H - renesas,rspi-r7s9210 # RZ/A2 - - renesas,r9a07g043-rspi # RZ/G2UL + - renesas,r9a07g043-rspi # RZ/G2UL and RZ/Five - renesas,r9a07g044-rspi # RZ/G2{L,LC} - renesas,r9a07g054-rspi # RZ/V2L - const: renesas,rspi-rz @@ -141,15 +141,15 @@ examples: #include <dt-bindings/power/r8a7791-sysc.h> qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7791", "renesas,qspi"; - reg = <0xe6b10000 0x2c>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; + compatible = "renesas,qspi-r8a7791", "renesas,qspi"; + reg = <0xe6b10000 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; }; diff --git a/dts/Bindings/spi/renesas,rzv2m-csi.yaml b/dts/Bindings/spi/renesas,rzv2m-csi.yaml new file mode 100644 index 0000000000..bed829837d --- /dev/null +++ b/dts/Bindings/spi/renesas,rzv2m-csi.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M Clocked Serial Interface (CSI) + +maintainers: + - Fabrizio Castro <fabrizio.castro.jz@renesas.com> + - Geert Uytterhoeven <geert+renesas@glider.be> + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: renesas,rzv2m-csi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The clock used to generate the output clock (CSICLK) + - description: Internal clock to access the registers (PCLK) + + clock-names: + items: + - const: csiclk + - const: pclk + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + renesas,csi-no-ss: + type: boolean + description: + The CSI Slave Selection (SS) pin won't be used to enable transmission and + reception. Only available when in target mode. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - power-domains + - '#address-cells' + - '#size-cells' + +dependencies: + renesas,csi-no-ss: [ spi-slave ] + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/r9a09g011-cpg.h> + csi4: spi@a4020200 { + compatible = "renesas,rzv2m-csi"; + reg = <0xa4020200 0x80>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>, + <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>; + clock-names = "csiclk", "pclk"; + resets = <&cpg R9A09G011_CSI_GPH_PRESETN>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/dts/Bindings/spi/renesas,sh-msiof.yaml b/dts/Bindings/spi/renesas,sh-msiof.yaml index 491a695a2d..00acbbb0f6 100644 --- a/dts/Bindings/spi/renesas,sh-msiof.yaml +++ b/dts/Bindings/spi/renesas,sh-msiof.yaml @@ -149,23 +149,38 @@ required: - compatible - reg - interrupts + - clocks + - power-domains - '#address-cells' - '#size-cells' +if: + not: + properties: + compatible: + contains: + const: renesas,sh-mobile-msiof +then: + required: + - resets + unevaluatedProperties: false examples: - | - #include <dt-bindings/clock/r8a7791-clock.h> - #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/r8a7791-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7791-sysc.h> msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof"; reg = <0xe6e20000 0x0064>; - interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 000>; dmas = <&dmac0 0x51>, <&dmac0 0x52>; dma-names = "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 0>; #address-cells = <1>; #size-cells = <0>; }; diff --git a/dts/Bindings/spi/rockchip-sfc.yaml b/dts/Bindings/spi/rockchip-sfc.yaml index 339fb39529..ac1503de04 100644 --- a/dts/Bindings/spi/rockchip-sfc.yaml +++ b/dts/Bindings/spi/rockchip-sfc.yaml @@ -47,6 +47,8 @@ properties: patternProperties: "^flash@[0-3]$": type: object + additionalProperties: true + properties: reg: minimum: 0 diff --git a/dts/Bindings/spi/samsung,spi.yaml b/dts/Bindings/spi/samsung,spi.yaml index e0a465d70b..79da99ca0e 100644 --- a/dts/Bindings/spi/samsung,spi.yaml +++ b/dts/Bindings/spi/samsung,spi.yaml @@ -35,8 +35,6 @@ properties: minItems: 2 maxItems: 3 - cs-gpios: true - dmas: minItems: 2 maxItems: 2 diff --git a/dts/Bindings/spi/snps,dw-apb-ssi.yaml b/dts/Bindings/spi/snps,dw-apb-ssi.yaml index d33b72fabc..fde3776a55 100644 --- a/dts/Bindings/spi/snps,dw-apb-ssi.yaml +++ b/dts/Bindings/spi/snps,dw-apb-ssi.yaml @@ -10,7 +10,7 @@ maintainers: - Mark Brown <broonie@kernel.org> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# - if: properties: compatible: @@ -37,6 +37,17 @@ allOf: else: required: - interrupts + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-spi + then: + required: + - amd,pensando-elba-syscon + else: + properties: + amd,pensando-elba-syscon: false properties: compatible: @@ -61,8 +72,10 @@ properties: - const: snps,dw-apb-ssi - description: Intel Keem Bay SPI Controller const: intel,keembay-ssi - - description: Intel Thunder Bay SPI Controller - const: intel,thunderbay-ssi + - description: Intel Mount Evans Integrated Management Complex SPI Controller + const: intel,mountevans-imc-ssi + - description: AMD Pensando Elba SoC SPI Controller + const: amd,pensando-elba-spi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller @@ -136,9 +149,17 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration. + amd,pensando-elba-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Block address to control SPI chip-selects. The Elba SoC system controller + provides an interface to override the native DWC SSI CS control. + patternProperties: "^.*@[0-9a-f]+$": type: object + additionalProperties: true + properties: reg: minimum: 0 diff --git a/dts/Bindings/spi/socionext,uniphier-spi.yaml b/dts/Bindings/spi/socionext,uniphier-spi.yaml index 597fc4e6b0..c96131ebbe 100644 --- a/dts/Bindings/spi/socionext,uniphier-spi.yaml +++ b/dts/Bindings/spi/socionext,uniphier-spi.yaml @@ -17,9 +17,6 @@ allOf: - $ref: spi-controller.yaml# properties: - "#address-cells": true - "#size-cells": true - compatible: const: socionext,uniphier-scssi diff --git a/dts/Bindings/spi/spi-bcm63xx-hsspi.txt b/dts/Bindings/spi/spi-bcm63xx-hsspi.txt deleted file mode 100644 index 37b29ee138..0000000000 --- a/dts/Bindings/spi/spi-bcm63xx-hsspi.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for Broadcom BCM6328 High Speed SPI controller - -Required properties: -- compatible: must contain of "brcm,bcm6328-hsspi". -- reg: Base address and size of the controllers memory area. -- interrupts: Interrupt for the SPI block. -- clocks: phandles of the SPI clock and the PLL clock. -- clock-names: must be "hsspi", "pll". -- #address-cells: <1>, as required by generic SPI binding. -- #size-cells: <0>, also as required by generic SPI binding. - -Optional properties: -- num-cs: some controllers have less than 8 cs signals. Defaults to 8 - if absent. - -Child nodes as per the generic SPI binding. - -Example: - - spi@10001000 { - compatible = "brcm,bcm6328-hsspi"; - reg = <0x10001000 0x600>; - - interrupts = <29>; - - clocks = <&clkctl 9>, <&hsspi_pll>; - clock-names = "hsspi", "pll"; - - num-cs = <2>; - - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/dts/Bindings/spi/spi-bcm63xx.txt b/dts/Bindings/spi/spi-bcm63xx.txt deleted file mode 100644 index 1c16f66926..0000000000 --- a/dts/Bindings/spi/spi-bcm63xx.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for Broadcom BCM6348/BCM6358 SPI controller - -Required properties: -- compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi". -- reg: Base address and size of the controllers memory area. -- interrupts: Interrupt for the SPI block. -- clocks: phandle of the SPI clock. -- clock-names: has to be "spi". -- #address-cells: <1>, as required by generic SPI binding. -- #size-cells: <0>, also as required by generic SPI binding. - -Optional properties: -- num-cs: some controllers have less than 8 cs signals. Defaults to 8 - if absent. - -Child nodes as per the generic SPI binding. - -Example: - - spi@10000800 { - compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi"; - reg = <0x10000800 0x70c>; - - interrupts = <1>; - - clocks = <&clkctl 9>; - clock-names = "spi"; - - num-cs = <5>; - - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/dts/Bindings/spi/spi-cadence.yaml b/dts/Bindings/spi/spi-cadence.yaml index 64bf4e6211..d4b61b0e83 100644 --- a/dts/Bindings/spi/spi-cadence.yaml +++ b/dts/Bindings/spi/spi-cadence.yaml @@ -7,10 +7,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence SPI controller maintainers: - - Michal Simek <michal.simek@xilinx.com> + - Michal Simek <michal.simek@amd.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: @@ -49,6 +49,12 @@ properties: enum: [ 0, 1 ] default: 0 + power-domains: + maxItems: 1 + + label: + description: Descriptive name of the SPI controller. + required: - compatible - reg diff --git a/dts/Bindings/spi/spi-controller.yaml b/dts/Bindings/spi/spi-controller.yaml index 5a7c72cadf..524f6fe8c2 100644 --- a/dts/Bindings/spi/spi-controller.yaml +++ b/dts/Bindings/spi/spi-controller.yaml @@ -17,7 +17,7 @@ description: | properties: $nodename: - pattern: "^spi(@.*|-[0-9a-f])*$" + pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$" "#address-cells": enum: [0, 1] @@ -94,6 +94,7 @@ patternProperties: "^.*@[0-9a-f]+$": type: object $ref: spi-peripheral-props.yaml + additionalProperties: true properties: spi-3wire: diff --git a/dts/Bindings/spi/spi-fsl-lpspi.yaml b/dts/Bindings/spi/spi-fsl-lpspi.yaml index 94caa2b7e2..727c5346b8 100644 --- a/dts/Bindings/spi/spi-fsl-lpspi.yaml +++ b/dts/Bindings/spi/spi-fsl-lpspi.yaml @@ -10,7 +10,7 @@ maintainers: - Anson Huang <Anson.Huang@nxp.com> allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: @@ -63,6 +63,9 @@ properties: maximum: 2 default: 1 + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/spi/spi-gpio.yaml b/dts/Bindings/spi/spi-gpio.yaml index f29b89076c..9ce1df93d4 100644 --- a/dts/Bindings/spi/spi-gpio.yaml +++ b/dts/Bindings/spi/spi-gpio.yaml @@ -14,7 +14,7 @@ description: dedicated GPIO lines. allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: @@ -41,7 +41,7 @@ properties: num-chipselects: description: Number of chipselect lines. Should be <0> if a single device with no chip select is connected. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 # Deprecated properties gpio-sck: false diff --git a/dts/Bindings/spi/spi-mux.yaml b/dts/Bindings/spi/spi-mux.yaml index 7ea79f6d33..fb2a603992 100644 --- a/dts/Bindings/spi/spi-mux.yaml +++ b/dts/Bindings/spi/spi-mux.yaml @@ -30,8 +30,8 @@ description: | +------------+ allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" - - $ref: "/schemas/spi/spi-peripheral-props.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# maintainers: - Chris Packham <chris.packham@alliedtelesis.co.nz> diff --git a/dts/Bindings/spi/spi-nxp-fspi.yaml b/dts/Bindings/spi/spi-nxp-fspi.yaml index 1b552c2982..7fd5911454 100644 --- a/dts/Bindings/spi/spi-nxp-fspi.yaml +++ b/dts/Bindings/spi/spi-nxp-fspi.yaml @@ -11,7 +11,7 @@ maintainers: - Kuldeep Singh <singh.kuldeep87k@gmail.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: @@ -45,6 +45,9 @@ properties: - const: fspi_en - const: fspi + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/spi/spi-peripheral-props.yaml b/dts/Bindings/spi/spi-peripheral-props.yaml index 9a60c0664b..15938f81fd 100644 --- a/dts/Bindings/spi/spi-peripheral-props.yaml +++ b/dts/Bindings/spi/spi-peripheral-props.yaml @@ -49,6 +49,16 @@ properties: Delay in nanoseconds to be introduced by the controller after CS is asserted. + spi-cs-hold-delay-ns: + description: + Delay in nanoseconds to be introduced by the controller before CS is + de-asserted. + + spi-cs-inactive-delay-ns: + description: + Delay in nanoseconds to be introduced by the controller after CS is + de-asserted. + spi-rx-bus-width: description: Bus width to the SPI bus used for read transfers. @@ -103,8 +113,14 @@ properties: minItems: 2 maxItems: 4 + st,spi-midi-ns: + description: | + Only for STM32H7, (Master Inter-Data Idleness) minimum time + delay in nanoseconds inserted between two consecutive data frames. + # The controller specific properties go here. allOf: + - $ref: arm,pl022-peripheral-props.yaml# - $ref: cdns,qspi-nor-peripheral-props.yaml# - $ref: samsung,spi-peripheral-props.yaml# - $ref: nvidia,tegra210-quad-peripheral-props.yaml# diff --git a/dts/Bindings/spi/spi-pl022.yaml b/dts/Bindings/spi/spi-pl022.yaml index 0e382119c6..7f174b7d0a 100644 --- a/dts/Bindings/spi/spi-pl022.yaml +++ b/dts/Bindings/spi/spi-pl022.yaml @@ -10,7 +10,8 @@ maintainers: - Linus Walleij <linus.walleij@linaro.org> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# + - $ref: /schemas/arm/primecell.yaml# # We need a select here so we don't match all nodes with 'arm,primecell' select: @@ -45,7 +46,7 @@ properties: description: delay in ms following transfer completion before the runtime power management system suspends the device. A setting of 0 indicates no delay and the device will be suspended immediately. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 pl022,rt: description: indicates the controller should run the message pump with realtime @@ -73,57 +74,6 @@ properties: resets: maxItems: 1 -patternProperties: - "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$": - type: object - # SPI slave nodes must be children of the SPI master node and can - # contain the following properties. - properties: - pl022,interface: - description: SPI interface type - $ref: "/schemas/types.yaml#/definitions/uint32" - enum: - - 0 # SPI - - 1 # Texas Instruments Synchronous Serial Frame Format - - 2 # Microwire (Half Duplex) - - pl022,com-mode: - description: Specifies the transfer mode - $ref: "/schemas/types.yaml#/definitions/uint32" - enum: - - 0 # interrupt mode - - 1 # polling mode - - 2 # DMA mode - default: 1 - - pl022,rx-level-trig: - description: Rx FIFO watermark level - $ref: "/schemas/types.yaml#/definitions/uint32" - minimum: 0 - maximum: 4 - - pl022,tx-level-trig: - description: Tx FIFO watermark level - $ref: "/schemas/types.yaml#/definitions/uint32" - minimum: 0 - maximum: 4 - - pl022,ctrl-len: - description: Microwire interface - Control length - $ref: "/schemas/types.yaml#/definitions/uint32" - minimum: 0x03 - maximum: 0x1f - - pl022,wait-state: - description: Microwire interface - Wait state - $ref: "/schemas/types.yaml#/definitions/uint32" - enum: [0, 1] - - pl022,duplex: - description: Microwire interface - Full/Half duplex - $ref: "/schemas/types.yaml#/definitions/uint32" - enum: [0, 1] - required: - compatible - reg diff --git a/dts/Bindings/spi/spi-rockchip.yaml b/dts/Bindings/spi/spi-rockchip.yaml index 66e49947b7..e4941e9212 100644 --- a/dts/Bindings/spi/spi-rockchip.yaml +++ b/dts/Bindings/spi/spi-rockchip.yaml @@ -11,7 +11,7 @@ description: as flash and display controllers using the SPI communication interface. allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# maintainers: - Heiko Stuebner <heiko@sntech.de> diff --git a/dts/Bindings/spi/spi-sifive.yaml b/dts/Bindings/spi/spi-sifive.yaml index 6e7e394fc1..5bffefb9c7 100644 --- a/dts/Bindings/spi/spi-sifive.yaml +++ b/dts/Bindings/spi/spi-sifive.yaml @@ -12,7 +12,7 @@ maintainers: - Palmer Dabbelt <palmer@sifive.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: @@ -51,14 +51,14 @@ properties: sifive,fifo-depth: description: Depth of hardware queues; defaults to 8 - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 enum: [8] default: 8 sifive,max-bits-per-word: description: Maximum bits per word; defaults to 8 - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8] default: 8 diff --git a/dts/Bindings/spi/spi-st-ssc.txt b/dts/Bindings/spi/spi-st-ssc.txt deleted file mode 100644 index 1bdc4709e4..0000000000 --- a/dts/Bindings/spi/spi-st-ssc.txt +++ /dev/null @@ -1,40 +0,0 @@ -STMicroelectronics SSC (SPI) Controller ---------------------------------------- - -Required properties: -- compatible : "st,comms-ssc4-spi" -- reg : Offset and length of the device's register set -- interrupts : The interrupt specifier -- clock-names : Must contain "ssc" -- clocks : Must contain an entry for each name in clock-names - See ../clk/* -- pinctrl-names : Uses "default", can use "sleep" if provided - See ../pinctrl/pinctrl-bindings.txt - -Optional properties: -- cs-gpios : List of GPIO chip selects - See ../spi/spi-bus.txt - -Child nodes represent devices on the SPI bus - See ../spi/spi-bus.txt - -Example: - spi@9840000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9840000 0x110>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-0 = <&pinctrl_spi0_default>; - pinctrl-names = "default"; - cs-gpios = <&pio17 5 0>; - #address-cells = <1>; - #size-cells = <0>; - - st95hf@0{ - compatible = "st,st95hf"; - reg = <0>; - spi-max-frequency = <1000000>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - }; diff --git a/dts/Bindings/spi/spi-sunplus-sp7021.yaml b/dts/Bindings/spi/spi-sunplus-sp7021.yaml index 3a58cf0f1e..edb5ba71af 100644 --- a/dts/Bindings/spi/spi-sunplus-sp7021.yaml +++ b/dts/Bindings/spi/spi-sunplus-sp7021.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sunplus sp7021 SPI controller allOf: - - $ref: "spi-controller.yaml" + - $ref: spi-controller.yaml maintainers: - Li-hao Kuo <lhjeff911@gmail.com> @@ -59,9 +59,9 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/irq.h> - spi@9C002D80 { + spi@9c002d80 { compatible = "sunplus,sp7021-spi"; - reg = <0x9C002D80 0x80>, <0x9C002E00 0x80>; + reg = <0x9c002d80 0x80>, <0x9c002e00 0x80>; reg-names = "master", "slave"; interrupt-parent = <&intc>; interrupt-names = "dma_w", diff --git a/dts/Bindings/spi/spi-xilinx.yaml b/dts/Bindings/spi/spi-xilinx.yaml index bbb735603f..4beb3af041 100644 --- a/dts/Bindings/spi/spi-xilinx.yaml +++ b/dts/Bindings/spi/spi-xilinx.yaml @@ -7,10 +7,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx SPI controller maintainers: - - Michal Simek <michal.simek@xilinx.com> + - Michal Simek <michal.simek@amd.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/dts/Bindings/spi/spi-zynqmp-qspi.yaml b/dts/Bindings/spi/spi-zynqmp-qspi.yaml index 546c416cdb..e5199b109d 100644 --- a/dts/Bindings/spi/spi-zynqmp-qspi.yaml +++ b/dts/Bindings/spi/spi-zynqmp-qspi.yaml @@ -7,10 +7,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller maintainers: - - Michal Simek <michal.simek@xilinx.com> + - Michal Simek <michal.simek@amd.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: @@ -32,6 +32,12 @@ properties: clocks: maxItems: 2 + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/spi/sprd,spi-adi.yaml b/dts/Bindings/spi/sprd,spi-adi.yaml index a3ab1a1f1e..903b06f88b 100644 --- a/dts/Bindings/spi/sprd,spi-adi.yaml +++ b/dts/Bindings/spi/sprd,spi-adi.yaml @@ -1,9 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- -$id: "http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Spreadtrum ADI controller diff --git a/dts/Bindings/spi/st,ssc-spi.yaml b/dts/Bindings/spi/st,ssc-spi.yaml new file mode 100644 index 0000000000..6a77cd3f5d --- /dev/null +++ b/dts/Bindings/spi/st,ssc-spi.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/st,ssc-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics SSC SPI Controller + +description: | + The STMicroelectronics SSC SPI controller can be found on STi platforms + and it used to communicate with external devices using the + Serial Peripheral Interface. + +maintainers: + - Patrice Chotard <patrice.chotard@foss.st.com> + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: st,comms-ssc4-spi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: ssc + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stih407-clks.h> + spi@9840000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9840000 0x110>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + pinctrl-0 = <&pinctrl_spi0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + }; + +... diff --git a/dts/Bindings/spi/st,stm32-qspi.yaml b/dts/Bindings/spi/st,stm32-qspi.yaml index 1eb17f7a4d..8bba965a9a 100644 --- a/dts/Bindings/spi/st,stm32-qspi.yaml +++ b/dts/Bindings/spi/st,stm32-qspi.yaml @@ -11,7 +11,7 @@ maintainers: - Patrice Chotard <patrice.chotard@foss.st.com> allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# properties: compatible: diff --git a/dts/Bindings/spi/st,stm32-spi.yaml b/dts/Bindings/spi/st,stm32-spi.yaml index 1cda15f91c..4bd9aeb812 100644 --- a/dts/Bindings/spi/st,stm32-spi.yaml +++ b/dts/Bindings/spi/st,stm32-spi.yaml @@ -17,22 +17,15 @@ maintainers: - Fabrice Gasnier <fabrice.gasnier@foss.st.com> allOf: - - $ref: "spi-controller.yaml#" - - if: - properties: - compatible: - contains: - const: st,stm32f4-spi - - then: - properties: - st,spi-midi-ns: false + - $ref: spi-controller.yaml# properties: compatible: enum: - st,stm32f4-spi + - st,stm32f7-spi - st,stm32h7-spi + - st,stm32mp25-spi reg: maxItems: 1 @@ -59,17 +52,6 @@ properties: - const: rx - const: tx -patternProperties: - "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$": - type: object - # SPI slave nodes must be children of the SPI master node and can - # contain the following properties. - properties: - st,spi-midi-ns: - description: | - Only for STM32H7, (Master Inter-Data Idleness) minimum time - delay in nanoseconds inserted between two consecutive data frames. - required: - compatible - reg @@ -84,18 +66,17 @@ examples: #include <dt-bindings/clock/stm32mp1-clks.h> #include <dt-bindings/reset/stm32mp1-resets.h> spi@4000b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000b000 0x400>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI2_K>; - resets = <&rcc SPI2_R>; - dmas = <&dmamux1 0 39 0x400 0x05>, - <&dmamux1 1 40 0x400 0x05>; - dma-names = "rx", "tx"; - cs-gpios = <&gpioa 11 0>; - + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + dmas = <&dmamux1 0 39 0x400 0x05>, + <&dmamux1 1 40 0x400 0x05>; + dma-names = "rx", "tx"; + cs-gpios = <&gpioa 11 0>; }; ... diff --git a/dts/Bindings/spi/xlnx,zynq-qspi.yaml b/dts/Bindings/spi/xlnx,zynq-qspi.yaml index 1f1c40a9f3..7ea8fb42ce 100644 --- a/dts/Bindings/spi/xlnx,zynq-qspi.yaml +++ b/dts/Bindings/spi/xlnx,zynq-qspi.yaml @@ -11,10 +11,10 @@ description: memory devices. allOf: - - $ref: "spi-controller.yaml#" + - $ref: spi-controller.yaml# maintainers: - - Michal Simek <michal.simek@xilinx.com> + - Michal Simek <michal.simek@amd.com> # Everything else is described in the common file properties: |