diff options
Diffstat (limited to 'dts/Bindings/spi')
| -rw-r--r-- | dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 | ||||
| -rw-r--r-- | dts/Bindings/spi/amlogic,meson-gx-spicc.yaml | 1 | ||||
| -rw-r--r-- | dts/Bindings/spi/amlogic,meson6-spifc.yaml | 1 | ||||
| -rw-r--r-- | dts/Bindings/spi/aspeed,ast2600-fmc.yaml | 82 | ||||
| -rw-r--r-- | dts/Bindings/spi/ingenic,spi.yaml | 3 | ||||
| -rw-r--r-- | dts/Bindings/spi/mediatek,spi-mt65xx.yaml | 4 | ||||
| -rw-r--r-- | dts/Bindings/spi/mediatek,spi-mtk-snfi.yaml | 88 | ||||
| -rw-r--r-- | dts/Bindings/spi/qcom,spi-geni-qcom.txt | 39 | ||||
| -rw-r--r-- | dts/Bindings/spi/qcom,spi-geni-qcom.yaml | 116 | ||||
| -rw-r--r-- | dts/Bindings/spi/qcom,spi-qcom-qspi.yaml | 4 | ||||
| -rw-r--r-- | dts/Bindings/spi/qcom,spi-qup.txt | 103 | ||||
| -rw-r--r-- | dts/Bindings/spi/qcom,spi-qup.yaml | 81 | ||||
| -rw-r--r-- | dts/Bindings/spi/renesas,hspi.yaml | 1 | ||||
| -rw-r--r-- | dts/Bindings/spi/renesas,rspi.yaml | 2 | ||||
| -rw-r--r-- | dts/Bindings/spi/spi-davinci.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/spi/spi-pl022.yaml | 2 |
16 files changed, 381 insertions, 149 deletions
diff --git a/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml b/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml index 908248260a..ca4c95345a 100644 --- a/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -26,6 +26,7 @@ properties: - allwinner,sun8i-r40-spi - allwinner,sun50i-h6-spi - allwinner,sun50i-h616-spi + - allwinner,suniv-f1c100s-spi - const: allwinner,sun8i-h3-spi reg: diff --git a/dts/Bindings/spi/amlogic,meson-gx-spicc.yaml b/dts/Bindings/spi/amlogic,meson-gx-spicc.yaml index 4d46c49ec3..50de0da42c 100644 --- a/dts/Bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/dts/Bindings/spi/amlogic,meson-gx-spicc.yaml @@ -95,4 +95,3 @@ examples: reg = <0>; }; }; - diff --git a/dts/Bindings/spi/amlogic,meson6-spifc.yaml b/dts/Bindings/spi/amlogic,meson6-spifc.yaml index 54b6f15eca..8a9d526d06 100644 --- a/dts/Bindings/spi/amlogic,meson6-spifc.yaml +++ b/dts/Bindings/spi/amlogic,meson6-spifc.yaml @@ -52,4 +52,3 @@ examples: spi-max-frequency = <40000000>; }; }; - diff --git a/dts/Bindings/spi/aspeed,ast2600-fmc.yaml b/dts/Bindings/spi/aspeed,ast2600-fmc.yaml new file mode 100644 index 0000000000..fa8f4ac209 --- /dev/null +++ b/dts/Bindings/spi/aspeed,ast2600-fmc.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed SMC controllers bindings + +maintainers: + - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> + - Cédric Le Goater <clg@kaod.org> + +description: | + This binding describes the Aspeed Static Memory Controllers (FMC and + SPI) of the AST2400, AST2500 and AST2600 SOCs. + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + enum: + - aspeed,ast2600-fmc + - aspeed,ast2600-spi + - aspeed,ast2500-fmc + - aspeed,ast2500-spi + - aspeed,ast2400-fmc + - aspeed,ast2400-spi + + reg: + items: + - description: registers + - description: memory mapping + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> + #include <dt-bindings/clock/ast2600-clock.h> + + spi@1e620000 { + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-fmc"; + clocks = <&syscon ASPEED_CLK_AHB>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + }; + + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + }; + + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; + }; + }; diff --git a/dts/Bindings/spi/ingenic,spi.yaml b/dts/Bindings/spi/ingenic,spi.yaml index 5b1c7a2a6a..360f76c226 100644 --- a/dts/Bindings/spi/ingenic,spi.yaml +++ b/dts/Bindings/spi/ingenic,spi.yaml @@ -18,7 +18,10 @@ properties: oneOf: - enum: - ingenic,jz4750-spi + - ingenic,jz4775-spi - ingenic,jz4780-spi + - ingenic,x1000-spi + - ingenic,x2000-spi - items: - enum: - ingenic,jz4760-spi diff --git a/dts/Bindings/spi/mediatek,spi-mt65xx.yaml b/dts/Bindings/spi/mediatek,spi-mt65xx.yaml index 818130b11b..94ef0552bd 100644 --- a/dts/Bindings/spi/mediatek,spi-mt65xx.yaml +++ b/dts/Bindings/spi/mediatek,spi-mt65xx.yaml @@ -53,16 +53,20 @@ properties: maxItems: 1 clocks: + minItems: 3 items: - description: clock used for the parent clock - description: clock used for the muxes clock - description: clock used for the clock gate + - description: clock used for the AHB bus, this clock is optional clock-names: + minItems: 3 items: - const: parent-clk - const: sel-clk - const: spi-clk + - const: hclk mediatek,pad-select: $ref: /schemas/types.yaml#/definitions/uint32-array diff --git a/dts/Bindings/spi/mediatek,spi-mtk-snfi.yaml b/dts/Bindings/spi/mediatek,spi-mtk-snfi.yaml new file mode 100644 index 0000000000..6e6e02c917 --- /dev/null +++ b/dts/Bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPI-NAND flash controller for MediaTek ARM SoCs + +maintainers: + - Chuanhong Guo <gch981213@gmail.com> + +description: | + The Mediatek SPI-NAND flash controller is an extended version of + the Mediatek NAND flash controller. It can perform standard SPI + instructions with one continuous write and one read for up-to 0xa0 + bytes. It also supports typical SPI-NAND page cache operations + in single, dual or quad IO mode with pipelined ECC encoding/decoding + using the accompanying ECC engine. There should be only one spi + slave device following generic spi bindings. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - mediatek,mt7622-snand + - mediatek,mt7629-snand + + reg: + items: + - description: core registers + + interrupts: + items: + - description: NFI interrupt + + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + + clock-names: + items: + - const: nfi_clk + - const: pad_clk + + nand-ecc-engine: + description: device-tree node of the accompanying ECC engine. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - nand-ecc-engine + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt7622-clk.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + snfi: spi@1100d000 { + compatible = "mediatek,mt7622-snand"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; + clock-names = "nfi_clk", "pad_clk"; + nand-ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + }; + }; + }; diff --git a/dts/Bindings/spi/qcom,spi-geni-qcom.txt b/dts/Bindings/spi/qcom,spi-geni-qcom.txt deleted file mode 100644 index c8c1e913f4..0000000000 --- a/dts/Bindings/spi/qcom,spi-geni-qcom.txt +++ /dev/null @@ -1,39 +0,0 @@ -GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) - -The QUP v3 core is a GENI based AHB slave that provides a common data path -(an output FIFO and an input FIFO) for serial peripheral interface (SPI) -mini-core. - -SPI in master mode supports up to 50MHz, up to four chip selects, programmable -data path from 4 bits to 32 bits and numerous protocol variants. - -Required properties: -- compatible: Must contain "qcom,geni-spi". -- reg: Must contain SPI register location and length. -- interrupts: Must contain SPI controller interrupts. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. -- #address-cells: Must be <1> to define a chip select address on - the SPI bus. -- #size-cells: Must be <0>. - -SPI Controller nodes must be child of GENI based Qualcomm Universal -Peripharal. Please refer GENI based QUP wrapper controller node bindings -described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. - -SPI slave nodes must be children of the SPI master node and conform to SPI bus -binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. - -Example: - spi0: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0xa84000 0x4000>; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_spi_2_active>; - pinctrl-1 = <&qup_1_spi_2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/dts/Bindings/spi/qcom,spi-geni-qcom.yaml b/dts/Bindings/spi/qcom,spi-geni-qcom.yaml new file mode 100644 index 0000000000..e2c7b934c5 --- /dev/null +++ b/dts/Bindings/spi/qcom,spi-geni-qcom.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) + +maintainers: + - Andy Gross <agross@kernel.org> + - Bjorn Andersson <bjorn.andersson@linaro.org> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +description: + The QUP v3 core is a GENI based AHB slave that provides a common data path + (an output FIFO and an input FIFO) for serial peripheral interface (SPI) + mini-core. + + SPI in master mode supports up to 50MHz, up to four chip selects, + programmable data path from 4 bits to 32 bits and numerous protocol variants. + + SPI Controller nodes must be child of GENI based Qualcomm Universal + Peripharal. Please refer GENI based QUP wrapper controller node bindings + described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: qcom,geni-spi + + clocks: + maxItems: 1 + + clock-names: + const: se + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: qup-core + - const: qup-config + + interrupts: + maxItems: 1 + + operating-points-v2: true + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/interconnect/qcom,sc7180.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x00880000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + }; + + - | + #include <dt-bindings/dma/qcom-gpi.h> + + spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x00884000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_default>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml b/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml index 5a60fba14b..b622bb7363 100644 --- a/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml +++ b/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml @@ -8,8 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Qualcomm Quad Serial Peripheral Interface (QSPI) maintainers: - - Mukesh Savaliya <msavaliy@codeaurora.org> - - Akash Asthana <akashast@codeaurora.org> + - Bjorn Andersson <bjorn.andersson@linaro.org> description: The QSPI controller allows SPI protocol communication in single, dual, or quad wire transmission modes for read/write access to slaves such @@ -49,6 +48,7 @@ properties: maxItems: 2 interconnect-names: + minItems: 1 items: - const: qspi-config - const: qspi-memory diff --git a/dts/Bindings/spi/qcom,spi-qup.txt b/dts/Bindings/spi/qcom,spi-qup.txt deleted file mode 100644 index 5c090771c0..0000000000 --- a/dts/Bindings/spi/qcom,spi-qup.txt +++ /dev/null @@ -1,103 +0,0 @@ -Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) - -The QUP core is an AHB slave that provides a common data path (an output FIFO -and an input FIFO) for serial peripheral interface (SPI) mini-core. - -SPI in master mode supports up to 50MHz, up to four chip selects, programmable -data path from 4 bits to 32 bits and numerous protocol variants. - -Required properties: -- compatible: Should contain: - "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064. - "qcom,spi-qup-v2.1.1" for 8974 and later - "qcom,spi-qup-v2.2.1" for 8974 v2 and later. - -- reg: Should contain base register location and length -- interrupts: Interrupt number used by this controller - -- clocks: Should contain the core clock and the AHB clock. -- clock-names: Should be "core" for the core clock and "iface" for the - AHB clock. - -- #address-cells: Number of cells required to define a chip select - address on the SPI bus. Should be set to 1. -- #size-cells: Should be zero. - -Optional properties: -- spi-max-frequency: Specifies maximum SPI clock frequency, - Units - Hz. Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt -- num-cs: total number of chipselects -- cs-gpios: should specify GPIOs used for chipselects. - The gpios will be referred to as reg = <index> in the SPI child - nodes. If unspecified, a single SPI device without a chip - select can be used. - -- dmas: Two DMA channel specifiers following the convention outlined - in bindings/dma/dma.txt -- dma-names: Names for the dma channels, if present. There must be at - least one channel named "tx" for transmit and named "rx" for - receive. - -SPI slave nodes must be children of the SPI master node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - - spi_8: spi@f9964000 { /* BLSP2 QUP2 */ - - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xf9964000 0x1000>; - interrupts = <0 102 0>; - spi-max-frequency = <19200000>; - - clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - - dmas = <&blsp1_bam 13>, <&blsp1_bam 12>; - dma-names = "rx", "tx"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi8_default>; - - device@0 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <19200000>; - spi-cpol; - }; - - device@1 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; /* Chip select 1 */ - spi-max-frequency = <9600000>; - spi-cpha; - }; - - device@2 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <2>; /* Chip select 2 */ - spi-max-frequency = <19200000>; - spi-cpol; - spi-cpha; - }; - - device@3 { - compatible = "arm,pl022-dummy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <3>; /* Chip select 3 */ - spi-max-frequency = <19200000>; - spi-cpol; - spi-cpha; - spi-cs-high; - }; - }; diff --git a/dts/Bindings/spi/qcom,spi-qup.yaml b/dts/Bindings/spi/qcom,spi-qup.yaml new file mode 100644 index 0000000000..93f14dd01a --- /dev/null +++ b/dts/Bindings/spi/qcom,spi-qup.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) + +maintainers: + - Andy Gross <agross@kernel.org> + - Bjorn Andersson <bjorn.andersson@linaro.org> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +description: + The QUP core is an AHB slave that provides a common data path (an output FIFO + and an input FIFO) for serial peripheral interface (SPI) mini-core. + + SPI in master mode supports up to 50MHz, up to four chip selects, + programmable data path from 4 bits to 32 bits and numerous protocol variants. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064 + - qcom,spi-qup-v2.1.1 # for 8974 and later + - qcom,spi-qup-v2.2.1 # for 8974 v2 and later + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: iface + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8996.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + spi@7575000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07575000 0x600>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_spi1_default>; + pinctrl-1 = <&blsp1_spi1_sleep>; + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/dts/Bindings/spi/renesas,hspi.yaml b/dts/Bindings/spi/renesas,hspi.yaml index c0eccf7030..bab5d4b7fc 100644 --- a/dts/Bindings/spi/renesas,hspi.yaml +++ b/dts/Bindings/spi/renesas,hspi.yaml @@ -56,4 +56,3 @@ examples: #address-cells = <1>; #size-cells = <0>; }; - diff --git a/dts/Bindings/spi/renesas,rspi.yaml b/dts/Bindings/spi/renesas,rspi.yaml index 2c3c6bd6ec..f45d3b75d6 100644 --- a/dts/Bindings/spi/renesas,rspi.yaml +++ b/dts/Bindings/spi/renesas,rspi.yaml @@ -21,6 +21,7 @@ properties: - enum: - renesas,rspi-r7s72100 # RZ/A1H - renesas,rspi-r7s9210 # RZ/A2 + - renesas,r9a07g043-rspi # RZ/G2UL - renesas,r9a07g044-rspi # RZ/G2{L,LC} - renesas,r9a07g054-rspi # RZ/V2L - const: renesas,rspi-rz @@ -124,6 +125,7 @@ allOf: contains: enum: - renesas,qspi + - renesas,r9a07g043-rspi - renesas,r9a07g044-rspi - renesas,r9a07g054-rspi then: diff --git a/dts/Bindings/spi/spi-davinci.txt b/dts/Bindings/spi/spi-davinci.txt index 200c7fc7b0..f012888656 100644 --- a/dts/Bindings/spi/spi-davinci.txt +++ b/dts/Bindings/spi/spi-davinci.txt @@ -78,7 +78,7 @@ spi0:spi@20bf0000 { interrupts = <338>; clocks = <&clkspi>; - flash: n25q032@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p32"; diff --git a/dts/Bindings/spi/spi-pl022.yaml b/dts/Bindings/spi/spi-pl022.yaml index bda45ff3d2..0e382119c6 100644 --- a/dts/Bindings/spi/spi-pl022.yaml +++ b/dts/Bindings/spi/spi-pl022.yaml @@ -143,7 +143,7 @@ examples: <&dma_controller 24 0>; dma-names = "rx", "tx"; - m25p80@1 { + flash@1 { compatible = "st,m25p80"; reg = <1>; spi-max-frequency = <12000000>; |