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-rw-r--r--dts/Bindings/timer/arm,sp804.txt29
-rw-r--r--dts/Bindings/timer/arm,sp804.yaml97
-rw-r--r--dts/Bindings/timer/cdns,ttc.yaml2
-rw-r--r--dts/Bindings/timer/mediatek,mtk-timer.txt1
-rw-r--r--dts/Bindings/timer/renesas,cmt.yaml4
-rw-r--r--dts/Bindings/timer/samsung,exynos4210-mct.yaml25
-rw-r--r--dts/Bindings/timer/snps,dw-apb-timer.yaml2
7 files changed, 130 insertions, 30 deletions
diff --git a/dts/Bindings/timer/arm,sp804.txt b/dts/Bindings/timer/arm,sp804.txt
deleted file mode 100644
index 5cd8eee74a..0000000000
--- a/dts/Bindings/timer/arm,sp804.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-ARM sp804 Dual Timers
----------------------------------------
-
-Required properties:
-- compatible: Should be "arm,sp804" & "arm,primecell"
-- interrupts: Should contain the list of Dual Timer interrupts. This is the
- interrupt for timer 1 and timer 2. In the case of a single entry, it is
- the combined interrupt or if "arm,sp804-has-irq" is present that
- specifies which timer interrupt is connected.
-- reg: Should contain location and length for dual timer register.
-- clocks: clocks driving the dual timer hardware. This list should be 1 or 3
- clocks. With 3 clocks, the order is timer0 clock, timer1 clock,
- apb_pclk. A single clock can also be specified if the same clock is
- used for all clock inputs.
-
-Optional properties:
-- arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this
- specifies if the irq connection is for timer 1 or timer 2. A value of 1
- or 2 should be used.
-
-Example:
-
- timer0: timer@fc800000 {
- compatible = "arm,sp804", "arm,primecell";
- reg = <0xfc800000 0x1000>;
- interrupts = <0 0 4>, <0 1 4>;
- clocks = <&timclk1 &timclk2 &pclk>;
- clock-names = "timer1", "timer2", "apb_pclk";
- };
diff --git a/dts/Bindings/timer/arm,sp804.yaml b/dts/Bindings/timer/arm,sp804.yaml
new file mode 100644
index 0000000000..e35d305325
--- /dev/null
+++ b/dts/Bindings/timer/arm,sp804.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM sp804 Dual Timers
+
+maintainers:
+ - Haojian Zhuang <haojian.zhuang@linaro.org>
+
+description: |+
+ The Arm SP804 IP implements two independent timers, configurable for
+ 16 or 32 bit operation and capable of running in one-shot, periodic, or
+ free-running mode. The input clock is shared, but can be gated and prescaled
+ independently for each timer.
+
+ There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
+ SoCs, such as Hi1212, should use the dedicated compatible: "hisilicon,sp804".
+
+# Need a custom select here or 'arm,primecell' will match on lots of nodes
+select:
+ properties:
+ compatible:
+ contains:
+ oneOf:
+ - const: arm,sp804
+ - const: hisilicon,sp804
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - arm,sp804
+ - hisilicon,sp804
+ - const: arm,primecell
+
+ interrupts:
+ description: |
+ If two interrupts are listed, those are the interrupts for timer
+ 1 and 2, respectively. If there is only a single interrupt, it is
+ either a combined interrupt or the sole interrupt of one timer, as
+ specified by the "arm,sp804-has-irq" property.
+ minItems: 1
+ maxItems: 2
+
+ reg:
+ description: The physical base address of the SP804 IP.
+ maxItems: 1
+
+ clocks:
+ description: |
+ Clocks driving the dual timer hardware. This list should
+ be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
+ clock, apb_pclk. A single clock can also be specified if the same
+ clock is used for all clock inputs.
+ oneOf:
+ - items:
+ - description: clock for timer 1
+ - description: clock for timer 2
+ - description: bus clock
+ - items:
+ - description: unified clock for both timers and the bus
+
+ clock-names: true
+ # The original binding did not specify any clock names, and there is no
+ # consistent naming used in the existing DTs. The primecell binding
+ # requires the "apb_pclk" name, so we need this property.
+ # Use "timer0clk", "timer1clk", "apb_pclk" for new DTs.
+
+ arm,sp804-has-irq:
+ description: If only one interrupt line is connected to the interrupt
+ controller, this property specifies which timer is connected to this
+ line.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 2
+
+required:
+ - compatible
+ - interrupts
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ timer0: timer@fc800000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0xfc800000 0x1000>;
+ interrupts = <0 0 4>, <0 1 4>;
+ clocks = <&timclk1>, <&timclk2>, <&pclk>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ };
diff --git a/dts/Bindings/timer/cdns,ttc.yaml b/dts/Bindings/timer/cdns,ttc.yaml
index c532b60b9c..8615353f69 100644
--- a/dts/Bindings/timer/cdns,ttc.yaml
+++ b/dts/Bindings/timer/cdns,ttc.yaml
@@ -36,6 +36,8 @@ required:
- interrupts
- clocks
+additionalProperties: false
+
examples:
- |
ttc0: ttc0@f8001000 {
diff --git a/dts/Bindings/timer/mediatek,mtk-timer.txt b/dts/Bindings/timer/mediatek,mtk-timer.txt
index 0d256486f8..690a9c0966 100644
--- a/dts/Bindings/timer/mediatek,mtk-timer.txt
+++ b/dts/Bindings/timer/mediatek,mtk-timer.txt
@@ -22,6 +22,7 @@ Required properties:
For those SoCs that use SYST
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
+ * "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
* "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)
diff --git a/dts/Bindings/timer/renesas,cmt.yaml b/dts/Bindings/timer/renesas,cmt.yaml
index 7e4dc5623d..428db3a21b 100644
--- a/dts/Bindings/timer/renesas,cmt.yaml
+++ b/dts/Bindings/timer/renesas,cmt.yaml
@@ -39,6 +39,7 @@ properties:
- items:
- enum:
- renesas,r8a73a4-cmt0 # 32-bit CMT0 on R-Mobile APE6
+ - renesas,r8a7742-cmt0 # 32-bit CMT0 on RZ/G1H
- renesas,r8a7743-cmt0 # 32-bit CMT0 on RZ/G1M
- renesas,r8a7744-cmt0 # 32-bit CMT0 on RZ/G1N
- renesas,r8a7745-cmt0 # 32-bit CMT0 on RZ/G1E
@@ -53,6 +54,7 @@ properties:
- items:
- enum:
- renesas,r8a73a4-cmt1 # 48-bit CMT1 on R-Mobile APE6
+ - renesas,r8a7742-cmt1 # 48-bit CMT1 on RZ/G1H
- renesas,r8a7743-cmt1 # 48-bit CMT1 on RZ/G1M
- renesas,r8a7744-cmt1 # 48-bit CMT1 on RZ/G1N
- renesas,r8a7745-cmt1 # 48-bit CMT1 on RZ/G1E
@@ -69,6 +71,7 @@ properties:
- renesas,r8a774a1-cmt0 # 32-bit CMT0 on RZ/G2M
- renesas,r8a774b1-cmt0 # 32-bit CMT0 on RZ/G2N
- renesas,r8a774c0-cmt0 # 32-bit CMT0 on RZ/G2E
+ - renesas,r8a774e1-cmt0 # 32-bit CMT0 on RZ/G2H
- renesas,r8a7795-cmt0 # 32-bit CMT0 on R-Car H3
- renesas,r8a7796-cmt0 # 32-bit CMT0 on R-Car M3-W
- renesas,r8a77965-cmt0 # 32-bit CMT0 on R-Car M3-N
@@ -83,6 +86,7 @@ properties:
- renesas,r8a774a1-cmt1 # 48-bit CMT on RZ/G2M
- renesas,r8a774b1-cmt1 # 48-bit CMT on RZ/G2N
- renesas,r8a774c0-cmt1 # 48-bit CMT on RZ/G2E
+ - renesas,r8a774e1-cmt1 # 48-bit CMT on RZ/G2H
- renesas,r8a7795-cmt1 # 48-bit CMT on R-Car H3
- renesas,r8a7796-cmt1 # 48-bit CMT on R-Car M3-W
- renesas,r8a77965-cmt1 # 48-bit CMT on R-Car M3-N
diff --git a/dts/Bindings/timer/samsung,exynos4210-mct.yaml b/dts/Bindings/timer/samsung,exynos4210-mct.yaml
index 37bd01a62c..f11cbc7ccc 100644
--- a/dts/Bindings/timer/samsung,exynos4210-mct.yaml
+++ b/dts/Bindings/timer/samsung,exynos4210-mct.yaml
@@ -23,6 +23,15 @@ properties:
- samsung,exynos4210-mct
- samsung,exynos4412-mct
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - pattern: "^(fin_pll|mct)$"
+ - pattern: "^(fin_pll|mct)$"
+
reg:
maxItems: 1
@@ -49,6 +58,8 @@ properties:
required:
- compatible
+ - clock-names
+ - clocks
- interrupts
- reg
@@ -59,11 +70,15 @@ examples:
// In this example, the IP contains two local timers, using separate
// interrupts, so two local timer interrupts have been specified,
// in addition to four global timer interrupts.
+ #include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
@@ -75,11 +90,15 @@ examples:
- |
// In this example, the timer interrupts are connected to two separate
// interrupt controllers. Hence, an interrupts-extended is needed.
+ #include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+
interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<&combiner 12 6>,
@@ -92,11 +111,14 @@ examples:
// In this example, the IP contains four local timers, but using
// a per-processor interrupt to handle them. Only one first local
// interrupt is specified.
+ #include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@10050000 {
compatible = "samsung,exynos4412-mct";
reg = <0x10050000 0x800>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+ clock-names = "fin_pll", "mct";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
@@ -109,11 +131,14 @@ examples:
// In this example, the IP contains four local timers, but using
// a per-processor interrupt to handle them. All the local timer
// interrupts are specified.
+ #include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@10050000 {
compatible = "samsung,exynos4412-mct";
reg = <0x10050000 0x800>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+ clock-names = "fin_pll", "mct";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/dts/Bindings/timer/snps,dw-apb-timer.yaml b/dts/Bindings/timer/snps,dw-apb-timer.yaml
index 7b39e3204f..2fc617377e 100644
--- a/dts/Bindings/timer/snps,dw-apb-timer.yaml
+++ b/dts/Bindings/timer/snps,dw-apb-timer.yaml
@@ -45,7 +45,7 @@ properties:
frequency in HZ, but is defined only for the backwards compatibility
with the picoxcell platform.
-unevaluatedProperties: false
+additionalProperties: false
required:
- compatible
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-28 14:37:11 +0000