diff options
Diffstat (limited to 'dts/Bindings/timer')
| -rw-r--r-- | dts/Bindings/timer/fsl,imxgpt.txt | 39 | ||||
| -rw-r--r-- | dts/Bindings/timer/mediatek,mtk-timer.txt | 11 | ||||
| -rw-r--r-- | dts/Bindings/timer/nvidia,tegra210-timer.txt | 36 | ||||
| -rw-r--r-- | dts/Bindings/timer/renesas,cmt.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/timer/renesas,tmu.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/timer/socionext,milbeaut-timer.txt | 17 |
6 files changed, 97 insertions, 9 deletions
diff --git a/dts/Bindings/timer/fsl,imxgpt.txt b/dts/Bindings/timer/fsl,imxgpt.txt index 9809b11f71..5d8fd5b525 100644 --- a/dts/Bindings/timer/fsl,imxgpt.txt +++ b/dts/Bindings/timer/fsl,imxgpt.txt @@ -2,17 +2,44 @@ Freescale i.MX General Purpose Timer (GPT) Required properties: -- compatible : should be "fsl,<soc>-gpt" -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 4 interrupts; one per timer channel. -- clocks : The clocks provided by the SoC to drive the timer. +- compatible : should be one of following: + for i.MX1: + - "fsl,imx1-gpt"; + for i.MX21: + - "fsl,imx21-gpt"; + for i.MX27: + - "fsl,imx27-gpt", "fsl,imx21-gpt"; + for i.MX31: + - "fsl,imx31-gpt"; + for i.MX25: + - "fsl,imx25-gpt", "fsl,imx31-gpt"; + for i.MX50: + - "fsl,imx50-gpt", "fsl,imx31-gpt"; + for i.MX51: + - "fsl,imx51-gpt", "fsl,imx31-gpt"; + for i.MX53: + - "fsl,imx53-gpt", "fsl,imx31-gpt"; + for i.MX6Q: + - "fsl,imx6q-gpt", "fsl,imx31-gpt"; + for i.MX6DL: + - "fsl,imx6dl-gpt"; + for i.MX6SL: + - "fsl,imx6sl-gpt", "fsl,imx6dl-gpt"; + for i.MX6SX: + - "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; +- reg : specifies base physical address and size of the registers. +- interrupts : should be the gpt interrupt. +- clocks : the clocks provided by the SoC to drive the timer, must contain + an entry for each entry in clock-names. +- clock-names : must include "ipg" entry first, then "per" entry. Example: gpt1: timer@10003000 { - compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; + compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; reg = <0x10003000 0x1000>; interrupts = <26>; - clocks = <&clks 46>, <&clks 61>; + clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; }; diff --git a/dts/Bindings/timer/mediatek,mtk-timer.txt b/dts/Bindings/timer/mediatek,mtk-timer.txt index 18d4d0166c..ff7c567a79 100644 --- a/dts/Bindings/timer/mediatek,mtk-timer.txt +++ b/dts/Bindings/timer/mediatek,mtk-timer.txt @@ -1,7 +1,7 @@ -Mediatek Timers +MediaTek Timers --------------- -Mediatek SoCs have two different timers on different platforms, +MediaTek SoCs have two different timers on different platforms, - GPT (General Purpose Timer) - SYST (System Timer) @@ -9,6 +9,7 @@ The proper timer will be selected automatically by driver. Required properties: - compatible should contain: + For those SoCs that use GPT * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT) * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT) * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT) @@ -17,7 +18,11 @@ Required properties: * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT) * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT) * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT) - * "mediatek,mt6765-timer" for MT6765 compatible timers (SYST) + + For those SoCs that use SYST + * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) + * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST) + - reg: Should contain location and length for timer register. - clocks: Should contain system clock. diff --git a/dts/Bindings/timer/nvidia,tegra210-timer.txt b/dts/Bindings/timer/nvidia,tegra210-timer.txt new file mode 100644 index 0000000000..032cda96fe --- /dev/null +++ b/dts/Bindings/timer/nvidia,tegra210-timer.txt @@ -0,0 +1,36 @@ +NVIDIA Tegra210 timer + +The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived +from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock +(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic, +or watchdog interrupts. + +Required properties: +- compatible : "nvidia,tegra210-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 14 interrupts; one per each timer channels 0 through + 13. +- clocks : Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + +timer@60005000 { + compatible = "nvidia,tegra210-timer"; + reg = <0x0 0x60005000 0x0 0x400>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_TIMER>; + clock-names = "timer"; +}; diff --git a/dts/Bindings/timer/renesas,cmt.txt b/dts/Bindings/timer/renesas,cmt.txt index 862a80f038..c0594450e9 100644 --- a/dts/Bindings/timer/renesas,cmt.txt +++ b/dts/Bindings/timer/renesas,cmt.txt @@ -32,6 +32,8 @@ Required Properties: - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470. - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1. - "renesas,r8a774a1-cmt1" for the 48-bit CMT1 device included in r8a774a1. + - "renesas,r8a774c0-cmt0" for the 32-bit CMT0 device included in r8a774c0. + - "renesas,r8a774c0-cmt1" for the 48-bit CMT1 device included in r8a774c0. - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. diff --git a/dts/Bindings/timer/renesas,tmu.txt b/dts/Bindings/timer/renesas,tmu.txt index 4ddff85837..13ad07416b 100644 --- a/dts/Bindings/timer/renesas,tmu.txt +++ b/dts/Bindings/timer/renesas,tmu.txt @@ -10,6 +10,7 @@ Required Properties: - compatible: must contain one or more of the following: - "renesas,tmu-r8a7740" for the r8a7740 TMU + - "renesas,tmu-r8a774c0" for the r8a774C0 TMU - "renesas,tmu-r8a7778" for the r8a7778 TMU - "renesas,tmu-r8a7779" for the r8a7779 TMU - "renesas,tmu-r8a77970" for the r8a77970 TMU diff --git a/dts/Bindings/timer/socionext,milbeaut-timer.txt b/dts/Bindings/timer/socionext,milbeaut-timer.txt new file mode 100644 index 0000000000..ac44c4b675 --- /dev/null +++ b/dts/Bindings/timer/socionext,milbeaut-timer.txt @@ -0,0 +1,17 @@ +Milbeaut SoCs Timer Controller + +Required properties: + +- compatible : should be "socionext,milbeaut-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : The interrupt of the first timer. +- clocks: phandle to the input clk. + +Example: + +timer { + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20> + interrupts = <0 91 4>; + clocks = <&clk 4>; +}; |