diff options
Diffstat (limited to 'dts/Bindings/timer')
| -rw-r--r-- | dts/Bindings/timer/arm,mps2-timer.txt | 28 | ||||
| -rw-r--r-- | dts/Bindings/timer/ezchip,nps400-timer.txt | 15 | ||||
| -rw-r--r-- | dts/Bindings/timer/snps,arc-timer.txt | 31 | ||||
| -rw-r--r-- | dts/Bindings/timer/snps,archs-gfrc.txt | 14 | ||||
| -rw-r--r-- | dts/Bindings/timer/snps,archs-rtc.txt | 14 |
5 files changed, 102 insertions, 0 deletions
diff --git a/dts/Bindings/timer/arm,mps2-timer.txt b/dts/Bindings/timer/arm,mps2-timer.txt new file mode 100644 index 0000000000..48f84d74ed --- /dev/null +++ b/dts/Bindings/timer/arm,mps2-timer.txt @@ -0,0 +1,28 @@ +ARM MPS2 timer + +The MPS2 platform has simple general-purpose 32 bits timers. + +Required properties: +- compatible : Should be "arm,mps2-timer" +- reg : Address and length of the register set +- interrupts : Reference to the timer interrupt + +Required clocking property, have to be one of: +- clocks : The input clock of the timer +- clock-frequency : The rate in HZ in input of the ARM MPS2 timer + +Examples: + +timer1: mps2-timer@40000000 { + compatible = "arm,mps2-timer"; + reg = <0x40000000 0x1000>; + interrupts = <8>; + clocks = <&sysclk>; +}; + +timer2: mps2-timer@40001000 { + compatible = "arm,mps2-timer"; + reg = <0x40001000 0x1000>; + interrupts = <9>; + clock-frequency = <25000000>; +}; diff --git a/dts/Bindings/timer/ezchip,nps400-timer.txt b/dts/Bindings/timer/ezchip,nps400-timer.txt new file mode 100644 index 0000000000..c8c03d7003 --- /dev/null +++ b/dts/Bindings/timer/ezchip,nps400-timer.txt @@ -0,0 +1,15 @@ +NPS Network Processor + +Required properties: + +- compatible : should be "ezchip,nps400-timer" + +Clocks required for compatible = "ezchip,nps400-timer": +- clocks : Must contain a single entry describing the clock input + +Example: + +timer { + compatible = "ezchip,nps400-timer"; + clocks = <&sysclk>; +}; diff --git a/dts/Bindings/timer/snps,arc-timer.txt b/dts/Bindings/timer/snps,arc-timer.txt new file mode 100644 index 0000000000..4ef024630d --- /dev/null +++ b/dts/Bindings/timer/snps,arc-timer.txt @@ -0,0 +1,31 @@ +Synopsys ARC Local Timer with Interrupt Capabilities +- Found on all ARC CPUs (ARC700/ARCHS) +- Can be optionally programmed to interrupt on Limit +- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically + TIMER0 used as clockevent provider (true for all ARC cores) + TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) + +Required properties: + +- compatible : should be "snps,arc-timer" +- interrupts : single Interrupt going into parent intc + (16 for ARCHS cores, 3 for ARC700 cores) +- clocks : phandle to the source clock + +Optional properties: + +- interrupt-parent : phandle to parent intc + +Example: + + timer0 { + compatible = "snps,arc-timer"; + interrupts = <3>; + interrupt-parent = <&core_intc>; + clocks = <&core_clk>; + }; + + timer1 { + compatible = "snps,arc-timer"; + clocks = <&core_clk>; + }; diff --git a/dts/Bindings/timer/snps,archs-gfrc.txt b/dts/Bindings/timer/snps,archs-gfrc.txt new file mode 100644 index 0000000000..b6cd1b3922 --- /dev/null +++ b/dts/Bindings/timer/snps,archs-gfrc.txt @@ -0,0 +1,14 @@ +Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs +- clocksource provider for SMP SoC + +Required properties: + +- compatible : should be "snps,archs-gfrc" +- clocks : phandle to the source clock + +Example: + + gfrc { + compatible = "snps,archs-gfrc"; + clocks = <&core_clk>; + }; diff --git a/dts/Bindings/timer/snps,archs-rtc.txt b/dts/Bindings/timer/snps,archs-rtc.txt new file mode 100644 index 0000000000..47bd7a702f --- /dev/null +++ b/dts/Bindings/timer/snps,archs-rtc.txt @@ -0,0 +1,14 @@ +Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs +- clocksource provider for UP SoC + +Required properties: + +- compatible : should be "snps,archs-rtc" +- clocks : phandle to the source clock + +Example: + + rtc { + compatible = "snps,arc-rtc"; + clocks = <&core_clk>; + }; |