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-rw-r--r--dts/Bindings/timer/arm,arch_timer.yaml10
-rw-r--r--dts/Bindings/timer/arm,arch_timer_mmio.yaml11
-rw-r--r--dts/Bindings/timer/cadence,ttc-timer.txt21
-rw-r--r--dts/Bindings/timer/cdns,ttc.yaml48
-rw-r--r--dts/Bindings/timer/fsl,imxgpt.txt45
-rw-r--r--dts/Bindings/timer/fsl,imxgpt.yaml72
-rw-r--r--dts/Bindings/timer/ingenic,tcu.txt138
-rw-r--r--dts/Bindings/timer/ingenic,tcu.yaml280
-rw-r--r--dts/Bindings/timer/nxp,sysctr-timer.txt25
-rw-r--r--dts/Bindings/timer/nxp,sysctr-timer.yaml54
-rw-r--r--dts/Bindings/timer/nxp,tpm-timer.txt28
-rw-r--r--dts/Bindings/timer/nxp,tpm-timer.yaml61
-rw-r--r--dts/Bindings/timer/renesas,cmt.txt110
-rw-r--r--dts/Bindings/timer/renesas,cmt.yaml182
-rw-r--r--dts/Bindings/timer/renesas,em-sti.yaml46
-rw-r--r--dts/Bindings/timer/renesas,mtu2.txt42
-rw-r--r--dts/Bindings/timer/renesas,mtu2.yaml76
-rw-r--r--dts/Bindings/timer/renesas,ostm.txt31
-rw-r--r--dts/Bindings/timer/renesas,ostm.yaml59
-rw-r--r--dts/Bindings/timer/snps,dw-apb-timer.yaml88
20 files changed, 979 insertions, 448 deletions
diff --git a/dts/Bindings/timer/arm,arch_timer.yaml b/dts/Bindings/timer/arm,arch_timer.yaml
index fa255672e8..2c75105c13 100644
--- a/dts/Bindings/timer/arm,arch_timer.yaml
+++ b/dts/Bindings/timer/arm,arch_timer.yaml
@@ -28,10 +28,10 @@ properties:
- arm,armv7-timer
- items:
- enum:
- - arm,armv7-timer
+ - arm,armv7-timer
- items:
- enum:
- - arm,armv8-timer
+ - arm,armv8-timer
interrupts:
items:
@@ -51,6 +51,12 @@ properties:
description: If present, the timer is powered through an always-on power
domain, therefore it never loses context.
+ allwinner,erratum-unknown1:
+ type: boolean
+ description: Indicates the presence of an erratum found in Allwinner SoCs,
+ where reading certain values from the counter is unreliable. This also
+ affects writes to the tval register, due to the implicit counter read.
+
fsl,erratum-a008585:
type: boolean
description: Indicates the presence of QorIQ erratum A-008585, which says
diff --git a/dts/Bindings/timer/arm,arch_timer_mmio.yaml b/dts/Bindings/timer/arm,arch_timer_mmio.yaml
index 582bbef62b..d83a1f97f9 100644
--- a/dts/Bindings/timer/arm,arch_timer_mmio.yaml
+++ b/dts/Bindings/timer/arm,arch_timer_mmio.yaml
@@ -20,7 +20,7 @@ properties:
compatible:
items:
- enum:
- - arm,armv7-timer-mem
+ - arm,armv7-timer-mem
reg:
maxItems: 1
@@ -65,10 +65,9 @@ patternProperties:
description: A timer node has up to 8 frame sub-nodes, each with the following properties.
properties:
frame-number:
- allOf:
- - $ref: "/schemas/types.yaml#/definitions/uint32"
- - minimum: 0
- maximum: 7
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 7
interrupts:
minItems: 1
@@ -77,7 +76,7 @@ patternProperties:
- description: physical timer irq
- description: virtual timer irq
- reg :
+ reg:
minItems: 1
maxItems: 2
items:
diff --git a/dts/Bindings/timer/cadence,ttc-timer.txt b/dts/Bindings/timer/cadence,ttc-timer.txt
deleted file mode 100644
index eeee6cd51e..0000000000
--- a/dts/Bindings/timer/cadence,ttc-timer.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Cadence TTC - Triple Timer Counter
-
-Required properties:
-- compatible : Should be "cdns,ttc".
-- reg : Specifies base physical address and size of the registers.
-- interrupts : A list of 3 interrupts; one per timer channel.
-- clocks: phandle to the source clock
-
-Optional properties:
-- timer-width: Bit width of the timer, necessary if not 16.
-
-Example:
-
-ttc0: ttc0@f8001000 {
- interrupt-parent = <&intc>;
- interrupts = < 0 10 4 0 11 4 0 12 4 >;
- compatible = "cdns,ttc";
- reg = <0xF8001000 0x1000>;
- clocks = <&cpu_clk 3>;
- timer-width = <32>;
-};
diff --git a/dts/Bindings/timer/cdns,ttc.yaml b/dts/Bindings/timer/cdns,ttc.yaml
new file mode 100644
index 0000000000..c532b60b9c
--- /dev/null
+++ b/dts/Bindings/timer/cdns,ttc.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/cdns,ttc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence TTC - Triple Timer Counter
+
+maintainers:
+ - Michal Simek <michal.simek@xilinx.com>
+
+properties:
+ compatible:
+ const: cdns,ttc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 3
+ maxItems: 3
+ description: |
+ A list of 3 interrupts; one per timer channel.
+
+ clocks:
+ maxItems: 1
+
+ timer-width:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ description: |
+ Bit width of the timer, necessary if not 16.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ ttc0: ttc0@f8001000 {
+ interrupt-parent = <&intc>;
+ interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
+ compatible = "cdns,ttc";
+ reg = <0xF8001000 0x1000>;
+ clocks = <&cpu_clk 3>;
+ timer-width = <32>;
+ };
diff --git a/dts/Bindings/timer/fsl,imxgpt.txt b/dts/Bindings/timer/fsl,imxgpt.txt
deleted file mode 100644
index 5d8fd5b525..0000000000
--- a/dts/Bindings/timer/fsl,imxgpt.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-Freescale i.MX General Purpose Timer (GPT)
-
-Required properties:
-
-- compatible : should be one of following:
- for i.MX1:
- - "fsl,imx1-gpt";
- for i.MX21:
- - "fsl,imx21-gpt";
- for i.MX27:
- - "fsl,imx27-gpt", "fsl,imx21-gpt";
- for i.MX31:
- - "fsl,imx31-gpt";
- for i.MX25:
- - "fsl,imx25-gpt", "fsl,imx31-gpt";
- for i.MX50:
- - "fsl,imx50-gpt", "fsl,imx31-gpt";
- for i.MX51:
- - "fsl,imx51-gpt", "fsl,imx31-gpt";
- for i.MX53:
- - "fsl,imx53-gpt", "fsl,imx31-gpt";
- for i.MX6Q:
- - "fsl,imx6q-gpt", "fsl,imx31-gpt";
- for i.MX6DL:
- - "fsl,imx6dl-gpt";
- for i.MX6SL:
- - "fsl,imx6sl-gpt", "fsl,imx6dl-gpt";
- for i.MX6SX:
- - "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
-- reg : specifies base physical address and size of the registers.
-- interrupts : should be the gpt interrupt.
-- clocks : the clocks provided by the SoC to drive the timer, must contain
- an entry for each entry in clock-names.
-- clock-names : must include "ipg" entry first, then "per" entry.
-
-Example:
-
-gpt1: timer@10003000 {
- compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
- reg = <0x10003000 0x1000>;
- interrupts = <26>;
- clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
- <&clks IMX27_CLK_PER1_GATE>;
- clock-names = "ipg", "per";
-};
diff --git a/dts/Bindings/timer/fsl,imxgpt.yaml b/dts/Bindings/timer/fsl,imxgpt.yaml
new file mode 100644
index 0000000000..883f7f4665
--- /dev/null
+++ b/dts/Bindings/timer/fsl,imxgpt.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/fsl,imxgpt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX General Purpose Timer (GPT)
+
+maintainers:
+ - Sascha Hauer <s.hauer@pengutronix.de>
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,imx1-gpt
+ - const: fsl,imx21-gpt
+ - items:
+ - const: fsl,imx27-gpt
+ - const: fsl,imx21-gpt
+ - const: fsl,imx31-gpt
+ - items:
+ - enum:
+ - fsl,imx25-gpt
+ - fsl,imx50-gpt
+ - fsl,imx51-gpt
+ - fsl,imx53-gpt
+ - fsl,imx6q-gpt
+ - const: fsl,imx31-gpt
+ - const: fsl,imx6dl-gpt
+ - items:
+ - enum:
+ - fsl,imx6sl-gpt
+ - fsl,imx6sx-gpt
+ - const: fsl,imx6dl-gpt
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: SoC GPT ipg clock
+ - description: SoC GPT per clock
+
+ clock-names:
+ items:
+ - const: ipg
+ - const: per
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx27-clock.h>
+
+ timer@10003000 {
+ compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
+ reg = <0x10003000 0x1000>;
+ interrupts = <26>;
+ clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
+ <&clks IMX27_CLK_PER1_GATE>;
+ clock-names = "ipg", "per";
+ };
diff --git a/dts/Bindings/timer/ingenic,tcu.txt b/dts/Bindings/timer/ingenic,tcu.txt
deleted file mode 100644
index 91f7049518..0000000000
--- a/dts/Bindings/timer/ingenic,tcu.txt
+++ /dev/null
@@ -1,138 +0,0 @@
-Ingenic JZ47xx SoCs Timer/Counter Unit devicetree bindings
-==========================================================
-
-For a description of the TCU hardware and drivers, have a look at
-Documentation/mips/ingenic-tcu.rst.
-
-Required properties:
-
-- compatible: Must be one of:
- * ingenic,jz4740-tcu
- * ingenic,jz4725b-tcu
- * ingenic,jz4770-tcu
- * ingenic,x1000-tcu
- followed by "simple-mfd".
-- reg: Should be the offset/length value corresponding to the TCU registers
-- clocks: List of phandle & clock specifiers for clocks external to the TCU.
- The "pclk", "rtc" and "ext" clocks should be provided. The "tcu" clock
- should be provided if the SoC has it.
-- clock-names: List of name strings for the external clocks.
-- #clock-cells: Should be <1>;
- Clock consumers specify this argument to identify a clock. The valid values
- may be found in <dt-bindings/clock/ingenic,tcu.h>.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The value should be 1.
-- interrupts : Specifies the interrupt the controller is connected to.
-
-Optional properties:
-
-- ingenic,pwm-channels-mask: Bitmask of TCU channels reserved for PWM use.
- Default value is 0xfc.
-
-
-Children nodes
-==========================================================
-
-
-PWM node:
----------
-
-Required properties:
-
-- compatible: Must be one of:
- * ingenic,jz4740-pwm
- * ingenic,jz4725b-pwm
-- #pwm-cells: Should be 3. See ../pwm/pwm.yaml for a description of the cell
- format.
-- clocks: List of phandle & clock specifiers for the TCU clocks.
-- clock-names: List of name strings for the TCU clocks.
-
-
-Watchdog node:
---------------
-
-Required properties:
-
-- compatible: Must be "ingenic,jz4740-watchdog"
-- clocks: phandle to the WDT clock
-- clock-names: should be "wdt"
-
-
-OS Timer node:
----------
-
-Required properties:
-
-- compatible: Must be one of:
- * ingenic,jz4725b-ost
- * ingenic,jz4770-ost
-- clocks: phandle to the OST clock
-- clock-names: should be "ost"
-- interrupts : Specifies the interrupt the OST is connected to.
-
-
-Example
-==========================================================
-
-#include <dt-bindings/clock/jz4770-cgu.h>
-#include <dt-bindings/clock/ingenic,tcu.h>
-
-/ {
- tcu: timer@10002000 {
- compatible = "ingenic,jz4770-tcu", "simple-mfd";
- reg = <0x10002000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x10002000 0x1000>;
-
- #clock-cells = <1>;
-
- clocks = <&cgu JZ4770_CLK_RTC
- &cgu JZ4770_CLK_EXT
- &cgu JZ4770_CLK_PCLK>;
- clock-names = "rtc", "ext", "pclk";
-
- interrupt-controller;
- #interrupt-cells = <1>;
-
- interrupt-parent = <&intc>;
- interrupts = <27 26 25>;
-
- watchdog: watchdog@0 {
- compatible = "ingenic,jz4740-watchdog";
- reg = <0x0 0xc>;
-
- clocks = <&tcu TCU_CLK_WDT>;
- clock-names = "wdt";
- };
-
- pwm: pwm@40 {
- compatible = "ingenic,jz4740-pwm";
- reg = <0x40 0x80>;
-
- #pwm-cells = <3>;
-
- clocks = <&tcu TCU_CLK_TIMER0
- &tcu TCU_CLK_TIMER1
- &tcu TCU_CLK_TIMER2
- &tcu TCU_CLK_TIMER3
- &tcu TCU_CLK_TIMER4
- &tcu TCU_CLK_TIMER5
- &tcu TCU_CLK_TIMER6
- &tcu TCU_CLK_TIMER7>;
- clock-names = "timer0", "timer1", "timer2", "timer3",
- "timer4", "timer5", "timer6", "timer7";
- };
-
- ost: timer@e0 {
- compatible = "ingenic,jz4770-ost";
- reg = <0xe0 0x20>;
-
- clocks = <&tcu TCU_CLK_OST>;
- clock-names = "ost";
-
- interrupts = <15>;
- };
- };
-};
diff --git a/dts/Bindings/timer/ingenic,tcu.yaml b/dts/Bindings/timer/ingenic,tcu.yaml
new file mode 100644
index 0000000000..03893e6a2f
--- /dev/null
+++ b/dts/Bindings/timer/ingenic,tcu.yaml
@@ -0,0 +1,280 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/ingenic,tcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs Timer/Counter Unit (TCU) devicetree bindings
+
+description: |
+ For a description of the TCU hardware and drivers, have a look at
+ Documentation/mips/ingenic-tcu.rst.
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ingenic,jz4740-tcu
+ - ingenic,jz4725b-tcu
+ - ingenic,jz4770-tcu
+ - ingenic,jz4780-tcu
+ - ingenic,x1000-tcu
+ required:
+ - compatible
+
+properties:
+ $nodename:
+ pattern: "^timer@[0-9a-f]+$"
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupt-controller: true
+
+ ranges: true
+
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - ingenic,jz4740-tcu
+ - ingenic,jz4725b-tcu
+ - ingenic,jz4770-tcu
+ - ingenic,x1000-tcu
+ - const: simple-mfd
+ - items:
+ - const: ingenic,jz4780-tcu
+ - const: ingenic,jz4770-tcu
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: RTC clock
+ - description: EXT clock
+ - description: PCLK clock
+ - description: TCU clock
+ minItems: 3
+
+ clock-names:
+ items:
+ - const: rtc
+ - const: ext
+ - const: pclk
+ - const: tcu
+ minItems: 3
+
+ interrupts:
+ items:
+ - description: TCU0 interrupt
+ - description: TCU1 interrupt
+ - description: TCU2 interrupt
+ minItems: 1
+
+ assigned-clocks:
+ minItems: 1
+ maxItems: 8
+
+ assigned-clock-parents:
+ minItems: 1
+ maxItems: 8
+
+ assigned-clock-rates:
+ minItems: 1
+ maxItems: 8
+
+ ingenic,pwm-channels-mask:
+ description: Bitmask of TCU channels reserved for PWM use.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0x00
+ maximum: 0xff
+ default: 0xfc
+
+patternProperties:
+ "^watchdog@[a-f0-9]+$":
+ type: object
+ $ref: ../watchdog/watchdog.yaml#
+ properties:
+ compatible:
+ oneOf:
+ - enum:
+ - ingenic,jz4740-watchdog
+ - ingenic,jz4780-watchdog
+ - items:
+ - const: ingenic,jz4770-watchdog
+ - const: ingenic,jz4740-watchdog
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: wdt
+
+ required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+ "^pwm@[a-f0-9]+$":
+ type: object
+ $ref: ../pwm/pwm.yaml#
+ properties:
+ compatible:
+ oneOf:
+ - enum:
+ - ingenic,jz4740-pwm
+ - items:
+ - enum:
+ - ingenic,jz4770-pwm
+ - ingenic,jz4780-pwm
+ - const: ingenic,jz4740-pwm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 6
+ maxItems: 8
+
+ clock-names:
+ items:
+ - const: timer0
+ - const: timer1
+ - const: timer2
+ - const: timer3
+ - const: timer4
+ - const: timer5
+ - const: timer6
+ - const: timer7
+ minItems: 6
+
+ required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+ "^timer@[a-f0-9]+$":
+ type: object
+ properties:
+ compatible:
+ oneOf:
+ - enum:
+ - ingenic,jz4725b-ost
+ - ingenic,jz4770-ost
+ - items:
+ - const: ingenic,jz4780-ost
+ - const: ingenic,jz4770-ost
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ost
+
+ interrupts:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+ additionalProperties: false
+
+required:
+ - "#clock-cells"
+ - "#interrupt-cells"
+ - interrupt-controller
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4770-cgu.h>
+ #include <dt-bindings/clock/ingenic,tcu.h>
+ tcu: timer@10002000 {
+ compatible = "ingenic,jz4770-tcu", "simple-mfd";
+ reg = <0x10002000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10002000 0x1000>;
+
+ #clock-cells = <1>;
+
+ clocks = <&cgu JZ4770_CLK_RTC>,
+ <&cgu JZ4770_CLK_EXT>,
+ <&cgu JZ4770_CLK_PCLK>;
+ clock-names = "rtc", "ext", "pclk";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <27 26 25>;
+
+ watchdog: watchdog@0 {
+ compatible = "ingenic,jz4770-watchdog", "ingenic,jz4740-watchdog";
+ reg = <0x0 0xc>;
+
+ clocks = <&tcu TCU_CLK_WDT>;
+ clock-names = "wdt";
+ };
+
+ pwm: pwm@40 {
+ compatible = "ingenic,jz4770-pwm", "ingenic,jz4740-pwm";
+ reg = <0x40 0x80>;
+
+ #pwm-cells = <3>;
+
+ clocks = <&tcu TCU_CLK_TIMER0>,
+ <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_TIMER2>,
+ <&tcu TCU_CLK_TIMER3>,
+ <&tcu TCU_CLK_TIMER4>,
+ <&tcu TCU_CLK_TIMER5>,
+ <&tcu TCU_CLK_TIMER6>,
+ <&tcu TCU_CLK_TIMER7>;
+ clock-names = "timer0", "timer1", "timer2", "timer3",
+ "timer4", "timer5", "timer6", "timer7";
+ };
+
+ ost: timer@e0 {
+ compatible = "ingenic,jz4770-ost";
+ reg = <0xe0 0x20>;
+
+ clocks = <&tcu TCU_CLK_OST>;
+ clock-names = "ost";
+
+ interrupts = <15>;
+ };
+ };
diff --git a/dts/Bindings/timer/nxp,sysctr-timer.txt b/dts/Bindings/timer/nxp,sysctr-timer.txt
deleted file mode 100644
index d57659996d..0000000000
--- a/dts/Bindings/timer/nxp,sysctr-timer.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-NXP System Counter Module(sys_ctr)
-
-The system counter(sys_ctr) is a programmable system counter which provides
-a shared time base to Cortex A15, A7, A53, A73, etc. it is intended for use in
-applications where the counter is always powered and support multiple,
-unrelated clocks. The compare frame inside can be used for timer purpose.
-
-Required properties:
-
-- compatible : should be "nxp,sysctr-timer"
-- reg : Specifies the base physical address and size of the comapre
- frame and the counter control, read & compare.
-- interrupts : should be the first compare frames' interrupt
-- clocks : Specifies the counter clock.
-- clock-names: Specifies the clock's name of this module
-
-Example:
-
- system_counter: timer@306a0000 {
- compatible = "nxp,sysctr-timer";
- reg = <0x306a0000 0x20000>;/* system-counter-rd & compare */
- clocks = <&clk_8m>;
- clock-names = "per";
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- };
diff --git a/dts/Bindings/timer/nxp,sysctr-timer.yaml b/dts/Bindings/timer/nxp,sysctr-timer.yaml
new file mode 100644
index 0000000000..830211c55b
--- /dev/null
+++ b/dts/Bindings/timer/nxp,sysctr-timer.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP System Counter Module(sys_ctr)
+
+maintainers:
+ - Bai Ping <ping.bai@nxp.com>
+
+description: |
+ The system counter(sys_ctr) is a programmable system counter
+ which provides a shared time base to Cortex A15, A7, A53, A73,
+ etc. it is intended for use in applications where the counter
+ is always powered and support multiple, unrelated clocks. The
+ compare frame inside can be used for timer purpose.
+
+properties:
+ compatible:
+ const: nxp,sysctr-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: per
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ timer@306a0000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a0000 0x20000>;
+ clocks = <&clk_8m>;
+ clock-names = "per";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/Bindings/timer/nxp,tpm-timer.txt b/dts/Bindings/timer/nxp,tpm-timer.txt
deleted file mode 100644
index f82087b220..0000000000
--- a/dts/Bindings/timer/nxp,tpm-timer.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-NXP Low Power Timer/Pulse Width Modulation Module (TPM)
-
-The Timer/PWM Module (TPM) supports input capture, output compare,
-and the generation of PWM signals to control electric motor and power
-management applications. The counter, compare and capture registers
-are clocked by an asynchronous clock that can remain enabled in low
-power modes. TPM can support global counter bus where one TPM drives
-the counter bus for the others, provided bit width is the same.
-
-Required properties:
-
-- compatible : should be "fsl,imx7ulp-tpm"
-- reg : Specifies base physical address and size of the register sets
- for the clock event device and clock source device.
-- interrupts : Should be the clock event device interrupt.
-- clocks : The clocks provided by the SoC to drive the timer, must contain
- an entry for each entry in clock-names.
-- clock-names : Must include the following entries: "ipg" and "per".
-
-Example:
-tpm5: tpm@40260000 {
- compatible = "fsl,imx7ulp-tpm";
- reg = <0x40260000 0x1000>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&clks IMX7ULP_CLK_LPTPM5>;
- clock-names = "ipg", "per";
-};
diff --git a/dts/Bindings/timer/nxp,tpm-timer.yaml b/dts/Bindings/timer/nxp,tpm-timer.yaml
new file mode 100644
index 0000000000..edd9585f67
--- /dev/null
+++ b/dts/Bindings/timer/nxp,tpm-timer.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Low Power Timer/Pulse Width Modulation Module (TPM)
+
+maintainers:
+ - Dong Aisheng <aisheng.dong@nxp.com>
+
+description: |
+ The Timer/PWM Module (TPM) supports input capture, output compare,
+ and the generation of PWM signals to control electric motor and power
+ management applications. The counter, compare and capture registers
+ are clocked by an asynchronous clock that can remain enabled in low
+ power modes. TPM can support global counter bus where one TPM drives
+ the counter bus for the others, provided bit width is the same.
+
+properties:
+ compatible:
+ const: fsl,imx7ulp-tpm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: SoC TPM ipg clock
+ - description: SoC TPM per clock
+
+ clock-names:
+ items:
+ - const: ipg
+ - const: per
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx7ulp-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ timer@40260000 {
+ compatible = "fsl,imx7ulp-tpm";
+ reg = <0x40260000 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&pcc2 IMX7ULP_CLK_LPTPM5>;
+ clock-names = "ipg", "per";
+ };
diff --git a/dts/Bindings/timer/renesas,cmt.txt b/dts/Bindings/timer/renesas,cmt.txt
deleted file mode 100644
index a747fabab7..0000000000
--- a/dts/Bindings/timer/renesas,cmt.txt
+++ /dev/null
@@ -1,110 +0,0 @@
-* Renesas R-Car Compare Match Timer (CMT)
-
-The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
-inputs and programmable compare match.
-
-Channels share hardware resources but their counter and compare match value
-are independent. A particular CMT instance can implement only a subset of the
-channels supported by the CMT model. Channel indices represent the hardware
-position of the channel in the CMT and don't match the channel numbers in the
-datasheets.
-
-Required Properties:
-
- - compatible: must contain one or more of the following:
- - "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4.
- - "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4.
- - "renesas,r8a7740-cmt0" for the 32-bit CMT0 device included in r8a7740.
- - "renesas,r8a7740-cmt1" for the 48-bit CMT1 device included in r8a7740.
- - "renesas,r8a7740-cmt2" for the 32-bit CMT2 device included in r8a7740.
- - "renesas,r8a7740-cmt3" for the 32-bit CMT3 device included in r8a7740.
- - "renesas,r8a7740-cmt4" for the 32-bit CMT4 device included in r8a7740.
- - "renesas,r8a7743-cmt0" for the 32-bit CMT0 device included in r8a7743.
- - "renesas,r8a7743-cmt1" for the 48-bit CMT1 device included in r8a7743.
- - "renesas,r8a7744-cmt0" for the 32-bit CMT0 device included in r8a7744.
- - "renesas,r8a7744-cmt1" for the 48-bit CMT1 device included in r8a7744.
- - "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745.
- - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745.
- - "renesas,r8a77470-cmt0" for the 32-bit CMT0 device included in r8a77470.
- - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470.
- - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1.
- - "renesas,r8a774a1-cmt1" for the 48-bit CMT devices included in r8a774a1.
- - "renesas,r8a774b1-cmt0" for the 32-bit CMT0 device included in r8a774b1.
- - "renesas,r8a774b1-cmt1" for the 48-bit CMT devices included in r8a774b1.
- - "renesas,r8a774c0-cmt0" for the 32-bit CMT0 device included in r8a774c0.
- - "renesas,r8a774c0-cmt1" for the 48-bit CMT devices included in r8a774c0.
- - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790.
- - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790.
- - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791.
- - "renesas,r8a7791-cmt1" for the 48-bit CMT1 device included in r8a7791.
- - "renesas,r8a7792-cmt0" for the 32-bit CMT0 device included in r8a7792.
- - "renesas,r8a7792-cmt1" for the 48-bit CMT1 device included in r8a7792.
- - "renesas,r8a7793-cmt0" for the 32-bit CMT0 device included in r8a7793.
- - "renesas,r8a7793-cmt1" for the 48-bit CMT1 device included in r8a7793.
- - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794.
- - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794.
- - "renesas,r8a7795-cmt0" for the 32-bit CMT0 device included in r8a7795.
- - "renesas,r8a7795-cmt1" for the 48-bit CMT devices included in r8a7795.
- - "renesas,r8a7796-cmt0" for the 32-bit CMT0 device included in r8a7796.
- - "renesas,r8a7796-cmt1" for the 48-bit CMT devices included in r8a7796.
- - "renesas,r8a77965-cmt0" for the 32-bit CMT0 device included in r8a77965.
- - "renesas,r8a77965-cmt1" for the 48-bit CMT devices included in r8a77965.
- - "renesas,r8a77970-cmt0" for the 32-bit CMT0 device included in r8a77970.
- - "renesas,r8a77970-cmt1" for the 48-bit CMT devices included in r8a77970.
- - "renesas,r8a77980-cmt0" for the 32-bit CMT0 device included in r8a77980.
- - "renesas,r8a77980-cmt1" for the 48-bit CMT devices included in r8a77980.
- - "renesas,r8a77990-cmt0" for the 32-bit CMT0 device included in r8a77990.
- - "renesas,r8a77990-cmt1" for the 48-bit CMT devices included in r8a77990.
- - "renesas,r8a77995-cmt0" for the 32-bit CMT0 device included in r8a77995.
- - "renesas,r8a77995-cmt1" for the 48-bit CMT devices included in r8a77995.
- - "renesas,sh73a0-cmt0" for the 32-bit CMT0 device included in sh73a0.
- - "renesas,sh73a0-cmt1" for the 48-bit CMT1 device included in sh73a0.
- - "renesas,sh73a0-cmt2" for the 32-bit CMT2 device included in sh73a0.
- - "renesas,sh73a0-cmt3" for the 32-bit CMT3 device included in sh73a0.
- - "renesas,sh73a0-cmt4" for the 32-bit CMT4 device included in sh73a0.
-
- - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2
- and RZ/G1.
- - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2
- and RZ/G1.
- These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries
- listed above.
- - "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3
- and RZ/G2.
- - "renesas,rcar-gen3-cmt1" for 48-bit CMT devices included in R-Car Gen3
- and RZ/G2.
- These are fallbacks for R-Car Gen3 and RZ/G2 entries listed
- above.
-
- - reg: base address and length of the registers block for the timer module.
- - interrupts: interrupt-specifier for the timer, one per channel.
- - clocks: a list of phandle + clock-specifier pairs, one for each entry
- in clock-names.
- - clock-names: must contain "fck" for the functional clock.
-
-
-Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes
-
- cmt0: timer@ffca0000 {
- compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
- reg = <0 0xffca0000 0 0x1004>;
- interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
- <0 142 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
- clock-names = "fck";
- };
-
- cmt1: timer@e6130000 {
- compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
- reg = <0 0xe6130000 0 0x1004>;
- interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
- <0 121 IRQ_TYPE_LEVEL_HIGH>,
- <0 122 IRQ_TYPE_LEVEL_HIGH>,
- <0 123 IRQ_TYPE_LEVEL_HIGH>,
- <0 124 IRQ_TYPE_LEVEL_HIGH>,
- <0 125 IRQ_TYPE_LEVEL_HIGH>,
- <0 126 IRQ_TYPE_LEVEL_HIGH>,
- <0 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
- clock-names = "fck";
- };
diff --git a/dts/Bindings/timer/renesas,cmt.yaml b/dts/Bindings/timer/renesas,cmt.yaml
new file mode 100644
index 0000000000..7e4dc5623d
--- /dev/null
+++ b/dts/Bindings/timer/renesas,cmt.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/renesas,cmt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Compare Match Timer (CMT)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description:
+ The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
+ inputs and programmable compare match.
+
+ Channels share hardware resources but their counter and compare match values
+ are independent. A particular CMT instance can implement only a subset of the
+ channels supported by the CMT model. Channel indices represent the hardware
+ position of the channel in the CMT and don't match the channel numbers in the
+ datasheets.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
+ - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
+ - renesas,r8a7740-cmt2 # 32-bit CMT2 on R-Mobile A1
+ - renesas,r8a7740-cmt3 # 32-bit CMT3 on R-Mobile A1
+ - renesas,r8a7740-cmt4 # 32-bit CMT4 on R-Mobile A1
+ - renesas,sh73a0-cmt0 # 32-bit CMT0 on SH-Mobile AG5
+ - renesas,sh73a0-cmt1 # 48-bit CMT1 on SH-Mobile AG5
+ - renesas,sh73a0-cmt2 # 32-bit CMT2 on SH-Mobile AG5
+ - renesas,sh73a0-cmt3 # 32-bit CMT3 on SH-Mobile AG5
+ - renesas,sh73a0-cmt4 # 32-bit CMT4 on SH-Mobile AG5
+
+ - items:
+ - enum:
+ - renesas,r8a73a4-cmt0 # 32-bit CMT0 on R-Mobile APE6
+ - renesas,r8a7743-cmt0 # 32-bit CMT0 on RZ/G1M
+ - renesas,r8a7744-cmt0 # 32-bit CMT0 on RZ/G1N
+ - renesas,r8a7745-cmt0 # 32-bit CMT0 on RZ/G1E
+ - renesas,r8a77470-cmt0 # 32-bit CMT0 on RZ/G1C
+ - renesas,r8a7790-cmt0 # 32-bit CMT0 on R-Car H2
+ - renesas,r8a7791-cmt0 # 32-bit CMT0 on R-Car M2-W
+ - renesas,r8a7792-cmt0 # 32-bit CMT0 on R-Car V2H
+ - renesas,r8a7793-cmt0 # 32-bit CMT0 on R-Car M2-N
+ - renesas,r8a7794-cmt0 # 32-bit CMT0 on R-Car E2
+ - const: renesas,rcar-gen2-cmt0 # 32-bit CMT0 on R-Mobile APE6, R-Car Gen2 and RZ/G1
+
+ - items:
+ - enum:
+ - renesas,r8a73a4-cmt1 # 48-bit CMT1 on R-Mobile APE6
+ - renesas,r8a7743-cmt1 # 48-bit CMT1 on RZ/G1M
+ - renesas,r8a7744-cmt1 # 48-bit CMT1 on RZ/G1N
+ - renesas,r8a7745-cmt1 # 48-bit CMT1 on RZ/G1E
+ - renesas,r8a77470-cmt1 # 48-bit CMT1 on RZ/G1C
+ - renesas,r8a7790-cmt1 # 48-bit CMT1 on R-Car H2
+ - renesas,r8a7791-cmt1 # 48-bit CMT1 on R-Car M2-W
+ - renesas,r8a7792-cmt1 # 48-bit CMT1 on R-Car V2H
+ - renesas,r8a7793-cmt1 # 48-bit CMT1 on R-Car M2-N
+ - renesas,r8a7794-cmt1 # 48-bit CMT1 on R-Car E2
+ - const: renesas,rcar-gen2-cmt1 # 48-bit CMT1 on R-Mobile APE6, R-Car Gen2 and RZ/G1
+
+ - items:
+ - enum:
+ - renesas,r8a774a1-cmt0 # 32-bit CMT0 on RZ/G2M
+ - renesas,r8a774b1-cmt0 # 32-bit CMT0 on RZ/G2N
+ - renesas,r8a774c0-cmt0 # 32-bit CMT0 on RZ/G2E
+ - renesas,r8a7795-cmt0 # 32-bit CMT0 on R-Car H3
+ - renesas,r8a7796-cmt0 # 32-bit CMT0 on R-Car M3-W
+ - renesas,r8a77965-cmt0 # 32-bit CMT0 on R-Car M3-N
+ - renesas,r8a77970-cmt0 # 32-bit CMT0 on R-Car V3M
+ - renesas,r8a77980-cmt0 # 32-bit CMT0 on R-Car V3H
+ - renesas,r8a77990-cmt0 # 32-bit CMT0 on R-Car E3
+ - renesas,r8a77995-cmt0 # 32-bit CMT0 on R-Car D3
+ - const: renesas,rcar-gen3-cmt0 # 32-bit CMT0 on R-Car Gen3 and RZ/G2
+
+ - items:
+ - enum:
+ - renesas,r8a774a1-cmt1 # 48-bit CMT on RZ/G2M
+ - renesas,r8a774b1-cmt1 # 48-bit CMT on RZ/G2N
+ - renesas,r8a774c0-cmt1 # 48-bit CMT on RZ/G2E
+ - renesas,r8a7795-cmt1 # 48-bit CMT on R-Car H3
+ - renesas,r8a7796-cmt1 # 48-bit CMT on R-Car M3-W
+ - renesas,r8a77965-cmt1 # 48-bit CMT on R-Car M3-N
+ - renesas,r8a77970-cmt1 # 48-bit CMT on R-Car V3M
+ - renesas,r8a77980-cmt1 # 48-bit CMT on R-Car V3H
+ - renesas,r8a77990-cmt1 # 48-bit CMT on R-Car E3
+ - renesas,r8a77995-cmt1 # 48-bit CMT on R-Car D3
+ - const: renesas,rcar-gen3-cmt1 # 48-bit CMT on R-Car Gen3 and RZ/G2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 8
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: fck
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-cmt0
+ - renesas,rcar-gen3-cmt0
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-cmt1
+ - renesas,rcar-gen3-cmt1
+ then:
+ properties:
+ interrupts:
+ minItems: 8
+ maxItems: 8
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7790-sysc.h>
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
+ reg = <0xffca0000 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
+ reg = <0xe6130000 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+ };
diff --git a/dts/Bindings/timer/renesas,em-sti.yaml b/dts/Bindings/timer/renesas,em-sti.yaml
new file mode 100644
index 0000000000..233d74d540
--- /dev/null
+++ b/dts/Bindings/timer/renesas,em-sti.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/renesas,em-sti.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas EMMA Mobile System Timer
+
+maintainers:
+ - Magnus Damm <magnus.damm@gmail.com>
+
+properties:
+ compatible:
+ const: renesas,em-sti
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: sclk
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ timer@e0180000 {
+ compatible = "renesas,em-sti";
+ reg = <0xe0180000 0x54>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sti_sclk>;
+ clock-names = "sclk";
+ };
diff --git a/dts/Bindings/timer/renesas,mtu2.txt b/dts/Bindings/timer/renesas,mtu2.txt
deleted file mode 100644
index ba0a34d97e..0000000000
--- a/dts/Bindings/timer/renesas,mtu2.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-* Renesas Multi-Function Timer Pulse Unit 2 (MTU2)
-
-The MTU2 is a multi-purpose, multi-channel timer/counter with configurable
-clock inputs and programmable compare match.
-
-Channels share hardware resources but their counter and compare match value
-are independent. The MTU2 hardware supports five channels indexed from 0 to 4.
-
-Required Properties:
-
- - compatible: must be one or more of the following:
- - "renesas,mtu2-r7s72100" for the r7s72100 MTU2
- - "renesas,mtu2" for any MTU2
- This is a fallback for the above renesas,mtu2-* entries
-
- - reg: base address and length of the registers block for the timer module.
-
- - interrupts: interrupt specifiers for the timer, one for each entry in
- interrupt-names.
- - interrupt-names: must contain one entry named "tgi?a" for each enabled
- channel, where "?" is the channel index expressed as one digit from "0" to
- "4".
-
- - clocks: a list of phandle + clock-specifier pairs, one for each entry
- in clock-names.
- - clock-names: must contain "fck" for the functional clock.
-
-
-Example: R7S72100 (RZ/A1H) MTU2 node
-
- mtu2: timer@fcff0000 {
- compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
- reg = <0xfcff0000 0x400>;
- interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>,
- <0 146 IRQ_TYPE_LEVEL_HIGH>,
- <0 150 IRQ_TYPE_LEVEL_HIGH>,
- <0 154 IRQ_TYPE_LEVEL_HIGH>,
- <0 159 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tgi0a", "tgi1a", "tgi2a", "tgi3a", "tgi4a";
- clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
- clock-names = "fck";
- };
diff --git a/dts/Bindings/timer/renesas,mtu2.yaml b/dts/Bindings/timer/renesas,mtu2.yaml
new file mode 100644
index 0000000000..15d8dddf4a
--- /dev/null
+++ b/dts/Bindings/timer/renesas,mtu2.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/renesas,mtu2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Multi-Function Timer Pulse Unit 2 (MTU2)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description:
+ The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs
+ and programmable compare match.
+
+ Channels share hardware resources but their counter and compare match value are
+ independent. The MTU2 hardware supports five channels indexed from 0 to 4.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,mtu2-r7s72100 # RZ/A1H
+ - const: renesas,mtu2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 5
+ description: One entry for each enabled channel.
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: tgi0a
+ - const: tgi1a
+ - const: tgi2a
+ - const: tgi3a
+ - const: tgi4a
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: fck
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r7s72100-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ mtu2: timer@fcff0000 {
+ compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
+ reg = <0xfcff0000 0x400>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tgi0a";
+ clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ };
diff --git a/dts/Bindings/timer/renesas,ostm.txt b/dts/Bindings/timer/renesas,ostm.txt
deleted file mode 100644
index 81a78f8bcf..0000000000
--- a/dts/Bindings/timer/renesas,ostm.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* Renesas OS Timer (OSTM)
-
-The OSTM is a multi-channel 32-bit timer/counter with fixed clock
-source that can operate in either interval count down timer or free-running
-compare match mode.
-
-Channels are independent from each other.
-
-Required Properties:
-
- - compatible: must be one or more of the following:
- - "renesas,r7s72100-ostm" for the R7S72100 (RZ/A1) OSTM
- - "renesas,r7s9210-ostm" for the R7S9210 (RZ/A2) OSTM
- - "renesas,ostm" for any OSTM
- This is a fallback for the above renesas,*-ostm entries
-
- - reg: base address and length of the register block for a timer channel.
-
- - interrupts: interrupt specifier for the timer channel.
-
- - clocks: clock specifier for the timer channel.
-
-Example: R7S72100 (RZ/A1H) OSTM node
-
- ostm0: timer@fcfec000 {
- compatible = "renesas,r7s72100-ostm", "renesas,ostm";
- reg = <0xfcfec000 0x30>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
- clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
- power-domains = <&cpg_clocks>;
- };
diff --git a/dts/Bindings/timer/renesas,ostm.yaml b/dts/Bindings/timer/renesas,ostm.yaml
new file mode 100644
index 0000000000..600d47ab7d
--- /dev/null
+++ b/dts/Bindings/timer/renesas,ostm.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/renesas,ostm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas OS Timer (OSTM)
+
+maintainers:
+ - Chris Brandt <chris.brandt@renesas.com>
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The OSTM is a multi-channel 32-bit timer/counter with fixed clock source that
+ can operate in either interval count down timer or free-running compare match
+ mode.
+
+ Channels are independent from each other.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r7s72100-ostm # RZ/A1H
+ - renesas,r7s9210-ostm # RZ/A2M
+ - const: renesas,ostm # Generic
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r7s72100-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ ostm0: timer@fcfec000 {
+ compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+ reg = <0xfcfec000 0x30>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
+ power-domains = <&cpg_clocks>;
+ };
diff --git a/dts/Bindings/timer/snps,dw-apb-timer.yaml b/dts/Bindings/timer/snps,dw-apb-timer.yaml
new file mode 100644
index 0000000000..5d300efdf0
--- /dev/null
+++ b/dts/Bindings/timer/snps,dw-apb-timer.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare APB Timer
+
+maintainers:
+ - Daniel Lezcano <daniel.lezcano@linaro.org>
+
+properties:
+ compatible:
+ oneOf:
+ - const: snps,dw-apb-timer
+ - enum:
+ - snps,dw-apb-timer-sp
+ - snps,dw-apb-timer-osc
+ deprecated: true
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: Timer ticks reference clock source
+ - description: APB interface clock source
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: timer
+ - const: pclk
+
+ clock-frequency: true
+
+ clock-freq:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ description: |
+ Has the same meaning as the 'clock-frequency' property - timer clock
+ frequency in HZ, but is defined only for the backwards compatibility
+ with the picoxcell platform.
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+oneOf:
+ - required:
+ - clocks
+ - clock-names
+ - required:
+ - clock-frequency
+ - required:
+ - clock-freq
+
+examples:
+ - |
+ timer@ffe00000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 170 4>;
+ reg = <0xffe00000 0x1000>;
+ clocks = <&timer_clk>, <&timer_pclk>;
+ clock-names = "timer", "pclk";
+ };
+ - |
+ timer@ffe00000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 170 4>;
+ reg = <0xffe00000 0x1000>;
+ clocks = <&timer_clk>;
+ clock-names = "timer";
+ };
+ - |
+ timer@ffe00000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 170 4>;
+ reg = <0xffe00000 0x1000>;
+ clock-frequency = <25000000>;
+ };
+...
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 21:56:54 +0000