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-rw-r--r--dts/Bindings/ufs/cdns,ufshc.yaml2
-rw-r--r--dts/Bindings/ufs/qcom,ufs.yaml116
-rw-r--r--dts/Bindings/ufs/renesas,ufs.yaml61
-rw-r--r--dts/Bindings/ufs/samsung,exynos-ufs.yaml14
-rw-r--r--dts/Bindings/ufs/sprd,ums9620-ufs.yaml79
-rw-r--r--dts/Bindings/ufs/ufs-common.yaml39
6 files changed, 300 insertions, 11 deletions
diff --git a/dts/Bindings/ufs/cdns,ufshc.yaml b/dts/Bindings/ufs/cdns,ufshc.yaml
index fb45f66d64..835e17269d 100644
--- a/dts/Bindings/ufs/cdns,ufshc.yaml
+++ b/dts/Bindings/ufs/cdns,ufshc.yaml
@@ -49,6 +49,8 @@ properties:
reg:
maxItems: 1
+ dma-coherent: true
+
required:
- compatible
- clocks
diff --git a/dts/Bindings/ufs/qcom,ufs.yaml b/dts/Bindings/ufs/qcom,ufs.yaml
index dcd32c1020..cd3680dc00 100644
--- a/dts/Bindings/ufs/qcom,ufs.yaml
+++ b/dts/Bindings/ufs/qcom,ufs.yaml
@@ -26,23 +26,34 @@ properties:
- qcom,msm8994-ufshc
- qcom,msm8996-ufshc
- qcom,msm8998-ufshc
+ - qcom,sa8775p-ufshc
+ - qcom,sc7180-ufshc
+ - qcom,sc7280-ufshc
+ - qcom,sc8180x-ufshc
+ - qcom,sc8280xp-ufshc
- qcom,sdm845-ufshc
+ - qcom,sm6115-ufshc
+ - qcom,sm6125-ufshc
- qcom,sm6350-ufshc
- qcom,sm8150-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
- qcom,sm8450-ufshc
+ - qcom,sm8550-ufshc
+ - qcom,sm8650-ufshc
- const: qcom,ufshc
- const: jedec,ufs-2.0
clocks:
- minItems: 8
+ minItems: 7
maxItems: 11
clock-names:
- minItems: 8
+ minItems: 7
maxItems: 11
+ dma-coherent: true
+
interconnects:
minItems: 2
maxItems: 2
@@ -66,10 +77,22 @@ properties:
power-domains:
maxItems: 1
+ qcom,ice:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the Inline Crypto Engine node
+
reg:
minItems: 1
maxItems: 2
+ reg-names:
+ items:
+ - const: std
+ - const: ice
+
+ required-opps:
+ maxItems: 1
+
resets:
maxItems: 1
@@ -97,10 +120,41 @@ allOf:
compatible:
contains:
enum:
+ - qcom,sc7180-ufshc
+ then:
+ properties:
+ clocks:
+ minItems: 7
+ maxItems: 7
+ clock-names:
+ items:
+ - const: core_clk
+ - const: bus_aggr_clk
+ - const: iface_clk
+ - const: core_clk_unipro
+ - const: ref_clk
+ - const: tx_lane0_sync_clk
+ - const: rx_lane0_sync_clk
+ reg:
+ maxItems: 1
+ reg-names:
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,msm8998-ufshc
+ - qcom,sa8775p-ufshc
+ - qcom,sc7280-ufshc
+ - qcom,sc8180x-ufshc
+ - qcom,sc8280xp-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
- qcom,sm8450-ufshc
+ - qcom,sm8550-ufshc
+ - qcom,sm8650-ufshc
then:
properties:
clocks:
@@ -119,6 +173,8 @@ allOf:
reg:
minItems: 1
maxItems: 1
+ reg-names:
+ maxItems: 1
- if:
properties:
@@ -147,6 +203,10 @@ allOf:
reg:
minItems: 2
maxItems: 2
+ reg-names:
+ minItems: 2
+ required:
+ - reg-names
- if:
properties:
@@ -175,9 +235,60 @@ allOf:
reg:
minItems: 1
maxItems: 1
+ reg-names:
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm6115-ufshc
+ - qcom,sm6125-ufshc
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: core_clk
+ - const: bus_aggr_clk
+ - const: iface_clk
+ - const: core_clk_unipro
+ - const: ref_clk
+ - const: tx_lane0_sync_clk
+ - const: rx_lane0_sync_clk
+ - const: ice_core_clk
+ reg:
+ minItems: 2
+ maxItems: 2
+ reg-names:
+ minItems: 2
+ required:
+ - reg-names
# TODO: define clock bindings for qcom,msm8994-ufshc
+ - if:
+ required:
+ - qcom,ice
+ then:
+ properties:
+ reg:
+ maxItems: 1
+ clocks:
+ minItems: 7
+ maxItems: 8
+ else:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 2
+ clocks:
+ minItems: 7
+ maxItems: 11
+
unevaluatedProperties: false
examples:
@@ -240,5 +351,6 @@ examples:
<0 0>,
<0 0>,
<0 0>;
+ qcom,ice = <&ice>;
};
};
diff --git a/dts/Bindings/ufs/renesas,ufs.yaml b/dts/Bindings/ufs/renesas,ufs.yaml
new file mode 100644
index 0000000000..f04f9f61fa
--- /dev/null
+++ b/dts/Bindings/ufs/renesas,ufs.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/renesas,ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car UFS Host Controller
+
+maintainers:
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+allOf:
+ - $ref: ufs-common.yaml
+
+properties:
+ compatible:
+ const: renesas,r8a779f0-ufs
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: fck
+ - const: ref_clk
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a779f0-sysc.h>
+
+ ufs: ufs@e686000 {
+ compatible = "renesas,r8a779f0-ufs";
+ reg = <0xe6860000 0x100>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
+ clock-names = "fck", "ref_clk";
+ freq-table-hz = <200000000 200000000>, <38400000 38400000>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1514>;
+ };
diff --git a/dts/Bindings/ufs/samsung,exynos-ufs.yaml b/dts/Bindings/ufs/samsung,exynos-ufs.yaml
index c949eb6173..b2b509b394 100644
--- a/dts/Bindings/ufs/samsung,exynos-ufs.yaml
+++ b/dts/Bindings/ufs/samsung,exynos-ufs.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Samsung SoC series UFS host controller Device Tree Bindings
+title: Samsung SoC series UFS host controller
maintainers:
- Alim Akhtar <alim.akhtar@samsung.com>
@@ -21,6 +21,7 @@ properties:
- samsung,exynos7-ufs
- samsung,exynosautov9-ufs
- samsung,exynosautov9-ufs-vh
+ - tesla,fsd-ufs
reg:
items:
@@ -53,10 +54,13 @@ properties:
const: ufs-phy
samsung,sysreg:
- $ref: '/schemas/types.yaml#/definitions/phandle-array'
- description: Should be phandle/offset pair. The phandle to the syscon node
- which indicates the FSYSx sysreg interface and the offset of
- the control register for UFS io coherency setting.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to FSYSx sysreg node
+ - description: offset of the control register for UFS io coherency setting
+ description:
+ Phandle and offset to the FSYSx sysreg for UFS io coherency setting.
dma-coherent: true
diff --git a/dts/Bindings/ufs/sprd,ums9620-ufs.yaml b/dts/Bindings/ufs/sprd,ums9620-ufs.yaml
new file mode 100644
index 0000000000..36a8ae7794
--- /dev/null
+++ b/dts/Bindings/ufs/sprd,ums9620-ufs.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/sprd,ums9620-ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc Universal Flash Storage (UFS) Controller
+
+maintainers:
+ - Zhe Wang <zhe.wang1@unisoc.com>
+
+allOf:
+ - $ref: ufs-common.yaml
+
+properties:
+ compatible:
+ const: sprd,ums9620-ufs
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: controller_eb
+ - const: cfg_eb
+ - const: core
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: controller
+ - const: device
+
+ vdd-mphy-supply:
+ description:
+ Phandle to vdd-mphy supply regulator node.
+
+ sprd,ufs-anlg-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle of syscon used to control ufs analog regs.
+
+ sprd,aon-apb-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle of syscon used to control always-on regs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ ufs: ufs@22000000 {
+ compatible = "sprd,ums9620-ufs";
+ reg = <0x22000000 0x3000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ vcc-supply = <&vddemmccore>;
+ vdd-mphy-supply = <&vddufs1v2>;
+ clocks = <&apahb_gate 5>, <&apahb_gate 22>, <&aonapb_clk 52>;
+ clock-names = "controller_eb", "cfg_eb", "core";
+ assigned-clocks = <&aonapb_clk 52>;
+ assigned-clock-parents = <&g5l_pll 12>;
+ resets = <&apahb_gate 4>, <&aonapb_gate 69>;
+ reset-names = "controller", "device";
+ sprd,ufs-anlg-syscon = <&anlg_phy_g12_regs>;
+ sprd,aon-apb-syscon = <&aon_apb_regs>;
+ };
diff --git a/dts/Bindings/ufs/ufs-common.yaml b/dts/Bindings/ufs/ufs-common.yaml
index 47a4e9e1a7..31fe7f30ff 100644
--- a/dts/Bindings/ufs/ufs-common.yaml
+++ b/dts/Bindings/ufs/ufs-common.yaml
@@ -20,11 +20,25 @@ properties:
items:
- description: Minimum frequency for given clock in Hz
- description: Maximum frequency for given clock in Hz
+ deprecated: true
description: |
+ Preferred is operating-points-v2.
+
Array of <min max> operating frequencies in Hz stored in the same order
- as the clocks property. If this property is not defined or a value in the
- array is "0" then it is assumed that the frequency is set by the parent
- clock or a fixed rate clock source.
+ as the clocks property. If either this property or operating-points-v2 is
+ not defined or a value in the array is "0" then it is assumed that the
+ frequency is set by the parent clock or a fixed rate clock source.
+
+ operating-points-v2:
+ description:
+ Preferred over freq-table-hz.
+ If present, each OPP must contain array of frequencies stored in the same
+ order for each clock. If clock frequency in the array is "0" then it is
+ assumed that the frequency is set by the parent clock or a fixed rate
+ clock source.
+
+ opp-table:
+ type: object
interrupts:
maxItems: 1
@@ -73,10 +87,27 @@ properties:
description:
Specifies max. load that can be drawn from VCCQ2 supply.
+ msi-parent: true
+
dependencies:
- freq-table-hz: [ 'clocks' ]
+ freq-table-hz: [ clocks ]
+ operating-points-v2: [ clocks, clock-names ]
required:
- interrupts
+allOf:
+ - if:
+ required:
+ - freq-table-hz
+ then:
+ properties:
+ operating-points-v2: false
+ - if:
+ required:
+ - operating-points-v2
+ then:
+ properties:
+ freq-table-hz: false
+
additionalProperties: true
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-01 13:11:48 +0000