diff options
Diffstat (limited to 'dts/Bindings/usb')
| -rw-r--r-- | dts/Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml | 22 | ||||
| -rw-r--r-- | dts/Bindings/usb/atmel-usb.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/usb/cdns,usb3.yaml | 96 | ||||
| -rw-r--r-- | dts/Bindings/usb/cdns-usb3.txt | 45 | ||||
| -rw-r--r-- | dts/Bindings/usb/ci-hdrc-usb2.txt | 9 | ||||
| -rw-r--r-- | dts/Bindings/usb/dwc2.yaml | 5 | ||||
| -rw-r--r-- | dts/Bindings/usb/dwc3.txt | 3 | ||||
| -rw-r--r-- | dts/Bindings/usb/intel,keembay-dwc3.yaml | 77 | ||||
| -rw-r--r-- | dts/Bindings/usb/mediatek,mt6360-tcpc.yaml | 95 | ||||
| -rw-r--r-- | dts/Bindings/usb/nvidia,tegra-xudc.yaml | 2 | ||||
| -rw-r--r-- | dts/Bindings/usb/qcom,dwc3.yaml | 2 | ||||
| -rw-r--r-- | dts/Bindings/usb/renesas,usb-xhci.yaml | 1 | ||||
| -rw-r--r-- | dts/Bindings/usb/renesas,usb3-peri.yaml | 35 | ||||
| -rw-r--r-- | dts/Bindings/usb/renesas,usbhs.yaml | 1 | ||||
| -rw-r--r-- | dts/Bindings/usb/ti,hd3ss3220.txt | 38 | ||||
| -rw-r--r-- | dts/Bindings/usb/ti,hd3ss3220.yaml | 82 | ||||
| -rw-r--r-- | dts/Bindings/usb/ti,j721e-usb.yaml | 18 | ||||
| -rw-r--r-- | dts/Bindings/usb/ti,tps6598x.yaml | 2 | ||||
| -rw-r--r-- | dts/Bindings/usb/usb-hcd.yaml | 2 |
19 files changed, 447 insertions, 89 deletions
diff --git a/dts/Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/dts/Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml index 5b04a7dfa0..c0058332b9 100644 --- a/dts/Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml +++ b/dts/Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml @@ -25,13 +25,14 @@ description: | The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in host-only mode. - The Amlogic GXL & GXM SoCs doesn't embed an USB3 PHY. + The Amlogic GXL, GXM & AXG SoCs doesn't embed an USB3 PHY. properties: compatible: enum: - amlogic,meson-gxl-usb-ctrl - amlogic,meson-gxm-usb-ctrl + - amlogic,meson-axg-usb-ctrl - amlogic,meson-g12a-usb-ctrl - amlogic,meson-a1-usb-ctrl @@ -155,6 +156,25 @@ allOf: properties: compatible: enum: + - amlogic,meson-axg-usb-ctrl + + then: + properties: + phy-names: + items: + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used + clocks: + minItems: 2 + clock-names: + items: + - const: usb_ctrl + - const: ddr + required: + - clock-names + - if: + properties: + compatible: + enum: - amlogic,meson-a1-usb-ctrl then: diff --git a/dts/Bindings/usb/atmel-usb.txt b/dts/Bindings/usb/atmel-usb.txt index 423b99a8fd..a4002624ba 100644 --- a/dts/Bindings/usb/atmel-usb.txt +++ b/dts/Bindings/usb/atmel-usb.txt @@ -82,6 +82,7 @@ Required properties: "atmel,at91sam9rl-udc" "atmel,at91sam9g45-udc" "atmel,sama5d3-udc" + "microchip,sam9x60-udc" - reg: Address and length of the register set for the device - interrupts: Should contain usba interrupt - clocks: Should reference the peripheral and host clocks diff --git a/dts/Bindings/usb/cdns,usb3.yaml b/dts/Bindings/usb/cdns,usb3.yaml new file mode 100644 index 0000000000..ac20b98e99 --- /dev/null +++ b/dts/Bindings/usb/cdns,usb3.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cdns,usb3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence USBSS-DRD controller bindings + +maintainers: + - Pawel Laszczak <pawell@cadence.com> + +properties: + compatible: + const: cdns,usb3 + + reg: + items: + - description: OTG controller registers + - description: XHCI Host controller registers + - description: DEVICE controller registers + + reg-names: + items: + - const: otg + - const: xhci + - const: dev + + interrupts: + items: + - description: OTG/DRD controller interrupt + - description: XHCI host controller interrupt + - description: Device controller interrupt + + interrupt-names: + items: + - const: host + - const: peripheral + - const: otg + + dr_mode: + enum: [host, otg, peripheral] + + maximum-speed: + enum: [super-speed, high-speed, full-speed] + + phys: + minItems: 1 + maxItems: 2 + + phy-names: + minItems: 1 + maxItems: 2 + items: + anyOf: + - const: cdns3,usb2-phy + - const: cdns3,usb3-phy + + cdns,on-chip-buff-size: + description: + size of memory intended as internal memory for endpoints + buffers expressed in KB + $ref: /schemas/types.yaml#/definitions/uint32 + + cdns,phyrst-a-enable: + description: Enable resetting of PHY if Rx fail is detected + type: boolean + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + bus { + #address-cells = <2>; + #size-cells = <2>; + + usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host", "peripheral", "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; diff --git a/dts/Bindings/usb/cdns-usb3.txt b/dts/Bindings/usb/cdns-usb3.txt deleted file mode 100644 index b7dc606d37..0000000000 --- a/dts/Bindings/usb/cdns-usb3.txt +++ /dev/null @@ -1,45 +0,0 @@ -Binding for the Cadence USBSS-DRD controller - -Required properties: - - reg: Physical base address and size of the controller's register areas. - Controller has 3 different regions: - - HOST registers area - - DEVICE registers area - - OTG/DRD registers area - - reg-names - register memory area names: - "xhci" - for HOST registers space - "dev" - for DEVICE registers space - "otg" - for OTG/DRD registers space - - compatible: Should contain: "cdns,usb3" - - interrupts: Interrupts used by cdns3 controller: - "host" - interrupt used by XHCI driver. - "peripheral" - interrupt used by device driver - "otg" - interrupt used by DRD/OTG part of driver - -Optional properties: - - maximum-speed : valid arguments are "super-speed", "high-speed" and - "full-speed"; refer to usb/generic.txt - - dr_mode: Should be one of "host", "peripheral" or "otg". - - phys: reference to the USB PHY - - phy-names: from the *Generic PHY* bindings; - Supported names are: - - cdns3,usb2-phy - - cdns3,usb3-phy - - - cdns,on-chip-buff-size : size of memory intended as internal memory for endpoints - buffers expressed in KB - -Example: - usb@f3000000 { - compatible = "cdns,usb3"; - interrupts = <GIC_USB_IRQ 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_USB_IRQ 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_USB_IRQ 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host", "peripheral", "otg"; - reg = <0xf3000000 0x10000>, /* memory area for HOST registers */ - <0xf3010000 0x10000>, /* memory area for DEVICE registers */ - <0xf3020000 0x10000>; /* memory area for OTG/DRD registers */ - reg-names = "xhci", "dev", "otg"; - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "cdns3,usb2-phy", "cnds3,usb3-phy"; - }; diff --git a/dts/Bindings/usb/ci-hdrc-usb2.txt b/dts/Bindings/usb/ci-hdrc-usb2.txt index 51376cbe5f..a5c5db6a0b 100644 --- a/dts/Bindings/usb/ci-hdrc-usb2.txt +++ b/dts/Bindings/usb/ci-hdrc-usb2.txt @@ -100,6 +100,15 @@ i.mx specific properties It's recommended to specify the over current polarity. - power-active-high: power signal polarity is active high - external-vbus-divider: enables off-chip resistor divider for Vbus +- samsung,picophy-pre-emp-curr-control: HS Transmitter Pre-Emphasis Current + Control. This signal controls the amount of current sourced to the + USB_OTG*_DP and USB_OTG*_DN pins after a J-to-K or K-to-J transition. + The range is from 0x0 to 0x3, the default value is 0x1. + Details can refer to TXPREEMPAMPTUNE0 bits of USBNC_n_PHY_CFG1. +- samsung,picophy-dc-vol-level-adjust: HS DC Voltage Level Adjustment. + Adjust the high-speed transmitter DC level voltage. + The range is from 0x0 to 0xf, the default value is 0x3. + Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1. Example: diff --git a/dts/Bindings/usb/dwc2.yaml b/dts/Bindings/usb/dwc2.yaml index ffa157a0fc..e5ee51b7b4 100644 --- a/dts/Bindings/usb/dwc2.yaml +++ b/dts/Bindings/usb/dwc2.yaml @@ -39,6 +39,7 @@ properties: - amlogic,meson-g12a-usb - const: snps,dwc2 - const: amcc,dwc-otg + - const: apm,apm82181-dwc-otg - const: snps,dwc2 - const: st,stm32f4x9-fsotg - const: st,stm32f4x9-hsotg @@ -102,6 +103,10 @@ properties: dr_mode: enum: [host, peripheral, otg] + usb-role-switch: + $ref: /schemas/types.yaml#/definitions/flag + description: Support role switch. + g-rx-fifo-size: $ref: /schemas/types.yaml#/definitions/uint32 description: size of rx fifo size in gadget mode. diff --git a/dts/Bindings/usb/dwc3.txt b/dts/Bindings/usb/dwc3.txt index d03edf9d39..1aae2b6160 100644 --- a/dts/Bindings/usb/dwc3.txt +++ b/dts/Bindings/usb/dwc3.txt @@ -78,6 +78,9 @@ Optional properties: park mode are disabled. - snps,dis_metastability_quirk: when set, disable metastability workaround. CAUTION: use only if you are absolutely sure of it. + - snps,dis-split-quirk: when set, change the way URBs are handled by the + driver. Needed to avoid -EPROTO errors with usbhid + on some devices (Hikey 970). - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal utmi_l1_suspend_n, false when asserts utmi_sleep_n - snps,hird-threshold: HIRD threshold diff --git a/dts/Bindings/usb/intel,keembay-dwc3.yaml b/dts/Bindings/usb/intel,keembay-dwc3.yaml new file mode 100644 index 0000000000..dd32c10ce6 --- /dev/null +++ b/dts/Bindings/usb/intel,keembay-dwc3.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,keembay-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay DWC3 USB controller + +maintainers: + - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> + +properties: + compatible: + const: intel,keembay-dwc3 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: async_master + - const: ref + - const: alt_ref + - const: suspend + + ranges: true + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + +# Required child node: + +patternProperties: + "^dwc3@[0-9a-f]+$": + type: object + description: + A child node must exist to represent the core DWC3 IP block. + The content of the node is defined in dwc3.txt. + +required: + - compatible + - clocks + - clock-names + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #define KEEM_BAY_A53_AUX_USB + #define KEEM_BAY_A53_AUX_USB_REF + #define KEEM_BAY_A53_AUX_USB_ALT_REF + #define KEEM_BAY_A53_AUX_USB_SUSPEND + + usb { + compatible = "intel,keembay-dwc3"; + clocks = <&scmi_clk KEEM_BAY_A53_AUX_USB>, + <&scmi_clk KEEM_BAY_A53_AUX_USB_REF>, + <&scmi_clk KEEM_BAY_A53_AUX_USB_ALT_REF>, + <&scmi_clk KEEM_BAY_A53_AUX_USB_SUSPEND>; + clock-names = "async_master", "ref", "alt_ref", "suspend"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + dwc3@34000000 { + compatible = "snps,dwc3"; + reg = <0x34000000 0x10000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "peripheral"; + }; + }; diff --git a/dts/Bindings/usb/mediatek,mt6360-tcpc.yaml b/dts/Bindings/usb/mediatek,mt6360-tcpc.yaml new file mode 100644 index 0000000000..1e8e1c2218 --- /dev/null +++ b/dts/Bindings/usb/mediatek,mt6360-tcpc.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/mediatek,mt6360-tcpc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Mediatek MT6360 Type-C Port Switch and Power Delivery controller DT bindings + +maintainers: + - ChiYuan Huang <cy_huang@richtek.com> + +description: | + Mediatek MT6360 is a multi-functional device. It integrates charger, ADC, flash, RGB indicators, + regulators (BUCKs/LDOs), and TypeC Port Switch with Power Delivery controller. + This document only describes MT6360 Type-C Port Switch and Power Delivery controller. + +properties: + compatible: + enum: + - mediatek,mt6360-tcpc + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: PD_IRQB + + connector: + type: object + $ref: ../connector/usb-connector.yaml# + description: + Properties for usb c connector. + +additionalProperties: false + +required: + - compatible + - interrupts + - interrupt-names + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/usb/pd.h> + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + mt6360@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + tcpc { + compatible = "mediatek,mt6360-tcpc"; + interrupts-extended = <&gpio26 3 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "PD_IRQB"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>; + sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>; + op-sink-microwatt = <10000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&usb_hs>; + }; + }; + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&usb_ss>; + }; + }; + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&dp_aux>; + }; + }; + }; + }; + }; + }; + }; +... diff --git a/dts/Bindings/usb/nvidia,tegra-xudc.yaml b/dts/Bindings/usb/nvidia,tegra-xudc.yaml index 196589c933..e60e590dbe 100644 --- a/dts/Bindings/usb/nvidia,tegra-xudc.yaml +++ b/dts/Bindings/usb/nvidia,tegra-xudc.yaml @@ -155,6 +155,8 @@ allOf: clock-names: maxItems: 4 +additionalProperties: false + examples: - | #include <dt-bindings/clock/tegra210-car.h> diff --git a/dts/Bindings/usb/qcom,dwc3.yaml b/dts/Bindings/usb/qcom,dwc3.yaml index dac10848dd..2cf525d21e 100644 --- a/dts/Bindings/usb/qcom,dwc3.yaml +++ b/dts/Bindings/usb/qcom,dwc3.yaml @@ -121,6 +121,8 @@ required: - interrupts - interrupt-names +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,gcc-sdm845.h> diff --git a/dts/Bindings/usb/renesas,usb-xhci.yaml b/dts/Bindings/usb/renesas,usb-xhci.yaml index add9f7b66d..0f078bd0a3 100644 --- a/dts/Bindings/usb/renesas,usb-xhci.yaml +++ b/dts/Bindings/usb/renesas,usb-xhci.yaml @@ -30,6 +30,7 @@ properties: - renesas,xhci-r8a774a1 # RZ/G2M - renesas,xhci-r8a774b1 # RZ/G2N - renesas,xhci-r8a774c0 # RZ/G2E + - renesas,xhci-r8a774e1 # RZ/G2H - renesas,xhci-r8a7795 # R-Car H3 - renesas,xhci-r8a7796 # R-Car M3-W - renesas,xhci-r8a77961 # R-Car M3-W+ diff --git a/dts/Bindings/usb/renesas,usb3-peri.yaml b/dts/Bindings/usb/renesas,usb3-peri.yaml index e3cdeab119..929a3f413b 100644 --- a/dts/Bindings/usb/renesas,usb3-peri.yaml +++ b/dts/Bindings/usb/renesas,usb3-peri.yaml @@ -16,6 +16,7 @@ properties: - renesas,r8a774a1-usb3-peri # RZ/G2M - renesas,r8a774b1-usb3-peri # RZ/G2N - renesas,r8a774c0-usb3-peri # RZ/G2E + - renesas,r8a774e1-usb3-peri # RZ/G2H - renesas,r8a7795-usb3-peri # R-Car H3 - renesas,r8a7796-usb3-peri # R-Car M3-W - renesas,r8a77961-usb3-peri # R-Car M3-W+ @@ -52,11 +53,24 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: phandle of a companion. - port: + ports: description: | any connector to the data bus of this controller should be modelled using the OF graph bindings specified, if the "usb-role-switch" property is used. + type: object + properties: + port@0: + type: object + description: High Speed (HS) data bus. + + port@1: + type: object + description: Super Speed (SS) data bus. + + required: + - port@0 + - port@1 required: - compatible @@ -79,9 +93,20 @@ examples: companion = <&xhci0>; usb-role-switch; - port { - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_ep>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; }; }; diff --git a/dts/Bindings/usb/renesas,usbhs.yaml b/dts/Bindings/usb/renesas,usbhs.yaml index af4826fb68..737c1f47b7 100644 --- a/dts/Bindings/usb/renesas,usbhs.yaml +++ b/dts/Bindings/usb/renesas,usbhs.yaml @@ -39,6 +39,7 @@ properties: - renesas,usbhs-r8a774a1 # RZ/G2M - renesas,usbhs-r8a774b1 # RZ/G2N - renesas,usbhs-r8a774c0 # RZ/G2E + - renesas,usbhs-r8a774e1 # RZ/G2H - renesas,usbhs-r8a7795 # R-Car H3 - renesas,usbhs-r8a7796 # R-Car M3-W - renesas,usbhs-r8a77961 # R-Car M3-W+ diff --git a/dts/Bindings/usb/ti,hd3ss3220.txt b/dts/Bindings/usb/ti,hd3ss3220.txt deleted file mode 100644 index 2bd21b22ce..0000000000 --- a/dts/Bindings/usb/ti,hd3ss3220.txt +++ /dev/null @@ -1,38 +0,0 @@ -TI HD3SS3220 TypeC DRP Port Controller. - -Required properties: - - compatible: Must be "ti,hd3ss3220". - - reg: I2C slave address, must be 0x47 or 0x67 based on ADDR pin. - - interrupts: An interrupt specifier. - -Required sub-node: - - connector: The "usb-c-connector" attached to the hd3ss3220 chip. The - bindings of the connector node are specified in: - - Documentation/devicetree/bindings/connector/usb-connector.yaml - -Example: -hd3ss3220@47 { - compatible = "ti,hd3ss3220"; - reg = <0x47>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hd3ss3220_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; - }; - }; - }; -}; diff --git a/dts/Bindings/usb/ti,hd3ss3220.yaml b/dts/Bindings/usb/ti,hd3ss3220.yaml new file mode 100644 index 0000000000..5fe9e6211b --- /dev/null +++ b/dts/Bindings/usb/ti,hd3ss3220.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,hd3ss3220.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI HD3SS3220 TypeC DRP Port Controller + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: |- + HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel + Configuration (CC) logic and 5V VCONN sourcing for ecosystems implementing USB Type-C. The + HD3SS3220 can be configured as a Downstream Facing Port (DFP), Upstream Facing Port (UFP) or a + Dual Role Port (DRP) making it ideal for any application. + +properties: + compatible: + const: ti,hd3ss3220 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports: + description: OF graph bindings (specified in bindings/graph.txt) that model + SS data bus to the SS capable connector. + type: object + properties: + port@0: + type: object + description: Super Speed (SS) MUX inputs connected to SS capable connector. + $ref: /connector/usb-connector.yaml#/properties/ports/properties/port@1 + + port@1: + type: object + description: Output of 2:1 MUX connected to Super Speed (SS) data bus. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + hd3ss3220@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + interrupt-parent = <&gpio6>; + interrupts = <3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/usb/ti,j721e-usb.yaml b/dts/Bindings/usb/ti,j721e-usb.yaml index 484fc1091d..388245b91a 100644 --- a/dts/Bindings/usb/ti,j721e-usb.yaml +++ b/dts/Bindings/usb/ti,j721e-usb.yaml @@ -46,6 +46,22 @@ properties: VBUS pin of the SoC via a 1/3 voltage divider. type: boolean + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + +patternProperties: + "^usb@": + type: object + required: - compatible - reg @@ -53,6 +69,8 @@ required: - clocks - clock-names +additionalProperties: false + examples: - | #include <dt-bindings/soc/ti,sci_pm_domain.h> diff --git a/dts/Bindings/usb/ti,tps6598x.yaml b/dts/Bindings/usb/ti,tps6598x.yaml index 8eaf4b6c47..f6819bf2a3 100644 --- a/dts/Bindings/usb/ti,tps6598x.yaml +++ b/dts/Bindings/usb/ti,tps6598x.yaml @@ -32,6 +32,8 @@ required: - interrupts - interrupt-names +additionalProperties: true + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/dts/Bindings/usb/usb-hcd.yaml b/dts/Bindings/usb/usb-hcd.yaml index 7263b7f2b5..b545b087b3 100644 --- a/dts/Bindings/usb/usb-hcd.yaml +++ b/dts/Bindings/usb/usb-hcd.yaml @@ -22,6 +22,8 @@ properties: description: Name specifier for the USB PHY +additionalProperties: true + examples: - | usb { |